1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc; 16 }; 17 18 secure_otp: secure_otp@0xff5d0000 { 19 compatible = "rockchip,rv1126-secure-otp"; 20 reg = <0xff5d0000 0x4000>; 21 secure_conf = <0xfe0a0008>; 22 }; 23}; 24 25&psci { 26 u-boot,dm-pre-reloc; 27 status = "okay"; 28}; 29 30&uart2 { 31 clock-frequency = <24000000>; 32 u-boot,dm-spl; 33 /delete-property/ pinctrl-names; 34 /delete-property/ pinctrl-0; 35}; 36 37&sdmmc { 38 u-boot,dm-spl; 39 status = "okay"; 40}; 41 42&sdmmc0 { 43 u-boot,dm-spl; 44}; 45 46&sdmmc0_bus4 { 47 u-boot,dm-spl; 48}; 49 50&sdmmc0_clk { 51 u-boot,dm-spl; 52}; 53 54&sdmmc0_cmd { 55 u-boot,dm-spl; 56}; 57 58&sdmmc0_det { 59 u-boot,dm-spl; 60}; 61 62&emmc { 63 mmc-ecsd = <0x0020f000>; 64 u-boot,dm-spl; 65 /delete-property/ pinctrl-names; 66 /delete-property/ pinctrl-0; 67}; 68 69&pmu { 70 u-boot,dm-spl; 71}; 72 73&pmugrf { 74 u-boot,dm-spl; 75}; 76 77&pmucru { 78 u-boot,dm-spl; 79}; 80 81&cru { 82 u-boot,dm-spl; 83 /delete-property/ assigned-clocks; 84 /delete-property/ assigned-clock-rates; 85 /delete-property/ assigned-clock-parents; 86}; 87 88&crypto { 89 u-boot,dm-spl; 90 status = "okay"; 91}; 92 93&grf { 94 u-boot,dm-spl; 95}; 96 97&saradc { 98 u-boot,dm-spl; 99 status = "okay"; 100}; 101 102&sfc { 103 u-boot,dm-spl; 104 /delete-property/ pinctrl-names; 105 /delete-property/ pinctrl-0; 106 /delete-property/ assigned-clocks; 107 /delete-property/ assigned-clock-rates; 108 status = "okay"; 109 110 #address-cells = <1>; 111 #size-cells = <0>; 112 spi_nand: flash@0 { 113 u-boot,dm-spl; 114 compatible = "spi-nand"; 115 reg = <0>; 116 spi-tx-bus-width = <1>; 117 spi-rx-bus-width = <4>; 118 spi-max-frequency = <96000000>; 119 }; 120 121 spi_nor: flash@1 { 122 u-boot,dm-spl; 123 compatible = "jedec,spi-nor"; 124 label = "sfc_nor"; 125 reg = <0>; 126 spi-tx-bus-width = <1>; 127 spi-rx-bus-width = <4>; 128 spi-max-frequency = <100000000>; 129 }; 130}; 131 132&nandc { 133 u-boot,dm-spl; 134 /delete-property/ pinctrl-names; 135 /delete-property/ pinctrl-0; 136 status = "okay"; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 140 nand@0 { 141 u-boot,dm-spl; 142 reg = <0>; 143 nand-ecc-mode = "hw"; 144 nand-ecc-strength = <16>; 145 nand-ecc-step-size = <1024>; 146 }; 147}; 148 149&hw_decompress { 150 u-boot,dm-spl; 151 status = "okay"; 152}; 153 154&secure_otp { 155 u-boot,dm-spl; 156 status = "okay"; 157}; 158 159&i2c0 { 160 u-boot,dm-spl; 161 status = "okay"; 162 rk817_fg@20 { 163 u-boot,dm-spl; 164 compatible = "rk817,battery"; 165 reg = <0x20>; 166 bat_res_up = <140>; 167 bat_res_down = <20>; 168 }; 169}; 170 171&u2phy0 { 172 u-boot,dm-pre-reloc; 173 status = "okay"; 174}; 175 176&u2phy_otg { 177 u-boot,dm-pre-reloc; 178 status = "okay"; 179}; 180 181&usbdrd { 182 u-boot,dm-pre-reloc; 183 status = "okay"; 184}; 185 186&usbdrd_dwc3 { 187 u-boot,dm-pre-reloc; 188 status = "okay"; 189}; 190 191&pinctrl { 192 u-boot,dm-spl; 193 status = "okay"; 194}; 195 196&gpio0 { 197 u-boot,dm-spl; 198 status = "okay"; 199}; 200 201&gpio1 { 202 u-boot,dm-spl; 203 status = "okay"; 204}; 205 206&pcfg_pull_up_drv_level_2 { 207 u-boot,dm-spl; 208}; 209 210&pcfg_pull_none { 211 u-boot,dm-spl; 212}; 213 214&gpio3 { 215 u-boot,dm-pre-reloc; 216 status = "okay"; 217}; 218 219&gmac { 220 u-boot,dm-pre-reloc; 221 222 phy-mode = "rgmii"; 223 clock_in_out = "input"; 224 225 snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; 226 snps,reset-active-low; 227 /* Reset time is 20ms, 100ms for rtl8211f */ 228 snps,reset-delays-us = <0 20000 100000>; 229 230 assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>; 231 assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 232 assigned-clock-rates = <125000000>, <0>, <25000000>; 233 234 pinctrl-names = "default"; 235 pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; 236 237 tx_delay = <0x2a>; 238 rx_delay = <0x1a>; 239 240 phy-handle = <&phy>; 241 status = "okay"; 242}; 243 244&mdio { 245 u-boot,dm-pre-reloc; 246 status = "okay"; 247 248 phy: phy@0 { 249 compatible = "ethernet-phy-ieee802.3-c22"; 250 u-boot,dm-pre-reloc; 251 reg = <0x0>; 252 clocks = <&cru CLK_GMAC_ETHERNET_OUT>; 253 }; 254}; 255 256&stmmac_axi_setup { 257 u-boot,dm-pre-reloc; 258 status = "okay"; 259 queue0 { 260 u-boot,dm-pre-reloc; 261 }; 262}; 263 264&mtl_rx_setup { 265 u-boot,dm-pre-reloc; 266 status = "okay"; 267 queue0 { 268 u-boot,dm-pre-reloc; 269 }; 270}; 271 272&mtl_tx_setup { 273 u-boot,dm-pre-reloc; 274 status = "okay"; 275}; 276 277&gmac_clkin_m0 { 278 u-boot,dm-pre-reloc; 279 status = "okay"; 280}; 281 282&gmac_clkini_m1 { 283 u-boot,dm-pre-reloc; 284 status = "okay"; 285}; 286 287&rgmiim1_pins { 288 u-boot,dm-pre-reloc; 289 status = "okay"; 290}; 291 292&rng { 293 u-boot,dm-spl; 294 status = "okay"; 295}; 296 297&clk_out_ethernetm1_pins{ 298 u-boot,dm-pre-reloc; 299 status = "okay"; 300}; 301 302&pcfg_pull_none { 303 u-boot,dm-pre-reloc; 304 status = "okay"; 305}; 306 307&pcfg_pull_none_drv_level_12 { 308 u-boot,dm-pre-reloc; 309 status = "okay"; 310}; 311 312&wdt { 313 u-boot,dm-pre-reloc; 314 status = "okay"; 315}; 316