1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc; 16 }; 17 18 secure-otp@ff5d0000 { 19 compatible = "rockchip,rv1126-secure-otp"; 20 reg = <0xff5d0000 0x4000>; 21 secure_conf = <0xfe0a0008>; 22 u-boot,dm-spl; 23 status = "okay"; 24 }; 25}; 26 27&psci { 28 u-boot,dm-pre-reloc; 29 status = "okay"; 30}; 31 32&uart2 { 33 clock-frequency = <24000000>; 34 u-boot,dm-spl; 35 /delete-property/ pinctrl-names; 36 /delete-property/ pinctrl-0; 37}; 38 39&sdmmc { 40 u-boot,dm-spl; 41 pwr-en-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; 42 status = "okay"; 43}; 44 45&sdmmc0 { 46 u-boot,dm-spl; 47}; 48 49&sdmmc0_bus4 { 50 u-boot,dm-spl; 51}; 52 53&sdmmc0_clk { 54 u-boot,dm-spl; 55}; 56 57&sdmmc0_cmd { 58 u-boot,dm-spl; 59}; 60 61&sdmmc0_det { 62 u-boot,dm-spl; 63}; 64 65&sdmmc0_idle_pins { 66 u-boot,dm-spl; 67}; 68 69&sdmmc1_idle_pins { 70 u-boot,dm-spl; 71}; 72 73&emmc { 74 mmc-ecsd = <0x0020f000>; 75 u-boot,dm-spl; 76 /delete-property/ pinctrl-names; 77 /delete-property/ pinctrl-0; 78}; 79 80&pmu { 81 u-boot,dm-spl; 82}; 83 84&pmugrf { 85 u-boot,dm-spl; 86}; 87 88&pmucru { 89 u-boot,dm-spl; 90}; 91 92&cru { 93 u-boot,dm-spl; 94 /delete-property/ assigned-clocks; 95 /delete-property/ assigned-clock-rates; 96 /delete-property/ assigned-clock-parents; 97}; 98 99&crypto { 100 u-boot,dm-spl; 101 status = "okay"; 102}; 103 104&grf { 105 u-boot,dm-spl; 106}; 107 108&saradc { 109 u-boot,dm-spl; 110 status = "okay"; 111}; 112 113&sfc { 114 u-boot,dm-spl; 115 /delete-property/ pinctrl-names; 116 /delete-property/ pinctrl-0; 117 /delete-property/ assigned-clocks; 118 /delete-property/ assigned-clock-rates; 119 status = "okay"; 120 121 #address-cells = <1>; 122 #size-cells = <0>; 123 spi_nand: flash@0 { 124 u-boot,dm-spl; 125 compatible = "spi-nand"; 126 reg = <0>; 127 spi-tx-bus-width = <1>; 128 spi-rx-bus-width = <4>; 129 spi-max-frequency = <96000000>; 130 }; 131 132 spi_nor: flash@1 { 133 u-boot,dm-spl; 134 compatible = "jedec,spi-nor"; 135 label = "sfc_nor"; 136 reg = <0>; 137 spi-tx-bus-width = <1>; 138 spi-rx-bus-width = <4>; 139 spi-max-frequency = <100000000>; 140 }; 141}; 142 143&nandc { 144 u-boot,dm-spl; 145 /delete-property/ pinctrl-names; 146 /delete-property/ pinctrl-0; 147 status = "okay"; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 151 nand@0 { 152 u-boot,dm-spl; 153 reg = <0>; 154 nand-ecc-mode = "hw"; 155 nand-ecc-strength = <16>; 156 nand-ecc-step-size = <1024>; 157 }; 158}; 159 160&hw_decompress { 161 u-boot,dm-spl; 162 status = "okay"; 163}; 164 165&i2c0 { 166 u-boot,dm-spl; 167 status = "okay"; 168 rk817_fg@20 { 169 u-boot,dm-spl; 170 compatible = "rk817,battery"; 171 reg = <0x20>; 172 bat_res_up = <140>; 173 bat_res_down = <20>; 174 }; 175}; 176 177&u2phy0 { 178 u-boot,dm-pre-reloc; 179 status = "okay"; 180}; 181 182&u2phy_otg { 183 u-boot,dm-pre-reloc; 184 status = "okay"; 185}; 186 187&pinctrl { 188 u-boot,dm-spl; 189 status = "okay"; 190}; 191 192&gpio0 { 193 u-boot,dm-spl; 194 status = "okay"; 195}; 196 197&gpio1 { 198 u-boot,dm-spl; 199 status = "okay"; 200}; 201 202&pcfg_pull_up_drv_level_2 { 203 u-boot,dm-spl; 204}; 205 206&pcfg_pull_none { 207 u-boot,dm-spl; 208}; 209 210&pcfg_pull_down{ 211 u-boot,dm-spl; 212}; 213 214&pcfg_pull_up{ 215 u-boot,dm-spl; 216}; 217 218&gpio3 { 219 u-boot,dm-pre-reloc; 220 status = "okay"; 221}; 222 223&gmac { 224 u-boot,dm-pre-reloc; 225 226 phy-mode = "rgmii"; 227 clock_in_out = "input"; 228 229 snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; 230 snps,reset-active-low; 231 /* Reset time is 20ms, 100ms for rtl8211f */ 232 snps,reset-delays-us = <0 20000 100000>; 233 234 assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>; 235 assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 236 assigned-clock-rates = <125000000>, <0>, <25000000>; 237 238 pinctrl-names = "default"; 239 pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; 240 241 tx_delay = <0x2a>; 242 rx_delay = <0x1a>; 243 244 phy-handle = <&phy>; 245 status = "okay"; 246}; 247 248&mdio { 249 u-boot,dm-pre-reloc; 250 status = "okay"; 251 252 phy: phy@0 { 253 compatible = "ethernet-phy-ieee802.3-c22"; 254 u-boot,dm-pre-reloc; 255 reg = <0x0>; 256 clocks = <&cru CLK_GMAC_ETHERNET_OUT>; 257 }; 258}; 259 260&stmmac_axi_setup { 261 u-boot,dm-pre-reloc; 262 status = "okay"; 263 queue0 { 264 u-boot,dm-pre-reloc; 265 }; 266}; 267 268&mtl_rx_setup { 269 u-boot,dm-pre-reloc; 270 status = "okay"; 271 queue0 { 272 u-boot,dm-pre-reloc; 273 }; 274}; 275 276&mtl_tx_setup { 277 u-boot,dm-pre-reloc; 278 status = "okay"; 279}; 280 281&gmac_clkin_m0 { 282 u-boot,dm-pre-reloc; 283 status = "okay"; 284}; 285 286&gmac_clkini_m1 { 287 u-boot,dm-pre-reloc; 288 status = "okay"; 289}; 290 291&rgmiim1_pins { 292 u-boot,dm-pre-reloc; 293 status = "okay"; 294}; 295 296&rng { 297 u-boot,dm-spl; 298 status = "okay"; 299}; 300 301&clk_out_ethernetm1_pins{ 302 u-boot,dm-pre-reloc; 303 status = "okay"; 304}; 305 306&pcfg_pull_none { 307 u-boot,dm-pre-reloc; 308 status = "okay"; 309}; 310 311&pcfg_pull_none_drv_level_12 { 312 u-boot,dm-pre-reloc; 313 status = "okay"; 314}; 315 316&wdt { 317 u-boot,dm-pre-reloc; 318 status = "okay"; 319}; 320