1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &spi_nand, &spi_nor, &nandc, &emmc; 16 }; 17 18 crypto: crypto@ff500000 { 19 compatible = "rockchip,rv1126-crypto"; 20 reg = <0xff500000 0x10000>; 21 clock-names = "sclk_crypto", "sclk_crypto_apk"; 22 clocks = <&cru CLK_CRYPTO_CORE>, <&cru CLK_CRYPTO_PKA>; 23 clock-frequency = <200000000>, <300000000>; 24 }; 25 26 secure_otp: secure_otp@0xff5d0000 { 27 compatible = "rockchip,rv1126-secure-otp"; 28 reg = <0xff5d0000 0x4000>; 29 secure_conf = <0xfe0a0008>; 30 }; 31}; 32 33&uart2 { 34 clock-frequency = <24000000>; 35 u-boot,dm-spl; 36 /delete-property/ pinctrl-names; 37 /delete-property/ pinctrl-0; 38}; 39 40&sdmmc { 41 u-boot,dm-spl; 42 /delete-property/ pinctrl-names; 43 /delete-property/ pinctrl-0; 44}; 45 46&emmc { 47 mmc-ecsd = <0x0020f000>; 48 u-boot,dm-spl; 49 /delete-property/ pinctrl-names; 50 /delete-property/ pinctrl-0; 51}; 52 53&pmu { 54 u-boot,dm-spl; 55}; 56 57&pmugrf { 58 u-boot,dm-spl; 59}; 60 61&pmucru { 62 u-boot,dm-spl; 63}; 64 65&cru { 66 u-boot,dm-spl; 67 /delete-property/ assigned-clocks; 68 /delete-property/ assigned-clock-rates; 69 /delete-property/ assigned-clock-parents; 70}; 71 72&crypto { 73 u-boot,dm-spl; 74 status = "okay"; 75}; 76 77&grf { 78 u-boot,dm-spl; 79}; 80 81&saradc { 82 u-boot,dm-spl; 83 status = "okay"; 84}; 85 86&sfc { 87 u-boot,dm-spl; 88 /delete-property/ assigned-clocks; 89 /delete-property/ assigned-clock-rates; 90 status = "okay"; 91 92 #address-cells = <1>; 93 #size-cells = <0>; 94 spi_nand: flash@0 { 95 u-boot,dm-spl; 96 compatible = "spi-nand"; 97 reg = <0>; 98 spi-tx-bus-width = <1>; 99 spi-rx-bus-width = <4>; 100 spi-max-frequency = <96000000>; 101 }; 102 103 spi_nor: flash@1 { 104 u-boot,dm-spl; 105 compatible = "jedec,spi-nor"; 106 label = "sfc_nor"; 107 reg = <0>; 108 spi-tx-bus-width = <1>; 109 spi-rx-bus-width = <4>; 110 spi-max-frequency = <96000000>; 111 }; 112}; 113 114&nandc { 115 u-boot,dm-spl; 116 status = "okay"; 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 nand@0 { 121 u-boot,dm-spl; 122 reg = <0>; 123 nand-ecc-mode = "hw_syndrome"; 124 nand-ecc-strength = <16>; 125 nand-ecc-step-size = <1024>; 126 }; 127}; 128 129&hw_decompress { 130 u-boot,dm-spl; 131 status = "okay"; 132}; 133 134&secure_otp { 135 u-boot,dm-spl; 136 status = "okay"; 137}; 138 139&u2phy0 { 140 u-boot,dm-pre-reloc; 141 status = "okay"; 142}; 143 144&u2phy_otg { 145 u-boot,dm-pre-reloc; 146 status = "okay"; 147}; 148 149&usbdrd { 150 u-boot,dm-pre-reloc; 151 status = "okay"; 152}; 153 154&usbdrd_dwc3 { 155 u-boot,dm-pre-reloc; 156 status = "okay"; 157}; 158 159&pinctrl { 160 u-boot,dm-pre-reloc; 161 status = "okay"; 162}; 163 164&gpio3 { 165 u-boot,dm-pre-reloc; 166 status = "okay"; 167}; 168 169&gmac { 170 u-boot,dm-pre-reloc; 171 172 phy-mode = "rgmii"; 173 clock_in_out = "input"; 174 175 snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; 176 snps,reset-active-low; 177 /* Reset time is 20ms, 100ms for rtl8211f */ 178 snps,reset-delays-us = <0 20000 100000>; 179 180 assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>; 181 assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 182 assigned-clock-rates = <125000000>, <0>, <25000000>; 183 184 pinctrl-names = "default"; 185 pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; 186 187 tx_delay = <0x2a>; 188 rx_delay = <0x1a>; 189 190 phy-handle = <&phy>; 191 status = "okay"; 192}; 193 194&mdio { 195 u-boot,dm-pre-reloc; 196 status = "okay"; 197 198 phy: phy@0 { 199 compatible = "ethernet-phy-ieee802.3-c22"; 200 u-boot,dm-pre-reloc; 201 reg = <0x0>; 202 clocks = <&cru CLK_GMAC_ETHERNET_OUT>; 203 }; 204}; 205 206&stmmac_axi_setup { 207 u-boot,dm-pre-reloc; 208 status = "okay"; 209 queue0 { 210 u-boot,dm-pre-reloc; 211 }; 212}; 213 214&mtl_rx_setup { 215 u-boot,dm-pre-reloc; 216 status = "okay"; 217 queue0 { 218 u-boot,dm-pre-reloc; 219 }; 220}; 221 222&mtl_tx_setup { 223 u-boot,dm-pre-reloc; 224 status = "okay"; 225}; 226 227&gmac_clkin_m0 { 228 u-boot,dm-pre-reloc; 229 status = "okay"; 230}; 231 232&gmac_clkini_m1 { 233 u-boot,dm-pre-reloc; 234 status = "okay"; 235}; 236 237&rgmiim1_pins { 238 u-boot,dm-pre-reloc; 239 status = "okay"; 240}; 241 242&clk_out_ethernetm1_pins{ 243 u-boot,dm-pre-reloc; 244 status = "okay"; 245}; 246 247&pcfg_pull_none { 248 u-boot,dm-pre-reloc; 249 status = "okay"; 250}; 251 252&pcfg_pull_none_drv_level_12 { 253 u-boot,dm-pre-reloc; 254 status = "okay"; 255}; 256 257