1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sfc, &nandc, &emmc; 16 }; 17}; 18 19&uart2 { 20 clock-frequency = <24000000>; 21 u-boot,dm-spl; 22}; 23 24&sdmmc { 25 u-boot,dm-spl; 26}; 27 28&emmc { 29 u-boot,dm-spl; 30}; 31 32&pmu { 33 u-boot,dm-spl; 34}; 35 36&pmugrf { 37 u-boot,dm-spl; 38}; 39 40&pmucru { 41 u-boot,dm-spl; 42}; 43 44&cru { 45 u-boot,dm-spl; 46}; 47 48&grf { 49 u-boot,dm-spl; 50}; 51 52&saradc { 53 u-boot,dm-spl; 54 status = "okay"; 55}; 56 57&sfc { 58 u-boot,dm-spl; 59 status = "okay"; 60 61 #address-cells = <1>; 62 #size-cells = <0>; 63 spi_nand: flash@0 { 64 u-boot,dm-spl; 65 compatible = "spi-nand"; 66 reg = <0>; 67 spi-tx-bus-width = <1>; 68 spi-rx-bus-width = <4>; 69 spi-max-frequency = <96000000>; 70 }; 71 72 spi_nor: flash@1 { 73 u-boot,dm-spl; 74 compatible = "jedec,spi-nor"; 75 reg = <0>; 76 spi-tx-bus-width = <1>; 77 spi-rx-bus-width = <4>; 78 spi-max-frequency = <96000000>; 79 }; 80}; 81 82&nandc { 83 u-boot,dm-spl; 84 status = "okay"; 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 nand@0 { 89 u-boot,dm-spl; 90 reg = <0>; 91 nand-ecc-mode = "hw_syndrome"; 92 nand-ecc-strength = <16>; 93 nand-ecc-step-size = <1024>; 94 }; 95}; 96 97&usbdrd { 98 u-boot,dm-pre-reloc; 99 status = "okay"; 100}; 101 102&usbdrd_dwc3 { 103 u-boot,dm-pre-reloc; 104 /delete-property/ phys; 105 status = "okay"; 106}; 107