1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc; 16 }; 17 18 secure_otp: secure_otp@0xff5d0000 { 19 compatible = "rockchip,rv1126-secure-otp"; 20 reg = <0xff5d0000 0x4000>; 21 secure_conf = <0xfe0a0008>; 22 }; 23}; 24 25&uart2 { 26 clock-frequency = <24000000>; 27 u-boot,dm-spl; 28 /delete-property/ pinctrl-names; 29 /delete-property/ pinctrl-0; 30}; 31 32&sdmmc { 33 u-boot,dm-spl; 34 status = "okay"; 35}; 36 37&sdmmc0 { 38 u-boot,dm-spl; 39}; 40 41&sdmmc0_bus4 { 42 u-boot,dm-spl; 43}; 44 45&sdmmc0_clk { 46 u-boot,dm-spl; 47}; 48 49&sdmmc0_cmd { 50 u-boot,dm-spl; 51}; 52 53&sdmmc0_det { 54 u-boot,dm-spl; 55}; 56 57&emmc { 58 mmc-ecsd = <0x0020f000>; 59 u-boot,dm-spl; 60 /delete-property/ pinctrl-names; 61 /delete-property/ pinctrl-0; 62}; 63 64&pmu { 65 u-boot,dm-spl; 66}; 67 68&pmugrf { 69 u-boot,dm-spl; 70}; 71 72&pmucru { 73 u-boot,dm-spl; 74}; 75 76&cru { 77 u-boot,dm-spl; 78 /delete-property/ assigned-clocks; 79 /delete-property/ assigned-clock-rates; 80 /delete-property/ assigned-clock-parents; 81}; 82 83&crypto { 84 u-boot,dm-spl; 85 status = "okay"; 86}; 87 88&grf { 89 u-boot,dm-spl; 90}; 91 92&saradc { 93 u-boot,dm-spl; 94 status = "okay"; 95}; 96 97&sfc { 98 u-boot,dm-spl; 99 /delete-property/ pinctrl-names; 100 /delete-property/ pinctrl-0; 101 /delete-property/ assigned-clocks; 102 /delete-property/ assigned-clock-rates; 103 status = "okay"; 104 105 #address-cells = <1>; 106 #size-cells = <0>; 107 spi_nand: flash@0 { 108 u-boot,dm-spl; 109 compatible = "spi-nand"; 110 reg = <0>; 111 spi-tx-bus-width = <1>; 112 spi-rx-bus-width = <4>; 113 spi-max-frequency = <96000000>; 114 }; 115 116 spi_nor: flash@1 { 117 u-boot,dm-spl; 118 compatible = "jedec,spi-nor"; 119 label = "sfc_nor"; 120 reg = <0>; 121 spi-tx-bus-width = <1>; 122 spi-rx-bus-width = <4>; 123 spi-max-frequency = <100000000>; 124 }; 125}; 126 127&nandc { 128 u-boot,dm-spl; 129 /delete-property/ pinctrl-names; 130 /delete-property/ pinctrl-0; 131 status = "okay"; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 135 nand@0 { 136 u-boot,dm-spl; 137 reg = <0>; 138 nand-ecc-mode = "hw_syndrome"; 139 nand-ecc-strength = <16>; 140 nand-ecc-step-size = <1024>; 141 }; 142}; 143 144&hw_decompress { 145 u-boot,dm-spl; 146 status = "okay"; 147}; 148 149&secure_otp { 150 u-boot,dm-spl; 151 status = "okay"; 152}; 153 154&u2phy0 { 155 u-boot,dm-pre-reloc; 156 status = "okay"; 157}; 158 159&u2phy_otg { 160 u-boot,dm-pre-reloc; 161 status = "okay"; 162}; 163 164&usbdrd { 165 u-boot,dm-pre-reloc; 166 status = "okay"; 167}; 168 169&usbdrd_dwc3 { 170 u-boot,dm-pre-reloc; 171 status = "okay"; 172}; 173 174&pinctrl { 175 u-boot,dm-spl; 176 status = "okay"; 177}; 178 179&gpio1 { 180 u-boot,dm-spl; 181 status = "okay"; 182}; 183 184&pcfg_pull_up_drv_level_2 { 185 u-boot,dm-spl; 186}; 187 188&pcfg_pull_none { 189 u-boot,dm-spl; 190}; 191 192&gpio3 { 193 u-boot,dm-pre-reloc; 194 status = "okay"; 195}; 196 197&gmac { 198 u-boot,dm-pre-reloc; 199 200 phy-mode = "rgmii"; 201 clock_in_out = "input"; 202 203 snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; 204 snps,reset-active-low; 205 /* Reset time is 20ms, 100ms for rtl8211f */ 206 snps,reset-delays-us = <0 20000 100000>; 207 208 assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>; 209 assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 210 assigned-clock-rates = <125000000>, <0>, <25000000>; 211 212 pinctrl-names = "default"; 213 pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; 214 215 tx_delay = <0x2a>; 216 rx_delay = <0x1a>; 217 218 phy-handle = <&phy>; 219 status = "okay"; 220}; 221 222&mdio { 223 u-boot,dm-pre-reloc; 224 status = "okay"; 225 226 phy: phy@0 { 227 compatible = "ethernet-phy-ieee802.3-c22"; 228 u-boot,dm-pre-reloc; 229 reg = <0x0>; 230 clocks = <&cru CLK_GMAC_ETHERNET_OUT>; 231 }; 232}; 233 234&stmmac_axi_setup { 235 u-boot,dm-pre-reloc; 236 status = "okay"; 237 queue0 { 238 u-boot,dm-pre-reloc; 239 }; 240}; 241 242&mtl_rx_setup { 243 u-boot,dm-pre-reloc; 244 status = "okay"; 245 queue0 { 246 u-boot,dm-pre-reloc; 247 }; 248}; 249 250&mtl_tx_setup { 251 u-boot,dm-pre-reloc; 252 status = "okay"; 253}; 254 255&gmac_clkin_m0 { 256 u-boot,dm-pre-reloc; 257 status = "okay"; 258}; 259 260&gmac_clkini_m1 { 261 u-boot,dm-pre-reloc; 262 status = "okay"; 263}; 264 265&rgmiim1_pins { 266 u-boot,dm-pre-reloc; 267 status = "okay"; 268}; 269 270&rng { 271 u-boot,dm-spl; 272 status = "okay"; 273}; 274 275&clk_out_ethernetm1_pins{ 276 u-boot,dm-pre-reloc; 277 status = "okay"; 278}; 279 280&pcfg_pull_none { 281 u-boot,dm-pre-reloc; 282 status = "okay"; 283}; 284 285&pcfg_pull_none_drv_level_12 { 286 u-boot,dm-pre-reloc; 287 status = "okay"; 288}; 289 290&wdt { 291 u-boot,dm-pre-reloc; 292 status = "okay"; 293}; 294