1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &spi_nand, &spi_nor, &nandc, &emmc; 16 }; 17 18 crypto: crypto@ff500000 { 19 compatible = "rockchip,rv1126-crypto"; 20 reg = <0xff500000 0x10000>; 21 clock-names = "sclk_crypto", "sclk_crypto_apk"; 22 clocks = <&cru CLK_CRYPTO_CORE>, <&cru CLK_CRYPTO_PKA>; 23 clock-frequency = <200000000>, <300000000>; 24 }; 25 26 secure_otp: secure_otp@0xff5d0000 { 27 compatible = "rockchip,rv1126-secure-otp"; 28 reg = <0xff5d0000 0x4000>; 29 secure_conf = <0xfe0a0008>; 30 }; 31}; 32 33&uart2 { 34 clock-frequency = <24000000>; 35 u-boot,dm-spl; 36}; 37 38&sdmmc { 39 u-boot,dm-spl; 40}; 41 42&emmc { 43 mmc-ecsd = <0x0020f000>; 44 u-boot,dm-spl; 45}; 46 47&pmu { 48 u-boot,dm-spl; 49}; 50 51&pmugrf { 52 u-boot,dm-spl; 53}; 54 55&pmucru { 56 u-boot,dm-spl; 57}; 58 59&cru { 60 u-boot,dm-spl; 61}; 62 63&crypto { 64 u-boot,dm-spl; 65 status = "okay"; 66}; 67 68&grf { 69 u-boot,dm-spl; 70}; 71 72&saradc { 73 u-boot,dm-spl; 74 status = "okay"; 75}; 76 77&sfc { 78 u-boot,dm-spl; 79 status = "okay"; 80 81 #address-cells = <1>; 82 #size-cells = <0>; 83 spi_nand: flash@0 { 84 u-boot,dm-spl; 85 compatible = "spi-nand"; 86 reg = <0>; 87 spi-tx-bus-width = <1>; 88 spi-rx-bus-width = <4>; 89 spi-max-frequency = <96000000>; 90 }; 91 92 spi_nor: flash@1 { 93 u-boot,dm-spl; 94 compatible = "jedec,spi-nor"; 95 reg = <0>; 96 spi-tx-bus-width = <1>; 97 spi-rx-bus-width = <4>; 98 spi-max-frequency = <96000000>; 99 }; 100}; 101 102&nandc { 103 u-boot,dm-spl; 104 status = "okay"; 105 #address-cells = <1>; 106 #size-cells = <0>; 107 108 nand@0 { 109 u-boot,dm-spl; 110 reg = <0>; 111 nand-ecc-mode = "hw_syndrome"; 112 nand-ecc-strength = <16>; 113 nand-ecc-step-size = <1024>; 114 }; 115}; 116 117&hw_decompress { 118 u-boot,dm-spl; 119 status = "okay"; 120}; 121 122&secure_otp { 123 u-boot,dm-spl; 124 status = "okay"; 125}; 126 127&u2phy0 { 128 u-boot,dm-pre-reloc; 129 status = "okay"; 130}; 131 132&u2phy_otg { 133 u-boot,dm-pre-reloc; 134 status = "okay"; 135}; 136 137&usbdrd { 138 u-boot,dm-pre-reloc; 139 status = "okay"; 140}; 141 142&usbdrd_dwc3 { 143 u-boot,dm-pre-reloc; 144 status = "okay"; 145}; 146 147&pinctrl { 148 u-boot,dm-pre-reloc; 149 status = "okay"; 150}; 151 152&gpio3 { 153 u-boot,dm-pre-reloc; 154 status = "okay"; 155}; 156 157&gmac { 158 u-boot,dm-pre-reloc; 159 160 phy-mode = "rgmii"; 161 clock_in_out = "input"; 162 163 snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; 164 snps,reset-active-low; 165 /* Reset time is 20ms, 100ms for rtl8211f */ 166 snps,reset-delays-us = <0 20000 100000>; 167 168 assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>; 169 assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 170 assigned-clock-rates = <125000000>, <0>, <25000000>; 171 172 pinctrl-names = "default"; 173 pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; 174 175 tx_delay = <0x2a>; 176 rx_delay = <0x1a>; 177 178 phy-handle = <&phy>; 179 status = "okay"; 180}; 181 182&mdio { 183 u-boot,dm-pre-reloc; 184 status = "okay"; 185 186 phy: phy@0 { 187 compatible = "ethernet-phy-ieee802.3-c22"; 188 u-boot,dm-pre-reloc; 189 reg = <0x0>; 190 clocks = <&cru CLK_GMAC_ETHERNET_OUT>; 191 }; 192}; 193 194&stmmac_axi_setup { 195 u-boot,dm-pre-reloc; 196 status = "okay"; 197 queue0 { 198 u-boot,dm-pre-reloc; 199 }; 200}; 201 202&mtl_rx_setup { 203 u-boot,dm-pre-reloc; 204 status = "okay"; 205 queue0 { 206 u-boot,dm-pre-reloc; 207 }; 208}; 209 210&mtl_tx_setup { 211 u-boot,dm-pre-reloc; 212 status = "okay"; 213}; 214 215&gmac_clkin_m0 { 216 u-boot,dm-pre-reloc; 217 status = "okay"; 218}; 219 220&gmac_clkini_m1 { 221 u-boot,dm-pre-reloc; 222 status = "okay"; 223}; 224 225&rgmiim1_pins { 226 u-boot,dm-pre-reloc; 227 status = "okay"; 228}; 229 230&clk_out_ethernetm1_pins{ 231 u-boot,dm-pre-reloc; 232 status = "okay"; 233}; 234 235&pcfg_pull_none { 236 u-boot,dm-pre-reloc; 237 status = "okay"; 238}; 239 240&pcfg_pull_none_drv_level_12 { 241 u-boot,dm-pre-reloc; 242 status = "okay"; 243}; 244 245