1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &spi_nand, &spi_nor, &nandc, &emmc; 16 }; 17 18 crypto: crypto@ff500000 { 19 compatible = "rockchip,rv1126-crypto"; 20 reg = <0xff500000 0x10000>; 21 clock-names = "sclk_crypto", "sclk_crypto_apk"; 22 clocks = <&cru CLK_CRYPTO_CORE>, <&cru CLK_CRYPTO_PKA>; 23 clock-frequency = <200000000>, <300000000>; 24 }; 25 26 secure_otp: secure_otp@0xff5d0000 { 27 compatible = "rockchip,rv1126-secure-otp"; 28 reg = <0xff5d0000 0x4000>; 29 secure_conf = <0xfe0a0008>; 30 }; 31}; 32 33&uart2 { 34 clock-frequency = <24000000>; 35 u-boot,dm-spl; 36}; 37 38&sdmmc { 39 u-boot,dm-spl; 40}; 41 42&emmc { 43 mmc-ecsd = <0x0020f000>; 44 u-boot,dm-spl; 45}; 46 47&pmu { 48 u-boot,dm-spl; 49}; 50 51&pmugrf { 52 u-boot,dm-spl; 53}; 54 55&pmucru { 56 u-boot,dm-spl; 57}; 58 59&cru { 60 u-boot,dm-spl; 61}; 62 63&crypto { 64 u-boot,dm-spl; 65 status = "okay"; 66}; 67 68&grf { 69 u-boot,dm-spl; 70}; 71 72&saradc { 73 u-boot,dm-spl; 74 status = "okay"; 75}; 76 77&sfc { 78 u-boot,dm-spl; 79 status = "okay"; 80 81 #address-cells = <1>; 82 #size-cells = <0>; 83 spi_nand: flash@0 { 84 u-boot,dm-spl; 85 compatible = "spi-nand"; 86 reg = <0>; 87 spi-tx-bus-width = <1>; 88 spi-rx-bus-width = <4>; 89 spi-max-frequency = <96000000>; 90 }; 91 92 spi_nor: flash@1 { 93 u-boot,dm-spl; 94 compatible = "jedec,spi-nor"; 95 label = "sfc_nor"; 96 reg = <0>; 97 spi-tx-bus-width = <1>; 98 spi-rx-bus-width = <4>; 99 spi-max-frequency = <96000000>; 100 }; 101}; 102 103&nandc { 104 u-boot,dm-spl; 105 status = "okay"; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 109 nand@0 { 110 u-boot,dm-spl; 111 reg = <0>; 112 nand-ecc-mode = "hw_syndrome"; 113 nand-ecc-strength = <16>; 114 nand-ecc-step-size = <1024>; 115 }; 116}; 117 118&hw_decompress { 119 u-boot,dm-spl; 120 status = "okay"; 121}; 122 123&secure_otp { 124 u-boot,dm-spl; 125 status = "okay"; 126}; 127 128&u2phy0 { 129 u-boot,dm-pre-reloc; 130 status = "okay"; 131}; 132 133&u2phy_otg { 134 u-boot,dm-pre-reloc; 135 status = "okay"; 136}; 137 138&usbdrd { 139 u-boot,dm-pre-reloc; 140 status = "okay"; 141}; 142 143&usbdrd_dwc3 { 144 u-boot,dm-pre-reloc; 145 status = "okay"; 146}; 147 148&pinctrl { 149 u-boot,dm-pre-reloc; 150 status = "okay"; 151}; 152 153&gpio3 { 154 u-boot,dm-pre-reloc; 155 status = "okay"; 156}; 157 158&gmac { 159 u-boot,dm-pre-reloc; 160 161 phy-mode = "rgmii"; 162 clock_in_out = "input"; 163 164 snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; 165 snps,reset-active-low; 166 /* Reset time is 20ms, 100ms for rtl8211f */ 167 snps,reset-delays-us = <0 20000 100000>; 168 169 assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>; 170 assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 171 assigned-clock-rates = <125000000>, <0>, <25000000>; 172 173 pinctrl-names = "default"; 174 pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; 175 176 tx_delay = <0x2a>; 177 rx_delay = <0x1a>; 178 179 phy-handle = <&phy>; 180 status = "okay"; 181}; 182 183&mdio { 184 u-boot,dm-pre-reloc; 185 status = "okay"; 186 187 phy: phy@0 { 188 compatible = "ethernet-phy-ieee802.3-c22"; 189 u-boot,dm-pre-reloc; 190 reg = <0x0>; 191 clocks = <&cru CLK_GMAC_ETHERNET_OUT>; 192 }; 193}; 194 195&stmmac_axi_setup { 196 u-boot,dm-pre-reloc; 197 status = "okay"; 198 queue0 { 199 u-boot,dm-pre-reloc; 200 }; 201}; 202 203&mtl_rx_setup { 204 u-boot,dm-pre-reloc; 205 status = "okay"; 206 queue0 { 207 u-boot,dm-pre-reloc; 208 }; 209}; 210 211&mtl_tx_setup { 212 u-boot,dm-pre-reloc; 213 status = "okay"; 214}; 215 216&gmac_clkin_m0 { 217 u-boot,dm-pre-reloc; 218 status = "okay"; 219}; 220 221&gmac_clkini_m1 { 222 u-boot,dm-pre-reloc; 223 status = "okay"; 224}; 225 226&rgmiim1_pins { 227 u-boot,dm-pre-reloc; 228 status = "okay"; 229}; 230 231&clk_out_ethernetm1_pins{ 232 u-boot,dm-pre-reloc; 233 status = "okay"; 234}; 235 236&pcfg_pull_none { 237 u-boot,dm-pre-reloc; 238 status = "okay"; 239}; 240 241&pcfg_pull_none_drv_level_12 { 242 u-boot,dm-pre-reloc; 243 status = "okay"; 244}; 245 246