1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &spi_nand, &spi_nor, &nandc, &emmc; 16 }; 17}; 18 19&uart2 { 20 clock-frequency = <24000000>; 21 u-boot,dm-spl; 22}; 23 24&sdmmc { 25 u-boot,dm-spl; 26}; 27 28&emmc { 29 u-boot,dm-spl; 30}; 31 32&pmu { 33 u-boot,dm-spl; 34}; 35 36&pmugrf { 37 u-boot,dm-spl; 38}; 39 40&pmucru { 41 u-boot,dm-spl; 42}; 43 44&cru { 45 u-boot,dm-spl; 46}; 47 48&crypto { 49 u-boot,dm-spl; 50 status = "okay"; 51}; 52 53&grf { 54 u-boot,dm-spl; 55}; 56 57&saradc { 58 u-boot,dm-spl; 59 status = "okay"; 60}; 61 62&sfc { 63 u-boot,dm-spl; 64 status = "okay"; 65 66 #address-cells = <1>; 67 #size-cells = <0>; 68 spi_nand: flash@0 { 69 u-boot,dm-spl; 70 compatible = "spi-nand"; 71 reg = <0>; 72 spi-tx-bus-width = <1>; 73 spi-rx-bus-width = <4>; 74 spi-max-frequency = <96000000>; 75 }; 76 77 spi_nor: flash@1 { 78 u-boot,dm-spl; 79 compatible = "jedec,spi-nor"; 80 reg = <0>; 81 spi-tx-bus-width = <1>; 82 spi-rx-bus-width = <4>; 83 spi-max-frequency = <96000000>; 84 }; 85}; 86 87&nandc { 88 u-boot,dm-spl; 89 status = "okay"; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 93 nand@0 { 94 u-boot,dm-spl; 95 reg = <0>; 96 nand-ecc-mode = "hw_syndrome"; 97 nand-ecc-strength = <16>; 98 nand-ecc-step-size = <1024>; 99 }; 100}; 101 102&u2phy0 { 103 u-boot,dm-pre-reloc; 104 status = "okay"; 105}; 106 107&u2phy_otg { 108 u-boot,dm-pre-reloc; 109 status = "okay"; 110}; 111 112&usbdrd { 113 u-boot,dm-pre-reloc; 114 status = "okay"; 115}; 116 117&usbdrd_dwc3 { 118 u-boot,dm-pre-reloc; 119 status = "okay"; 120}; 121