1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc; 16 }; 17 18 crypto: crypto@ff500000 { 19 compatible = "rockchip,rv1126-crypto"; 20 reg = <0xff500000 0x10000>; 21 clock-names = "sclk_crypto", "sclk_crypto_apk"; 22 clocks = <&cru CLK_CRYPTO_CORE>, <&cru CLK_CRYPTO_PKA>; 23 clock-frequency = <200000000>, <300000000>; 24 }; 25 26 secure_otp: secure_otp@0xff5d0000 { 27 compatible = "rockchip,rv1126-secure-otp"; 28 reg = <0xff5d0000 0x4000>; 29 secure_conf = <0xfe0a0008>; 30 }; 31}; 32 33&uart2 { 34 clock-frequency = <24000000>; 35 u-boot,dm-spl; 36 /delete-property/ pinctrl-names; 37 /delete-property/ pinctrl-0; 38}; 39 40&sdmmc { 41 u-boot,dm-spl; 42 status = "okay"; 43}; 44 45&sdmmc0 { 46 u-boot,dm-spl; 47}; 48 49&sdmmc0_bus4 { 50 u-boot,dm-spl; 51}; 52 53&sdmmc0_clk { 54 u-boot,dm-spl; 55}; 56 57&sdmmc0_cmd { 58 u-boot,dm-spl; 59}; 60 61&sdmmc0_det { 62 u-boot,dm-spl; 63}; 64 65&emmc { 66 mmc-ecsd = <0x0020f000>; 67 u-boot,dm-spl; 68 /delete-property/ pinctrl-names; 69 /delete-property/ pinctrl-0; 70}; 71 72&pmu { 73 u-boot,dm-spl; 74}; 75 76&pmugrf { 77 u-boot,dm-spl; 78}; 79 80&pmucru { 81 u-boot,dm-spl; 82}; 83 84&cru { 85 u-boot,dm-spl; 86 /delete-property/ assigned-clocks; 87 /delete-property/ assigned-clock-rates; 88 /delete-property/ assigned-clock-parents; 89}; 90 91&crypto { 92 u-boot,dm-spl; 93 status = "okay"; 94}; 95 96&grf { 97 u-boot,dm-spl; 98}; 99 100&saradc { 101 u-boot,dm-spl; 102 status = "okay"; 103}; 104 105&sfc { 106 u-boot,dm-spl; 107 /delete-property/ pinctrl-names; 108 /delete-property/ pinctrl-0; 109 /delete-property/ assigned-clocks; 110 /delete-property/ assigned-clock-rates; 111 status = "okay"; 112 113 #address-cells = <1>; 114 #size-cells = <0>; 115 spi_nand: flash@0 { 116 u-boot,dm-spl; 117 compatible = "spi-nand"; 118 reg = <0>; 119 spi-tx-bus-width = <1>; 120 spi-rx-bus-width = <4>; 121 spi-max-frequency = <96000000>; 122 }; 123 124 spi_nor: flash@1 { 125 u-boot,dm-spl; 126 compatible = "jedec,spi-nor"; 127 label = "sfc_nor"; 128 reg = <0>; 129 spi-tx-bus-width = <1>; 130 spi-rx-bus-width = <4>; 131 spi-max-frequency = <100000000>; 132 }; 133}; 134 135&nandc { 136 u-boot,dm-spl; 137 /delete-property/ pinctrl-names; 138 /delete-property/ pinctrl-0; 139 status = "okay"; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 143 nand@0 { 144 u-boot,dm-spl; 145 reg = <0>; 146 nand-ecc-mode = "hw_syndrome"; 147 nand-ecc-strength = <16>; 148 nand-ecc-step-size = <1024>; 149 }; 150}; 151 152&hw_decompress { 153 u-boot,dm-spl; 154 status = "okay"; 155}; 156 157&secure_otp { 158 u-boot,dm-spl; 159 status = "okay"; 160}; 161 162&u2phy0 { 163 u-boot,dm-pre-reloc; 164 status = "okay"; 165}; 166 167&u2phy_otg { 168 u-boot,dm-pre-reloc; 169 status = "okay"; 170}; 171 172&usbdrd { 173 u-boot,dm-pre-reloc; 174 status = "okay"; 175}; 176 177&usbdrd_dwc3 { 178 u-boot,dm-pre-reloc; 179 status = "okay"; 180}; 181 182&pinctrl { 183 u-boot,dm-spl; 184 status = "okay"; 185}; 186 187&gpio1 { 188 u-boot,dm-spl; 189 status = "okay"; 190}; 191 192&pcfg_pull_up_drv_level_2 { 193 u-boot,dm-spl; 194}; 195 196&pcfg_pull_none { 197 u-boot,dm-spl; 198}; 199 200&gpio3 { 201 u-boot,dm-pre-reloc; 202 status = "okay"; 203}; 204 205&gmac { 206 u-boot,dm-pre-reloc; 207 208 phy-mode = "rgmii"; 209 clock_in_out = "input"; 210 211 snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; 212 snps,reset-active-low; 213 /* Reset time is 20ms, 100ms for rtl8211f */ 214 snps,reset-delays-us = <0 20000 100000>; 215 216 assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>; 217 assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 218 assigned-clock-rates = <125000000>, <0>, <25000000>; 219 220 pinctrl-names = "default"; 221 pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; 222 223 tx_delay = <0x2a>; 224 rx_delay = <0x1a>; 225 226 phy-handle = <&phy>; 227 status = "okay"; 228}; 229 230&mdio { 231 u-boot,dm-pre-reloc; 232 status = "okay"; 233 234 phy: phy@0 { 235 compatible = "ethernet-phy-ieee802.3-c22"; 236 u-boot,dm-pre-reloc; 237 reg = <0x0>; 238 clocks = <&cru CLK_GMAC_ETHERNET_OUT>; 239 }; 240}; 241 242&stmmac_axi_setup { 243 u-boot,dm-pre-reloc; 244 status = "okay"; 245 queue0 { 246 u-boot,dm-pre-reloc; 247 }; 248}; 249 250&mtl_rx_setup { 251 u-boot,dm-pre-reloc; 252 status = "okay"; 253 queue0 { 254 u-boot,dm-pre-reloc; 255 }; 256}; 257 258&mtl_tx_setup { 259 u-boot,dm-pre-reloc; 260 status = "okay"; 261}; 262 263&gmac_clkin_m0 { 264 u-boot,dm-pre-reloc; 265 status = "okay"; 266}; 267 268&gmac_clkini_m1 { 269 u-boot,dm-pre-reloc; 270 status = "okay"; 271}; 272 273&rgmiim1_pins { 274 u-boot,dm-pre-reloc; 275 status = "okay"; 276}; 277 278&clk_out_ethernetm1_pins{ 279 u-boot,dm-pre-reloc; 280 status = "okay"; 281}; 282 283&pcfg_pull_none { 284 u-boot,dm-pre-reloc; 285 status = "okay"; 286}; 287 288&pcfg_pull_none_drv_level_12 { 289 u-boot,dm-pre-reloc; 290 status = "okay"; 291}; 292 293&wdt { 294 u-boot,dm-pre-reloc; 295 status = "okay"; 296}; 297