1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/rv1108-cru.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 compatible = "rockchip,rv1108"; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 spi0 = &sfc; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@f00 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a7"; 34 reg = <0xf00>; 35 }; 36 }; 37 38 arm-pmu { 39 compatible = "arm,cortex-a7-pmu"; 40 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 41 }; 42 43 timer { 44 compatible = "arm,armv7-timer"; 45 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, 46 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 47 clock-frequency = <24000000>; 48 }; 49 50 xin24m: oscillator { 51 compatible = "fixed-clock"; 52 clock-frequency = <24000000>; 53 clock-output-names = "xin24m"; 54 #clock-cells = <0>; 55 }; 56 57 amba { 58 compatible = "simple-bus"; 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 pdma: pdma@102a0000 { 64 compatible = "arm,pl330", "arm,primecell"; 65 reg = <0x102a0000 0x4000>; 66 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 67 #dma-cells = <1>; 68 arm,pl330-broken-no-flushp; 69 clocks = <&cru ACLK_DMAC>; 70 clock-names = "apb_pclk"; 71 }; 72 }; 73 74 bus_intmem@10080000 { 75 compatible = "mmio-sram"; 76 reg = <0x10080000 0x2000>; 77 #address-cells = <1>; 78 #size-cells = <1>; 79 ranges = <0 0x10080000 0x2000>; 80 }; 81 82 uart2: serial@10210000 { 83 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 84 reg = <0x10210000 0x100>; 85 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 86 reg-shift = <2>; 87 reg-io-width = <4>; 88 clock-frequency = <24000000>; 89 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 90 clock-names = "baudclk", "apb_pclk"; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&uart2m0_xfer>; 93 status = "disabled"; 94 }; 95 96 uart1: serial@10220000 { 97 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 98 reg = <0x10220000 0x100>; 99 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 100 reg-shift = <2>; 101 reg-io-width = <4>; 102 clock-frequency = <24000000>; 103 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 104 clock-names = "baudclk", "apb_pclk"; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&uart1_xfer>; 107 status = "disabled"; 108 }; 109 110 uart0: serial@10230000 { 111 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 112 reg = <0x10230000 0x100>; 113 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 114 reg-shift = <2>; 115 reg-io-width = <4>; 116 clock-frequency = <24000000>; 117 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 118 clock-names = "baudclk", "apb_pclk"; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 121 status = "disabled"; 122 }; 123 124 grf: syscon@10300000 { 125 compatible = "rockchip,rv1108-grf", "syscon"; 126 reg = <0x10300000 0x1000>; 127 }; 128 129 u2phy: usb2-phy@10300100 { 130 compatible = "rockchip,rv1108-usb2phy"; 131 reg = <0x100 0x0c>; 132 rockchip,grf = <&grf>; 133 rockchip,usbgrf = <&usbgrf>; 134 #phy-cells = <1>; 135 status = "disabled"; 136 137 u2phy_otg: otg-port { 138 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 139 interrupt-names = "otg-mux"; 140 #phy-cells = <0>; 141 status = "disabled"; 142 }; 143 144 u2phy_host: host-port { 145 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 146 interrupt-names = "linestate"; 147 #phy-cells = <0>; 148 status = "disabled"; 149 }; 150 }; 151 152 saradc: saradc@1038c000 { 153 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; 154 reg = <0x1038c000 0x100>; 155 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 156 #io-channel-cells = <1>; 157 clock-frequency = <1000000>; 158 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 159 clock-names = "saradc", "apb_pclk"; 160 status = "disabled"; 161 }; 162 163 pmugrf: syscon@20060000 { 164 compatible = "rockchip,rv1108-pmugrf", "syscon"; 165 reg = <0x20060000 0x1000>; 166 }; 167 168 cru: clock-controller@20200000 { 169 compatible = "rockchip,rv1108-cru"; 170 reg = <0x20200000 0x1000>; 171 rockchip,grf = <&grf>; 172 #clock-cells = <1>; 173 #reset-cells = <1>; 174 }; 175 176 usbgrf: syscon@202a0000 { 177 compatible = "rockchip,rv1108-usbgrf", "syscon"; 178 reg = <0x202a0000 0x1000>; 179 }; 180 181 emmc: dwmmc@30110000 { 182 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 183 clock-freq-min-max = <400000 150000000>; 184 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 185 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 186 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 187 fifo-depth = <0x100>; 188 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 189 reg = <0x30110000 0x4000>; 190 status = "disabled"; 191 }; 192 193 sdio: dwmmc@30120000 { 194 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 195 clock-freq-min-max = <400000 150000000>; 196 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 197 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 198 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 199 fifo-depth = <0x100>; 200 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 201 reg = <0x30120000 0x4000>; 202 status = "disabled"; 203 }; 204 205 sdmmc: dwmmc@30130000 { 206 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 207 clock-freq-min-max = <400000 100000000>; 208 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 209 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 210 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 211 fifo-depth = <0x100>; 212 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 213 reg = <0x30130000 0x4000>; 214 status = "disabled"; 215 }; 216 217 usb_host_ehci: usb@30140000 { 218 compatible = "generic-ehci"; 219 reg = <0x30140000 0x20000>; 220 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 221 phys = <&u2phy 1>; 222 phy-names = "usb"; 223 status = "disabled"; 224 }; 225 226 usb_host_ohci: usb@30160000 { 227 compatible = "generic-ohci"; 228 reg = <0x30160000 0x20000>; 229 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 230 phys = <&u2phy 1>; 231 phy-names = "usb"; 232 status = "disabled"; 233 }; 234 235 usb20_otg: usb@30180000 { 236 compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb", 237 "snps,dwc2"; 238 reg = <0x30180000 0x40000>; 239 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 240 hnp-srp-disable; 241 dr_mode = "otg"; 242 phys = <&u2phy 0>; 243 phy-names = "usb"; 244 status = "disabled"; 245 }; 246 247 sfc: sfc@301c0000 { 248 compatible = "rockchip,sfc"; 249 reg = <0x301c0000 0x200>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 254 clock-names = "clk_sfc", "hclk_sfc"; 255 pinctrl-0 = <&sfc_pins>; 256 pinctrl-names = "default"; 257 status = "disabled"; 258 }; 259 260 gmac: ethernet@30200000 { 261 compatible = "rockchip,rv1108-gmac"; 262 reg = <0x30200000 0x10000>; 263 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 264 interrupt-names = "macirq"; 265 rockchip,grf = <&grf>; 266 clocks = <&cru SCLK_MAC>, 267 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 268 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 269 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 270 clock-names = "stmmaceth", 271 "mac_clk_rx", "mac_clk_tx", 272 "clk_mac_ref", "clk_mac_refout", 273 "aclk_mac", "pclk_mac"; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&rmii_pins>; 276 phy-mode = "rmii"; 277 max-speed = <100>; 278 status = "disabled"; 279 }; 280 281 gic: interrupt-controller@32010000 { 282 compatible = "arm,gic-400"; 283 interrupt-controller; 284 #interrupt-cells = <3>; 285 #address-cells = <0>; 286 287 reg = <0x32011000 0x1000>, 288 <0x32012000 0x1000>, 289 <0x32014000 0x2000>, 290 <0x32016000 0x2000>; 291 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 292 }; 293 294 pinctrl: pinctrl { 295 compatible = "rockchip,rv1108-pinctrl"; 296 rockchip,grf = <&grf>; 297 rockchip,pmu = <&pmugrf>; 298 #address-cells = <1>; 299 #size-cells = <1>; 300 ranges; 301 302 gpio0: gpio0@20030000 { 303 compatible = "rockchip,gpio-bank"; 304 reg = <0x20030000 0x100>; 305 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&xin24m>; 307 308 gpio-controller; 309 #gpio-cells = <2>; 310 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 }; 314 315 gpio1: gpio1@10310000 { 316 compatible = "rockchip,gpio-bank"; 317 reg = <0x10310000 0x100>; 318 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&xin24m>; 320 321 gpio-controller; 322 #gpio-cells = <2>; 323 324 interrupt-controller; 325 #interrupt-cells = <2>; 326 }; 327 328 gpio2: gpio2@10320000 { 329 compatible = "rockchip,gpio-bank"; 330 reg = <0x10320000 0x100>; 331 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&xin24m>; 333 334 gpio-controller; 335 #gpio-cells = <2>; 336 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 }; 340 341 gpio3: gpio3@10330000 { 342 compatible = "rockchip,gpio-bank"; 343 reg = <0x10330000 0x100>; 344 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&xin24m>; 346 347 gpio-controller; 348 #gpio-cells = <2>; 349 350 interrupt-controller; 351 #interrupt-cells = <2>; 352 }; 353 354 pcfg_pull_up: pcfg-pull-up { 355 bias-pull-up; 356 }; 357 358 pcfg_pull_down: pcfg-pull-down { 359 bias-pull-down; 360 }; 361 362 pcfg_pull_none: pcfg-pull-none { 363 bias-disable; 364 }; 365 366 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { 367 drive-strength = <8>; 368 }; 369 370 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 371 drive-strength = <12>; 372 }; 373 374 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { 375 bias-pull-up; 376 drive-strength = <8>; 377 }; 378 379 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { 380 drive-strength = <4>; 381 }; 382 383 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { 384 bias-pull-up; 385 drive-strength = <4>; 386 }; 387 388 pcfg_output_high: pcfg-output-high { 389 output-high; 390 }; 391 392 pcfg_output_low: pcfg-output-low { 393 output-low; 394 }; 395 396 pcfg_input_high: pcfg-input-high { 397 bias-pull-up; 398 input-enable; 399 }; 400 401 gmac { 402 rmii_pins: rmii-pins { 403 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 404 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, 405 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 406 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 407 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 408 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 409 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, 410 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, 411 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, 412 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 413 }; 414 }; 415 416 i2c1 { 417 i2c1_xfer: i2c1-xfer { 418 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, 419 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 420 }; 421 }; 422 423 i2c2m1 { 424 i2c2m1_xfer: i2c2m1-xfer { 425 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, 426 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; 427 }; 428 429 i2c2m1_gpio: i2c2m1-gpio { 430 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, 431 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 432 }; 433 }; 434 435 i2c2m05v { 436 i2c2m05v_xfer: i2c2m05v-xfer { 437 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 438 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; 439 }; 440 441 i2c2m05v_gpio: i2c2m05v-gpio { 442 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, 443 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 444 }; 445 }; 446 447 i2c3 { 448 i2c3_xfer: i2c3-xfer { 449 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 450 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 451 }; 452 }; 453 454 sfc { 455 sfc_pins: sfc-pins { 456 rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>, 457 <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>, 458 <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>, 459 <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>, 460 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, 461 <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>; 462 }; 463 }; 464 465 sdmmc { 466 sdmmc_clk: sdmmc-clk { 467 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; 468 }; 469 470 sdmmc_cmd: sdmmc-cmd { 471 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 472 }; 473 474 sdmmc_cd: sdmmc-cd { 475 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 476 }; 477 478 sdmmc_bus1: sdmmc-bus1 { 479 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 480 }; 481 482 sdmmc_bus4: sdmmc-bus4 { 483 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, 484 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, 485 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, 486 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 487 }; 488 }; 489 490 uart0 { 491 uart0_xfer: uart0-xfer { 492 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, 493 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 494 }; 495 496 uart0_cts: uart0-cts { 497 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; 498 }; 499 500 uart0_rts: uart0-rts { 501 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 502 }; 503 504 uart0_rts_gpio: uart0-rts-gpio { 505 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 506 }; 507 }; 508 509 uart1 { 510 uart1_xfer: uart1-xfer { 511 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, 512 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; 513 }; 514 515 uart1_cts: uart1-cts { 516 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 517 }; 518 519 uart01rts: uart1-rts { 520 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 521 }; 522 }; 523 524 uart2m0 { 525 uart2m0_xfer: uart2m0-xfer { 526 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, 527 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 528 }; 529 }; 530 531 uart2m1 { 532 uart2m1_xfer: uart2m1-xfer { 533 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, 534 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 535 }; 536 }; 537 538 uart2_5v { 539 uart2_5v_cts: uart2_5v-cts { 540 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; 541 }; 542 543 uart2_5v_rts: uart2_5v-rts { 544 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 545 }; 546 }; 547 }; 548 549 dmc: dmc@202b0000 { 550 u-boot,dm-pre-reloc; 551 compatible = "rockchip,rv1108-dmc"; 552 reg = <0x202b0000 0x400 553 0x20210000 0x400 554 0x31070000 0x40 555 0x10300000 0xf94 556 0x20060000 0x38c 557 0x20200000 0x1f0 558 0x20010000 0x78>; 559 }; 560}; 561