1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/rv1108-cru.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/media/rockchip_mipi_dsi.h> 13#include <linux/media-bus-format.h> 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1108"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 i2c0 = &i2c0; 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 spi0 = &sfc; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@f00 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a7"; 37 reg = <0xf00>; 38 }; 39 }; 40 41 arm-pmu { 42 compatible = "arm,cortex-a7-pmu"; 43 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 44 }; 45 46 display_subsystem: display-subsystem { 47 compatible = "rockchip,display-subsystem"; 48 ports = <&vop_out>; 49 status = "disabled"; 50 51 route { 52 route_dsi: route-dsi { 53 status = "okay"; 54 logo,uboot = "logo.bmp"; 55 logo,kernel = "logo_kernel.bmp"; 56 logo,mode = "center"; 57 charge_logo,mode = "center"; 58 connect = <&vop_out_mipi>; 59 }; 60 }; 61 }; 62 63 mipi_dphy: mipi-dphy@0x20228000 { 64 compatible = "rockchip,rv1108-mipi-dphy"; 65 reg = <0x20228000 0x8000>; 66 clock-output-names = "mipi_dphy_pll"; 67 #clock-cells = <0>; 68 resets = <&cru PRST_MIPI_DSI_PHY>; 69 reset-names = "apb"; 70 #phy-cells = <0>; 71 status = "disabled"; 72 }; 73 74 dsi: dsi@300e0000 { 75 compatible = "rockchip,rv1108-mipi-dsi"; 76 reg = <0x300e0000 0x10000>; 77 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&cru PCLK_MIPI_DSI>, <&mipi_dphy>; 79 clock-names = "pclk", "hs_clk"; 80 resets = <&cru 127>; 81 reset-names = "apb"; 82 phys = <&mipi_dphy>; 83 phy-names = "mipi_dphy"; 84 rockchip,grf = <&grf>; 85 #address-cells = <1>; 86 #size-cells = <0>; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&lcdc_mipi_data>; 89 status = "disabled"; 90 91 ports { 92 #address-cells = <1>; 93 #size-cells = <0>; 94 95 port@0 { 96 reg = <0>; 97 98 #address-cells = <1>; 99 #size-cells = <0>; 100 101 mipi_in_vop: endpoint@0 { 102 reg = <0>; 103 remote-endpoint = <&vop_out_mipi>; 104 }; 105 }; 106 107 }; 108 }; 109 110 timer { 111 compatible = "arm,armv7-timer"; 112 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, 113 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 114 clock-frequency = <24000000>; 115 }; 116 117 xin24m: oscillator { 118 compatible = "fixed-clock"; 119 clock-frequency = <24000000>; 120 clock-output-names = "xin24m"; 121 #clock-cells = <0>; 122 }; 123 124 amba { 125 compatible = "simple-bus"; 126 #address-cells = <1>; 127 #size-cells = <1>; 128 ranges; 129 130 pdma: pdma@102a0000 { 131 compatible = "arm,pl330", "arm,primecell"; 132 reg = <0x102a0000 0x4000>; 133 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 134 #dma-cells = <1>; 135 arm,pl330-broken-no-flushp; 136 clocks = <&cru ACLK_DMAC>; 137 clock-names = "apb_pclk"; 138 }; 139 }; 140 141 bus_intmem@10080000 { 142 compatible = "mmio-sram"; 143 reg = <0x10080000 0x2000>; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 ranges = <0 0x10080000 0x2000>; 147 }; 148 149 uart2: serial@10210000 { 150 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 151 reg = <0x10210000 0x100>; 152 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 153 reg-shift = <2>; 154 reg-io-width = <4>; 155 clock-frequency = <24000000>; 156 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 157 clock-names = "baudclk", "apb_pclk"; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&uart2m0_xfer>; 160 status = "disabled"; 161 }; 162 163 uart1: serial@10220000 { 164 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 165 reg = <0x10220000 0x100>; 166 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 167 reg-shift = <2>; 168 reg-io-width = <4>; 169 clock-frequency = <24000000>; 170 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 171 clock-names = "baudclk", "apb_pclk"; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&uart1_xfer>; 174 status = "disabled"; 175 }; 176 177 uart0: serial@10230000 { 178 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 179 reg = <0x10230000 0x100>; 180 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 181 reg-shift = <2>; 182 reg-io-width = <4>; 183 clock-frequency = <24000000>; 184 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 185 clock-names = "baudclk", "apb_pclk"; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 188 status = "disabled"; 189 }; 190 191 grf: syscon@10300000 { 192 compatible = "rockchip,rv1108-grf", "syscon"; 193 reg = <0x10300000 0x1000>; 194 }; 195 196 u2phy: usb2-phy@10300100 { 197 compatible = "rockchip,rv1108-usb2phy"; 198 reg = <0x100 0x0c>; 199 rockchip,grf = <&grf>; 200 #phy-cells = <1>; 201 status = "disabled"; 202 203 u2phy_otg: otg-port { 204 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 205 interrupt-names = "otg-mux"; 206 #phy-cells = <0>; 207 status = "disabled"; 208 }; 209 210 u2phy_host: host-port { 211 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-names = "linestate"; 213 #phy-cells = <0>; 214 status = "disabled"; 215 }; 216 }; 217 218 saradc: saradc@1038c000 { 219 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; 220 reg = <0x1038c000 0x100>; 221 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 222 #io-channel-cells = <1>; 223 clock-frequency = <1000000>; 224 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 225 clock-names = "saradc", "apb_pclk"; 226 status = "disabled"; 227 }; 228 229 pwm0: pwm@20040000 { 230 compatible = "rockchip,rk1108-pwm", "rockchip,rk3328-pwm"; 231 reg = <0x20040000 0x10>; 232 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 233 #pwm-cells = <3>; 234 pinctrl-names = "active"; 235 pinctrl-0 = <&pwm0_pin>; 236 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 237 clock-names = "pwm", "pclk"; 238 status = "disabled"; 239 }; 240 241 pmugrf: syscon@20060000 { 242 compatible = "rockchip,rv1108-pmugrf", "syscon"; 243 reg = <0x20060000 0x1000>; 244 }; 245 246 cru: clock-controller@20200000 { 247 compatible = "rockchip,rv1108-cru"; 248 reg = <0x20200000 0x1000>; 249 rockchip,grf = <&grf>; 250 #clock-cells = <1>; 251 #reset-cells = <1>; 252 }; 253 i2c0: i2c@20000000 { 254 compatible = "rockchip,rv1108-i2c"; 255 reg = <0x20000000 0x1000>; 256 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 257 rockchip,grf = <&grf>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>; 261 clock-names = "i2c", "pclk"; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&i2c0_xfer>; 264 status = "disabled"; 265 }; 266 usbgrf: syscon@202a0000 { 267 compatible = "rockchip,rv1108-usbgrf", "syscon"; 268 reg = <0x202a0000 0x1000>; 269 }; 270 271 emmc: dwmmc@30110000 { 272 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 273 clock-freq-min-max = <400000 150000000>; 274 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 275 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 276 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 277 fifo-depth = <0x100>; 278 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 279 reg = <0x30110000 0x4000>; 280 status = "disabled"; 281 }; 282 283 sdio: dwmmc@30120000 { 284 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 285 clock-freq-min-max = <400000 150000000>; 286 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 287 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 288 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 289 fifo-depth = <0x100>; 290 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 291 reg = <0x30120000 0x4000>; 292 status = "disabled"; 293 }; 294 295 sdmmc: dwmmc@30130000 { 296 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 297 clock-freq-min-max = <400000 100000000>; 298 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 299 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 300 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 301 fifo-depth = <0x100>; 302 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 303 reg = <0x30130000 0x4000>; 304 status = "disabled"; 305 }; 306 307 usb_host_ehci: usb@30140000 { 308 compatible = "generic-ehci"; 309 reg = <0x30140000 0x20000>; 310 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 311 phys = <&u2phy_host>; 312 phy-names = "usb"; 313 status = "disabled"; 314 }; 315 316 usb_host_ohci: usb@30160000 { 317 compatible = "generic-ohci"; 318 reg = <0x30160000 0x20000>; 319 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 320 phys = <&u2phy_host>; 321 phy-names = "usb"; 322 status = "disabled"; 323 }; 324 325 usb20_otg: usb@30180000 { 326 compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb", 327 "snps,dwc2"; 328 reg = <0x30180000 0x40000>; 329 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 330 hnp-srp-disable; 331 dr_mode = "otg"; 332 phys = <&u2phy_otg>; 333 phy-names = "usb"; 334 status = "disabled"; 335 }; 336 337 sfc: sfc@301c0000 { 338 compatible = "rockchip,sfc"; 339 reg = <0x301c0000 0x200>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 344 clock-names = "clk_sfc", "hclk_sfc"; 345 pinctrl-0 = <&sfc_pins>; 346 pinctrl-names = "default"; 347 status = "disabled"; 348 }; 349 350 gmac: ethernet@30200000 { 351 compatible = "rockchip,rv1108-gmac"; 352 reg = <0x30200000 0x10000>; 353 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 354 interrupt-names = "macirq"; 355 rockchip,grf = <&grf>; 356 clocks = <&cru SCLK_MAC>, 357 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 358 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 359 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 360 clock-names = "stmmaceth", 361 "mac_clk_rx", "mac_clk_tx", 362 "clk_mac_ref", "clk_mac_refout", 363 "aclk_mac", "pclk_mac"; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&rmii_pins>; 366 phy-mode = "rmii"; 367 max-speed = <100>; 368 status = "disabled"; 369 }; 370 371 gic: interrupt-controller@32010000 { 372 compatible = "arm,gic-400"; 373 interrupt-controller; 374 #interrupt-cells = <3>; 375 #address-cells = <0>; 376 377 reg = <0x32011000 0x1000>, 378 <0x32012000 0x1000>, 379 <0x32014000 0x2000>, 380 <0x32016000 0x2000>; 381 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 382 }; 383 384 pinctrl: pinctrl { 385 compatible = "rockchip,rv1108-pinctrl"; 386 rockchip,grf = <&grf>; 387 rockchip,pmu = <&pmugrf>; 388 #address-cells = <1>; 389 #size-cells = <1>; 390 ranges; 391 392 gpio0: gpio0@20030000 { 393 compatible = "rockchip,gpio-bank"; 394 reg = <0x20030000 0x100>; 395 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&xin24m>; 397 398 gpio-controller; 399 #gpio-cells = <2>; 400 401 interrupt-controller; 402 #interrupt-cells = <2>; 403 }; 404 405 gpio1: gpio1@10310000 { 406 compatible = "rockchip,gpio-bank"; 407 reg = <0x10310000 0x100>; 408 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&xin24m>; 410 411 gpio-controller; 412 #gpio-cells = <2>; 413 414 interrupt-controller; 415 #interrupt-cells = <2>; 416 }; 417 418 gpio2: gpio2@10320000 { 419 compatible = "rockchip,gpio-bank"; 420 reg = <0x10320000 0x100>; 421 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&xin24m>; 423 424 gpio-controller; 425 #gpio-cells = <2>; 426 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 }; 430 431 gpio3: gpio3@10330000 { 432 compatible = "rockchip,gpio-bank"; 433 reg = <0x10330000 0x100>; 434 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&xin24m>; 436 437 gpio-controller; 438 #gpio-cells = <2>; 439 440 interrupt-controller; 441 #interrupt-cells = <2>; 442 }; 443 444 pcfg_pull_up: pcfg-pull-up { 445 bias-pull-up; 446 }; 447 448 pcfg_pull_down: pcfg-pull-down { 449 bias-pull-down; 450 }; 451 452 pcfg_pull_none: pcfg-pull-none { 453 bias-disable; 454 }; 455 456 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { 457 drive-strength = <8>; 458 }; 459 460 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 461 drive-strength = <12>; 462 }; 463 464 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { 465 bias-pull-up; 466 drive-strength = <8>; 467 }; 468 469 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { 470 drive-strength = <4>; 471 }; 472 473 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { 474 bias-pull-up; 475 drive-strength = <4>; 476 }; 477 478 pcfg_pull_none_smt: pcfg-pull-none-smt { 479 bias-disable; 480 input-schmitt-enable; 481 }; 482 483 pcfg_output_high: pcfg-output-high { 484 output-high; 485 }; 486 487 pcfg_output_low: pcfg-output-low { 488 output-low; 489 }; 490 491 pcfg_input_high: pcfg-input-high { 492 bias-pull-up; 493 input-enable; 494 }; 495 496 pwm0 { 497 pwm0_pin: pwm0-pin { 498 rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 499 }; 500 }; 501 502 gmac { 503 rmii_pins: rmii-pins { 504 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 505 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, 506 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 507 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 508 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 509 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 510 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, 511 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, 512 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, 513 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 514 }; 515 }; 516 517 gpio1_lcdc { 518 lcdc_mipi_data: lcdc-mipi_data { 519 rockchip,pins = <1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, /* DSI_CLKP */ 520 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, /* DSI_CLKN */ 521 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, /* D0P */ 522 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, /* D0N */ 523 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* D1P */ 524 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* D1N */ 525 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* D2P */ 526 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* D2N */ 527 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* D3P */ 528 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* D3N */ 529 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* D10 */ 530 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* D11 */ 531 }; 532 }; 533 534 i2c0 { 535 i2c0_xfer: i2c0-xfer { 536 rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>, 537 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>; 538 }; 539 }; 540 541 i2c1 { 542 i2c1_xfer: i2c1-xfer { 543 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, 544 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 545 }; 546 }; 547 548 i2c2m1 { 549 i2c2m1_xfer: i2c2m1-xfer { 550 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, 551 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; 552 }; 553 554 i2c2m1_gpio: i2c2m1-gpio { 555 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, 556 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 557 }; 558 }; 559 560 i2c2m05v { 561 i2c2m05v_xfer: i2c2m05v-xfer { 562 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 563 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; 564 }; 565 566 i2c2m05v_gpio: i2c2m05v-gpio { 567 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, 568 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 569 }; 570 }; 571 572 i2c3 { 573 i2c3_xfer: i2c3-xfer { 574 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 575 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 576 }; 577 }; 578 579 sfc { 580 sfc_pins: sfc-pins { 581 rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>, 582 <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>, 583 <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>, 584 <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>, 585 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, 586 <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>; 587 }; 588 }; 589 590 sdmmc { 591 sdmmc_clk: sdmmc-clk { 592 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; 593 }; 594 595 sdmmc_cmd: sdmmc-cmd { 596 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 597 }; 598 599 sdmmc_cd: sdmmc-cd { 600 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 601 }; 602 603 sdmmc_bus1: sdmmc-bus1 { 604 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 605 }; 606 607 sdmmc_bus4: sdmmc-bus4 { 608 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, 609 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, 610 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, 611 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 612 }; 613 }; 614 615 uart0 { 616 uart0_xfer: uart0-xfer { 617 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, 618 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 619 }; 620 621 uart0_cts: uart0-cts { 622 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; 623 }; 624 625 uart0_rts: uart0-rts { 626 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 627 }; 628 629 uart0_rts_gpio: uart0-rts-gpio { 630 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 631 }; 632 }; 633 634 uart1 { 635 uart1_xfer: uart1-xfer { 636 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, 637 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; 638 }; 639 640 uart1_cts: uart1-cts { 641 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 642 }; 643 644 uart01rts: uart1-rts { 645 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 646 }; 647 }; 648 649 uart2m0 { 650 uart2m0_xfer: uart2m0-xfer { 651 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, 652 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 653 }; 654 }; 655 656 uart2m1 { 657 uart2m1_xfer: uart2m1-xfer { 658 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, 659 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 660 }; 661 }; 662 663 uart2_5v { 664 uart2_5v_cts: uart2_5v-cts { 665 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; 666 }; 667 668 uart2_5v_rts: uart2_5v-rts { 669 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 670 }; 671 }; 672 }; 673 674 dmc: dmc@202b0000 { 675 u-boot,dm-pre-reloc; 676 compatible = "rockchip,rv1108-dmc"; 677 reg = <0x202b0000 0x400 678 0x20210000 0x400 679 0x31070000 0x40 680 0x10300000 0xf94 681 0x20060000 0x38c 682 0x20200000 0x1f0 683 0x20010000 0x78>; 684 }; 685 686 vop: vop@30040000 { 687 compatible = "rockchip,rv1108-vop"; 688 reg = <0x30040000 0xe00>; 689 reg-names = "regs"; 690 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, 692 <&cru HCLK_VOP>; 693 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 694 status = "disabled"; 695 696 vop_out: port { 697 #address-cells = <1>; 698 #size-cells = <0>; 699 700 vop_out_mipi: endpoint@0 { 701 reg = <0>; 702 remote-endpoint = <&mipi_in_vop>; 703 }; 704 }; 705 }; 706}; 707
