1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/rv1108-cru.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 compatible = "rockchip,rv1108"; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 i2c0 = &i2c0; 22 serial0 = &uart0; 23 serial1 = &uart1; 24 serial2 = &uart2; 25 spi0 = &sfc; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 }; 37 }; 38 39 arm-pmu { 40 compatible = "arm,cortex-a7-pmu"; 41 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 42 }; 43 44 timer { 45 compatible = "arm,armv7-timer"; 46 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, 47 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 48 clock-frequency = <24000000>; 49 }; 50 51 xin24m: oscillator { 52 compatible = "fixed-clock"; 53 clock-frequency = <24000000>; 54 clock-output-names = "xin24m"; 55 #clock-cells = <0>; 56 }; 57 58 amba { 59 compatible = "simple-bus"; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 ranges; 63 64 pdma: pdma@102a0000 { 65 compatible = "arm,pl330", "arm,primecell"; 66 reg = <0x102a0000 0x4000>; 67 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 68 #dma-cells = <1>; 69 arm,pl330-broken-no-flushp; 70 clocks = <&cru ACLK_DMAC>; 71 clock-names = "apb_pclk"; 72 }; 73 }; 74 75 bus_intmem@10080000 { 76 compatible = "mmio-sram"; 77 reg = <0x10080000 0x2000>; 78 #address-cells = <1>; 79 #size-cells = <1>; 80 ranges = <0 0x10080000 0x2000>; 81 }; 82 83 uart2: serial@10210000 { 84 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 85 reg = <0x10210000 0x100>; 86 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 87 reg-shift = <2>; 88 reg-io-width = <4>; 89 clock-frequency = <24000000>; 90 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 91 clock-names = "baudclk", "apb_pclk"; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&uart2m0_xfer>; 94 status = "disabled"; 95 }; 96 97 uart1: serial@10220000 { 98 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 99 reg = <0x10220000 0x100>; 100 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 101 reg-shift = <2>; 102 reg-io-width = <4>; 103 clock-frequency = <24000000>; 104 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 105 clock-names = "baudclk", "apb_pclk"; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&uart1_xfer>; 108 status = "disabled"; 109 }; 110 111 uart0: serial@10230000 { 112 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 113 reg = <0x10230000 0x100>; 114 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 115 reg-shift = <2>; 116 reg-io-width = <4>; 117 clock-frequency = <24000000>; 118 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 119 clock-names = "baudclk", "apb_pclk"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 122 status = "disabled"; 123 }; 124 125 grf: syscon@10300000 { 126 compatible = "rockchip,rv1108-grf", "syscon"; 127 reg = <0x10300000 0x1000>; 128 }; 129 130 u2phy: usb2-phy@10300100 { 131 compatible = "rockchip,rv1108-usb2phy"; 132 reg = <0x100 0x0c>; 133 rockchip,grf = <&grf>; 134 #phy-cells = <1>; 135 status = "disabled"; 136 137 u2phy_otg: otg-port { 138 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 139 interrupt-names = "otg-mux"; 140 #phy-cells = <0>; 141 status = "disabled"; 142 }; 143 144 u2phy_host: host-port { 145 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 146 interrupt-names = "linestate"; 147 #phy-cells = <0>; 148 status = "disabled"; 149 }; 150 }; 151 152 saradc: saradc@1038c000 { 153 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; 154 reg = <0x1038c000 0x100>; 155 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 156 #io-channel-cells = <1>; 157 clock-frequency = <1000000>; 158 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 159 clock-names = "saradc", "apb_pclk"; 160 status = "disabled"; 161 }; 162 163 pmugrf: syscon@20060000 { 164 compatible = "rockchip,rv1108-pmugrf", "syscon"; 165 reg = <0x20060000 0x1000>; 166 }; 167 168 cru: clock-controller@20200000 { 169 compatible = "rockchip,rv1108-cru"; 170 reg = <0x20200000 0x1000>; 171 rockchip,grf = <&grf>; 172 #clock-cells = <1>; 173 #reset-cells = <1>; 174 }; 175 i2c0: i2c@20000000 { 176 compatible = "rockchip,rv1108-i2c"; 177 reg = <0x20000000 0x1000>; 178 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 179 rockchip,grf = <&grf>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>; 183 clock-names = "i2c", "pclk"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&i2c0_xfer>; 186 status = "disabled"; 187 }; 188 usbgrf: syscon@202a0000 { 189 compatible = "rockchip,rv1108-usbgrf", "syscon"; 190 reg = <0x202a0000 0x1000>; 191 }; 192 193 emmc: dwmmc@30110000 { 194 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 195 clock-freq-min-max = <400000 150000000>; 196 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 197 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 198 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 199 fifo-depth = <0x100>; 200 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 201 reg = <0x30110000 0x4000>; 202 status = "disabled"; 203 }; 204 205 sdio: dwmmc@30120000 { 206 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 207 clock-freq-min-max = <400000 150000000>; 208 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 209 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 210 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 211 fifo-depth = <0x100>; 212 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 213 reg = <0x30120000 0x4000>; 214 status = "disabled"; 215 }; 216 217 sdmmc: dwmmc@30130000 { 218 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 219 clock-freq-min-max = <400000 100000000>; 220 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 221 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 222 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 223 fifo-depth = <0x100>; 224 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 225 reg = <0x30130000 0x4000>; 226 status = "disabled"; 227 }; 228 229 usb_host_ehci: usb@30140000 { 230 compatible = "generic-ehci"; 231 reg = <0x30140000 0x20000>; 232 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 233 phys = <&u2phy_host>; 234 phy-names = "usb"; 235 status = "disabled"; 236 }; 237 238 usb_host_ohci: usb@30160000 { 239 compatible = "generic-ohci"; 240 reg = <0x30160000 0x20000>; 241 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 242 phys = <&u2phy_host>; 243 phy-names = "usb"; 244 status = "disabled"; 245 }; 246 247 usb20_otg: usb@30180000 { 248 compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb", 249 "snps,dwc2"; 250 reg = <0x30180000 0x40000>; 251 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 252 hnp-srp-disable; 253 dr_mode = "otg"; 254 phys = <&u2phy_otg>; 255 phy-names = "usb"; 256 status = "disabled"; 257 }; 258 259 sfc: sfc@301c0000 { 260 compatible = "rockchip,sfc"; 261 reg = <0x301c0000 0x200>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 266 clock-names = "clk_sfc", "hclk_sfc"; 267 pinctrl-0 = <&sfc_pins>; 268 pinctrl-names = "default"; 269 status = "disabled"; 270 }; 271 272 gmac: ethernet@30200000 { 273 compatible = "rockchip,rv1108-gmac"; 274 reg = <0x30200000 0x10000>; 275 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 276 interrupt-names = "macirq"; 277 rockchip,grf = <&grf>; 278 clocks = <&cru SCLK_MAC>, 279 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 280 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 281 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 282 clock-names = "stmmaceth", 283 "mac_clk_rx", "mac_clk_tx", 284 "clk_mac_ref", "clk_mac_refout", 285 "aclk_mac", "pclk_mac"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&rmii_pins>; 288 phy-mode = "rmii"; 289 max-speed = <100>; 290 status = "disabled"; 291 }; 292 293 gic: interrupt-controller@32010000 { 294 compatible = "arm,gic-400"; 295 interrupt-controller; 296 #interrupt-cells = <3>; 297 #address-cells = <0>; 298 299 reg = <0x32011000 0x1000>, 300 <0x32012000 0x1000>, 301 <0x32014000 0x2000>, 302 <0x32016000 0x2000>; 303 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 304 }; 305 306 pinctrl: pinctrl { 307 compatible = "rockchip,rv1108-pinctrl"; 308 rockchip,grf = <&grf>; 309 rockchip,pmu = <&pmugrf>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges; 313 314 gpio0: gpio0@20030000 { 315 compatible = "rockchip,gpio-bank"; 316 reg = <0x20030000 0x100>; 317 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&xin24m>; 319 320 gpio-controller; 321 #gpio-cells = <2>; 322 323 interrupt-controller; 324 #interrupt-cells = <2>; 325 }; 326 327 gpio1: gpio1@10310000 { 328 compatible = "rockchip,gpio-bank"; 329 reg = <0x10310000 0x100>; 330 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&xin24m>; 332 333 gpio-controller; 334 #gpio-cells = <2>; 335 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 }; 339 340 gpio2: gpio2@10320000 { 341 compatible = "rockchip,gpio-bank"; 342 reg = <0x10320000 0x100>; 343 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&xin24m>; 345 346 gpio-controller; 347 #gpio-cells = <2>; 348 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 }; 352 353 gpio3: gpio3@10330000 { 354 compatible = "rockchip,gpio-bank"; 355 reg = <0x10330000 0x100>; 356 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&xin24m>; 358 359 gpio-controller; 360 #gpio-cells = <2>; 361 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 }; 365 366 pcfg_pull_up: pcfg-pull-up { 367 bias-pull-up; 368 }; 369 370 pcfg_pull_down: pcfg-pull-down { 371 bias-pull-down; 372 }; 373 374 pcfg_pull_none: pcfg-pull-none { 375 bias-disable; 376 }; 377 378 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { 379 drive-strength = <8>; 380 }; 381 382 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 383 drive-strength = <12>; 384 }; 385 386 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { 387 bias-pull-up; 388 drive-strength = <8>; 389 }; 390 391 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { 392 drive-strength = <4>; 393 }; 394 395 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { 396 bias-pull-up; 397 drive-strength = <4>; 398 }; 399 400 pcfg_pull_none_smt: pcfg-pull-none-smt { 401 bias-disable; 402 input-schmitt-enable; 403 }; 404 405 pcfg_output_high: pcfg-output-high { 406 output-high; 407 }; 408 409 pcfg_output_low: pcfg-output-low { 410 output-low; 411 }; 412 413 pcfg_input_high: pcfg-input-high { 414 bias-pull-up; 415 input-enable; 416 }; 417 418 gmac { 419 rmii_pins: rmii-pins { 420 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 421 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, 422 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 423 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 424 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 425 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 426 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, 427 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, 428 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, 429 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 430 }; 431 }; 432 433 i2c0 { 434 i2c0_xfer: i2c0-xfer { 435 rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>, 436 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>; 437 }; 438 }; 439 440 i2c1 { 441 i2c1_xfer: i2c1-xfer { 442 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, 443 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 444 }; 445 }; 446 447 i2c2m1 { 448 i2c2m1_xfer: i2c2m1-xfer { 449 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, 450 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; 451 }; 452 453 i2c2m1_gpio: i2c2m1-gpio { 454 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, 455 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 456 }; 457 }; 458 459 i2c2m05v { 460 i2c2m05v_xfer: i2c2m05v-xfer { 461 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 462 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; 463 }; 464 465 i2c2m05v_gpio: i2c2m05v-gpio { 466 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, 467 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 468 }; 469 }; 470 471 i2c3 { 472 i2c3_xfer: i2c3-xfer { 473 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 474 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 475 }; 476 }; 477 478 sfc { 479 sfc_pins: sfc-pins { 480 rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>, 481 <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>, 482 <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>, 483 <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>, 484 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, 485 <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>; 486 }; 487 }; 488 489 sdmmc { 490 sdmmc_clk: sdmmc-clk { 491 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; 492 }; 493 494 sdmmc_cmd: sdmmc-cmd { 495 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 496 }; 497 498 sdmmc_cd: sdmmc-cd { 499 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 500 }; 501 502 sdmmc_bus1: sdmmc-bus1 { 503 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 504 }; 505 506 sdmmc_bus4: sdmmc-bus4 { 507 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, 508 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, 509 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, 510 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 511 }; 512 }; 513 514 uart0 { 515 uart0_xfer: uart0-xfer { 516 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, 517 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 518 }; 519 520 uart0_cts: uart0-cts { 521 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; 522 }; 523 524 uart0_rts: uart0-rts { 525 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 526 }; 527 528 uart0_rts_gpio: uart0-rts-gpio { 529 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 530 }; 531 }; 532 533 uart1 { 534 uart1_xfer: uart1-xfer { 535 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, 536 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; 537 }; 538 539 uart1_cts: uart1-cts { 540 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 541 }; 542 543 uart01rts: uart1-rts { 544 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 545 }; 546 }; 547 548 uart2m0 { 549 uart2m0_xfer: uart2m0-xfer { 550 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, 551 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 552 }; 553 }; 554 555 uart2m1 { 556 uart2m1_xfer: uart2m1-xfer { 557 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, 558 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 559 }; 560 }; 561 562 uart2_5v { 563 uart2_5v_cts: uart2_5v-cts { 564 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; 565 }; 566 567 uart2_5v_rts: uart2_5v-rts { 568 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 569 }; 570 }; 571 }; 572 573 dmc: dmc@202b0000 { 574 u-boot,dm-pre-reloc; 575 compatible = "rockchip,rv1108-dmc"; 576 reg = <0x202b0000 0x400 577 0x20210000 0x400 578 0x31070000 0x40 579 0x10300000 0xf94 580 0x20060000 0x38c 581 0x20200000 0x1f0 582 0x20010000 0x78>; 583 }; 584}; 585