1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/rv1108-cru.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 compatible = "rockchip,rv1108"; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 spi0 = &sfc; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@f00 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a7"; 34 reg = <0xf00>; 35 }; 36 }; 37 38 arm-pmu { 39 compatible = "arm,cortex-a7-pmu"; 40 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 41 }; 42 43 timer { 44 compatible = "arm,armv7-timer"; 45 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, 46 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 47 clock-frequency = <24000000>; 48 }; 49 50 xin24m: oscillator { 51 compatible = "fixed-clock"; 52 clock-frequency = <24000000>; 53 clock-output-names = "xin24m"; 54 #clock-cells = <0>; 55 }; 56 57 amba { 58 compatible = "simple-bus"; 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 pdma: pdma@102a0000 { 64 compatible = "arm,pl330", "arm,primecell"; 65 reg = <0x102a0000 0x4000>; 66 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 67 #dma-cells = <1>; 68 arm,pl330-broken-no-flushp; 69 clocks = <&cru ACLK_DMAC>; 70 clock-names = "apb_pclk"; 71 }; 72 }; 73 74 bus_intmem@10080000 { 75 compatible = "mmio-sram"; 76 reg = <0x10080000 0x2000>; 77 #address-cells = <1>; 78 #size-cells = <1>; 79 ranges = <0 0x10080000 0x2000>; 80 }; 81 82 uart2: serial@10210000 { 83 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 84 reg = <0x10210000 0x100>; 85 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 86 reg-shift = <2>; 87 reg-io-width = <4>; 88 clock-frequency = <24000000>; 89 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 90 clock-names = "baudclk", "apb_pclk"; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&uart2m0_xfer>; 93 status = "disabled"; 94 }; 95 96 uart1: serial@10220000 { 97 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 98 reg = <0x10220000 0x100>; 99 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 100 reg-shift = <2>; 101 reg-io-width = <4>; 102 clock-frequency = <24000000>; 103 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 104 clock-names = "baudclk", "apb_pclk"; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&uart1_xfer>; 107 status = "disabled"; 108 }; 109 110 uart0: serial@10230000 { 111 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 112 reg = <0x10230000 0x100>; 113 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 114 reg-shift = <2>; 115 reg-io-width = <4>; 116 clock-frequency = <24000000>; 117 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 118 clock-names = "baudclk", "apb_pclk"; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 121 status = "disabled"; 122 }; 123 124 grf: syscon@10300000 { 125 compatible = "rockchip,rv1108-grf", "syscon"; 126 reg = <0x10300000 0x1000>; 127 }; 128 129 u2phy: usb2-phy@10300100 { 130 compatible = "rockchip,rv1108-usb2phy"; 131 reg = <0x100 0x0c>; 132 rockchip,grf = <&grf>; 133 #phy-cells = <1>; 134 status = "disabled"; 135 136 u2phy_otg: otg-port { 137 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 138 interrupt-names = "otg-mux"; 139 #phy-cells = <0>; 140 status = "disabled"; 141 }; 142 143 u2phy_host: host-port { 144 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 145 interrupt-names = "linestate"; 146 #phy-cells = <0>; 147 status = "disabled"; 148 }; 149 }; 150 151 saradc: saradc@1038c000 { 152 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; 153 reg = <0x1038c000 0x100>; 154 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 155 #io-channel-cells = <1>; 156 clock-frequency = <1000000>; 157 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 158 clock-names = "saradc", "apb_pclk"; 159 status = "disabled"; 160 }; 161 162 pmugrf: syscon@20060000 { 163 compatible = "rockchip,rv1108-pmugrf", "syscon"; 164 reg = <0x20060000 0x1000>; 165 }; 166 167 cru: clock-controller@20200000 { 168 compatible = "rockchip,rv1108-cru"; 169 reg = <0x20200000 0x1000>; 170 rockchip,grf = <&grf>; 171 #clock-cells = <1>; 172 #reset-cells = <1>; 173 }; 174 175 usbgrf: syscon@202a0000 { 176 compatible = "rockchip,rv1108-usbgrf", "syscon"; 177 reg = <0x202a0000 0x1000>; 178 }; 179 180 emmc: dwmmc@30110000 { 181 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 182 clock-freq-min-max = <400000 150000000>; 183 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 184 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 185 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 186 fifo-depth = <0x100>; 187 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 188 reg = <0x30110000 0x4000>; 189 status = "disabled"; 190 }; 191 192 sdio: dwmmc@30120000 { 193 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 194 clock-freq-min-max = <400000 150000000>; 195 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 196 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 197 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 198 fifo-depth = <0x100>; 199 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 200 reg = <0x30120000 0x4000>; 201 status = "disabled"; 202 }; 203 204 sdmmc: dwmmc@30130000 { 205 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 206 clock-freq-min-max = <400000 100000000>; 207 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 208 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 209 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 210 fifo-depth = <0x100>; 211 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 212 reg = <0x30130000 0x4000>; 213 status = "disabled"; 214 }; 215 216 usb_host_ehci: usb@30140000 { 217 compatible = "generic-ehci"; 218 reg = <0x30140000 0x20000>; 219 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 220 phys = <&u2phy_host>; 221 phy-names = "usb"; 222 status = "disabled"; 223 }; 224 225 usb_host_ohci: usb@30160000 { 226 compatible = "generic-ohci"; 227 reg = <0x30160000 0x20000>; 228 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 229 phys = <&u2phy_host>; 230 phy-names = "usb"; 231 status = "disabled"; 232 }; 233 234 usb20_otg: usb@30180000 { 235 compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb", 236 "snps,dwc2"; 237 reg = <0x30180000 0x40000>; 238 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 239 hnp-srp-disable; 240 dr_mode = "otg"; 241 phys = <&u2phy_otg>; 242 phy-names = "usb"; 243 status = "disabled"; 244 }; 245 246 sfc: sfc@301c0000 { 247 compatible = "rockchip,sfc"; 248 reg = <0x301c0000 0x200>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 253 clock-names = "clk_sfc", "hclk_sfc"; 254 pinctrl-0 = <&sfc_pins>; 255 pinctrl-names = "default"; 256 status = "disabled"; 257 }; 258 259 gmac: ethernet@30200000 { 260 compatible = "rockchip,rv1108-gmac"; 261 reg = <0x30200000 0x10000>; 262 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 263 interrupt-names = "macirq"; 264 rockchip,grf = <&grf>; 265 clocks = <&cru SCLK_MAC>, 266 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 267 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 268 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 269 clock-names = "stmmaceth", 270 "mac_clk_rx", "mac_clk_tx", 271 "clk_mac_ref", "clk_mac_refout", 272 "aclk_mac", "pclk_mac"; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&rmii_pins>; 275 phy-mode = "rmii"; 276 max-speed = <100>; 277 status = "disabled"; 278 }; 279 280 gic: interrupt-controller@32010000 { 281 compatible = "arm,gic-400"; 282 interrupt-controller; 283 #interrupt-cells = <3>; 284 #address-cells = <0>; 285 286 reg = <0x32011000 0x1000>, 287 <0x32012000 0x1000>, 288 <0x32014000 0x2000>, 289 <0x32016000 0x2000>; 290 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 291 }; 292 293 pinctrl: pinctrl { 294 compatible = "rockchip,rv1108-pinctrl"; 295 rockchip,grf = <&grf>; 296 rockchip,pmu = <&pmugrf>; 297 #address-cells = <1>; 298 #size-cells = <1>; 299 ranges; 300 301 gpio0: gpio0@20030000 { 302 compatible = "rockchip,gpio-bank"; 303 reg = <0x20030000 0x100>; 304 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&xin24m>; 306 307 gpio-controller; 308 #gpio-cells = <2>; 309 310 interrupt-controller; 311 #interrupt-cells = <2>; 312 }; 313 314 gpio1: gpio1@10310000 { 315 compatible = "rockchip,gpio-bank"; 316 reg = <0x10310000 0x100>; 317 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&xin24m>; 319 320 gpio-controller; 321 #gpio-cells = <2>; 322 323 interrupt-controller; 324 #interrupt-cells = <2>; 325 }; 326 327 gpio2: gpio2@10320000 { 328 compatible = "rockchip,gpio-bank"; 329 reg = <0x10320000 0x100>; 330 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&xin24m>; 332 333 gpio-controller; 334 #gpio-cells = <2>; 335 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 }; 339 340 gpio3: gpio3@10330000 { 341 compatible = "rockchip,gpio-bank"; 342 reg = <0x10330000 0x100>; 343 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&xin24m>; 345 346 gpio-controller; 347 #gpio-cells = <2>; 348 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 }; 352 353 pcfg_pull_up: pcfg-pull-up { 354 bias-pull-up; 355 }; 356 357 pcfg_pull_down: pcfg-pull-down { 358 bias-pull-down; 359 }; 360 361 pcfg_pull_none: pcfg-pull-none { 362 bias-disable; 363 }; 364 365 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { 366 drive-strength = <8>; 367 }; 368 369 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 370 drive-strength = <12>; 371 }; 372 373 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { 374 bias-pull-up; 375 drive-strength = <8>; 376 }; 377 378 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { 379 drive-strength = <4>; 380 }; 381 382 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { 383 bias-pull-up; 384 drive-strength = <4>; 385 }; 386 387 pcfg_output_high: pcfg-output-high { 388 output-high; 389 }; 390 391 pcfg_output_low: pcfg-output-low { 392 output-low; 393 }; 394 395 pcfg_input_high: pcfg-input-high { 396 bias-pull-up; 397 input-enable; 398 }; 399 400 gmac { 401 rmii_pins: rmii-pins { 402 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 403 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, 404 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 405 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 406 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 407 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 408 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, 409 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, 410 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, 411 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 412 }; 413 }; 414 415 i2c1 { 416 i2c1_xfer: i2c1-xfer { 417 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, 418 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 419 }; 420 }; 421 422 i2c2m1 { 423 i2c2m1_xfer: i2c2m1-xfer { 424 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, 425 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; 426 }; 427 428 i2c2m1_gpio: i2c2m1-gpio { 429 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, 430 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 431 }; 432 }; 433 434 i2c2m05v { 435 i2c2m05v_xfer: i2c2m05v-xfer { 436 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 437 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; 438 }; 439 440 i2c2m05v_gpio: i2c2m05v-gpio { 441 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, 442 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 443 }; 444 }; 445 446 i2c3 { 447 i2c3_xfer: i2c3-xfer { 448 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 449 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 450 }; 451 }; 452 453 sfc { 454 sfc_pins: sfc-pins { 455 rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>, 456 <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>, 457 <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>, 458 <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>, 459 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, 460 <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>; 461 }; 462 }; 463 464 sdmmc { 465 sdmmc_clk: sdmmc-clk { 466 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; 467 }; 468 469 sdmmc_cmd: sdmmc-cmd { 470 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 471 }; 472 473 sdmmc_cd: sdmmc-cd { 474 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 475 }; 476 477 sdmmc_bus1: sdmmc-bus1 { 478 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 479 }; 480 481 sdmmc_bus4: sdmmc-bus4 { 482 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, 483 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, 484 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, 485 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; 486 }; 487 }; 488 489 uart0 { 490 uart0_xfer: uart0-xfer { 491 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, 492 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 493 }; 494 495 uart0_cts: uart0-cts { 496 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; 497 }; 498 499 uart0_rts: uart0-rts { 500 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 501 }; 502 503 uart0_rts_gpio: uart0-rts-gpio { 504 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 505 }; 506 }; 507 508 uart1 { 509 uart1_xfer: uart1-xfer { 510 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, 511 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; 512 }; 513 514 uart1_cts: uart1-cts { 515 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 516 }; 517 518 uart01rts: uart1-rts { 519 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 520 }; 521 }; 522 523 uart2m0 { 524 uart2m0_xfer: uart2m0-xfer { 525 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, 526 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 527 }; 528 }; 529 530 uart2m1 { 531 uart2m1_xfer: uart2m1-xfer { 532 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, 533 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 534 }; 535 }; 536 537 uart2_5v { 538 uart2_5v_cts: uart2_5v-cts { 539 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; 540 }; 541 542 uart2_5v_rts: uart2_5v-rts { 543 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 544 }; 545 }; 546 }; 547 548 dmc: dmc@202b0000 { 549 u-boot,dm-pre-reloc; 550 compatible = "rockchip,rv1108-dmc"; 551 reg = <0x202b0000 0x400 552 0x20210000 0x400 553 0x31070000 0x40 554 0x10300000 0xf94 555 0x20060000 0x38c 556 0x20200000 0x1f0 557 0x20010000 0x78>; 558 }; 559}; 560