1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5#include <dt-bindings/clock/rv1106-cru.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11#include <dt-bindings/soc/rockchip-system-status.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1106"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 serial0 = &uart0; 30 serial1 = &uart1; 31 serial2 = &uart2; 32 serial3 = &uart3; 33 serial4 = &uart4; 34 serial5 = &uart5; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu0: cpu@f00 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a7"; 44 reg = <0xf00>; 45 }; 46 }; 47 48 arm-pmu { 49 compatible = "arm,cortex-a7-pmu"; 50 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 51 interrupt-affinity = <&cpu0>; 52 }; 53 54 fiq_debugger: fiq-debugger { 55 compatible = "rockchip,fiq-debugger"; 56 rockchip,serial-id = <2>; 57 rockchip,wake-irq = <0>; 58 rockchip,irq-mode-enable = <0>; 59 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 60 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 61 status = "disabled"; 62 }; 63 64 reserved-memory { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 ranges; 68 69 linux,cma { 70 compatible = "shared-dma-pool"; 71 inactive; 72 reusable; 73 size = <0x800000>; 74 linux,cma-default; 75 }; 76 }; 77 78 timer { 79 compatible = "arm,armv7-timer"; 80 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 81 clock-frequency = <24000000>; 82 }; 83 84 xin24m: oscillator { 85 compatible = "fixed-clock"; 86 clock-frequency = <24000000>; 87 clock-output-names = "xin24m"; 88 #clock-cells = <0>; 89 }; 90 91 grf: syscon@ff000000 { 92 compatible = "rockchip,rv1106-grf", "syscon", "simple-mfd"; 93 reg = <0xff000000 0x68000>; 94 }; 95 96 rtc: rtc@ff1c0000 { 97 compatible = "rockchip,rtc-1.0"; 98 reg = <0xff1c0000 0x1000>; 99 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 100 clocks = <&cru PCLK_VI_RTC_PHY>; 101 clock-names = "pclk"; 102 status = "disabled"; 103 }; 104 105 gic: interrupt-controller@ff1f0000 { 106 compatible = "arm,gic-400"; 107 interrupt-controller; 108 #interrupt-cells = <3>; 109 #address-cells = <0>; 110 111 reg = <0xff1f1000 0x1000>, 112 <0xff1f2000 0x2000>, 113 <0xff1f4000 0x2000>, 114 <0xff1f6000 0x2000>; 115 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 116 }; 117 118 arm-debug@ff200000 { 119 compatible = "rockchip,debug"; 120 reg = <0xff200000 0x1000>; 121 }; 122 123 i2c0: i2c@ff310000 { 124 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 125 reg = <0xff310000 0x1000>; 126 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 127 #address-cells = <1>; 128 #size-cells = <0>; 129 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 130 clock-names = "i2c", "pclk"; 131 status = "disabled"; 132 }; 133 134 i2c1: i2c@ff320000 { 135 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 136 reg = <0xff320000 0x1000>; 137 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 141 clock-names = "i2c", "pclk"; 142 status = "disabled"; 143 }; 144 145 dsm: codec-digital@ff340000 { 146 compatible = "rockchip,rv1106-codec-digital", "rockchip,codec-digital-v1"; 147 reg = <0xff340000 0x1000>; 148 clocks = <&cru MCLK_DSM>, <&cru PCLK_DSM>; 149 clock-names = "dac", "pclk"; 150 resets = <&cru SRST_M_DSM>; 151 reset-names = "reset" ; 152 rockchip,grf = <&grf>; 153 rockchip,pwm-output-mode; 154 #sound-dai-cells = <0>; 155 status = "disabled"; 156 }; 157 158 cru: clock-controller@ff3a0000 { 159 compatible = "rockchip,rv1106-cru"; 160 reg = <0xff3a0000 0x20000>; 161 rockchip,grf = <&grf>; 162 #clock-cells = <1>; 163 #reset-cells = <1>; 164 165 assigned-clocks = 166 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 167 <&cru ARMCLK>, 168 <&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>, 169 <&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>, 170 <&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>, 171 <&cru HCLK_PMU_ROOT>; 172 assigned-clock-rates = 173 <1188000000>, <1000000000>, 174 <816000000>, 175 <400000000>, <200000000>, 176 <100000000>, <300000000>, 177 <100000000>, <100000000>, 178 <200000000>; 179 }; 180 181 dmac: dma-controller@ff420000 { 182 compatible = "arm,pl330", "arm,primecell"; 183 reg = <0xff420000 0x4000>; 184 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 193 #dma-cells = <1>; 194 clocks = <&cru ACLK_DMAC>; 195 clock-names = "apb_pclk"; 196 arm,pl330-periph-burst; 197 }; 198 199 crypto: crypto@ff440000 { 200 compatible = "rockchip,crypto_v3"; 201 reg = <0xff440000 0x2000>; 202 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 204 clock-names = "aclk", "hclk", "sclk", "pka"; 205 assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 206 assigned-clock-rates = <300000000>, <300000000>; 207 resets = <&cru SRST_CORE_CRYPTO>; 208 reset-names = "crypto-rst"; 209 status = "disabled"; 210 }; 211 212 rng: rng@ff448000 { 213 compatible = "rockchip,trngv1"; 214 reg = <0xff448000 0x200>; 215 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&cru HCLK_TRNG_NS>; 217 clock-names = "hclk_trng"; 218 resets = <&cru SRST_H_TRNG_NS>; 219 reset-names = "reset"; 220 status = "disabled"; 221 }; 222 223 i2c2: i2c@ff450000 { 224 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 225 reg = <0xff450000 0x1000>; 226 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 230 clock-names = "i2c", "pclk"; 231 status = "disabled"; 232 }; 233 234 i2c3: i2c@ff460000 { 235 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 236 reg = <0xff460000 0x1000>; 237 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 241 clock-names = "i2c", "pclk"; 242 status = "disabled"; 243 }; 244 245 i2c4: i2c@ff470000 { 246 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 247 reg = <0xff470000 0x1000>; 248 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 252 clock-names = "i2c", "pclk"; 253 status = "disabled"; 254 }; 255 256 uart0: serial@ff4a0000 { 257 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 258 reg = <0xff4a0000 0x100>; 259 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 260 reg-shift = <2>; 261 reg-io-width = <4>; 262 dmas = <&dmac 7>, <&dmac 6>; 263 clock-frequency = <24000000>; 264 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 265 clock-names = "baudclk", "apb_pclk"; 266 status = "disabled"; 267 }; 268 269 uart1: serial@ff4b0000 { 270 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 271 reg = <0xff4b0000 0x100>; 272 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 273 reg-shift = <2>; 274 reg-io-width = <4>; 275 dmas = <&dmac 9>, <&dmac 8>; 276 clock-frequency = <24000000>; 277 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 278 clock-names = "baudclk", "apb_pclk"; 279 status = "disabled"; 280 }; 281 282 uart2: serial@ff4c0000 { 283 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 284 reg = <0xff4c0000 0x100>; 285 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 286 reg-shift = <2>; 287 reg-io-width = <4>; 288 dmas = <&dmac 11>, <&dmac 10>; 289 clock-frequency = <24000000>; 290 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 291 clock-names = "baudclk", "apb_pclk"; 292 status = "disabled"; 293 }; 294 295 uart3: serial@ff4d0000 { 296 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 297 reg = <0xff4d0000 0x100>; 298 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 299 reg-shift = <2>; 300 reg-io-width = <4>; 301 dmas = <&dmac 13>, <&dmac 12>; 302 clock-frequency = <24000000>; 303 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 304 clock-names = "baudclk", "apb_pclk"; 305 status = "disabled"; 306 }; 307 308 uart4: serial@ff4e0000 { 309 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 310 reg = <0xff4e0000 0x100>; 311 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 312 reg-shift = <2>; 313 reg-io-width = <4>; 314 dmas = <&dmac 15>, <&dmac 14>; 315 clock-frequency = <24000000>; 316 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 317 clock-names = "baudclk", "apb_pclk"; 318 status = "disabled"; 319 }; 320 321 uart5: serial@ff4f0000 { 322 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 323 reg = <0xff4f0000 0x100>; 324 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 325 reg-shift = <2>; 326 reg-io-width = <4>; 327 dmas = <&dmac 17>, <&dmac 16>; 328 clock-frequency = <24000000>; 329 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 330 clock-names = "baudclk", "apb_pclk"; 331 status = "disabled"; 332 }; 333 334 saradc: saradc@ff3c0000 { 335 compatible = "rockchip,rk3588-saradc"; 336 reg = <0xff3c0000 0x100>; 337 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 338 #io-channel-cells = <1>; 339 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 340 clock-names = "saradc", "apb_pclk"; 341 resets = <&cru SRST_P_SARADC>; 342 reset-names = "saradc-apb"; 343 status = "disabled"; 344 }; 345 346 sdio: mmc@ff9a0000 { 347 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 348 reg = <0xff9a0000 0x4000>; 349 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 351 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 352 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 353 fifo-depth = <0x100>; 354 max-frequency = <200000000>; 355 status = "disabled"; 356 }; 357 358 gmac: ethernet@ffa80000 { 359 compatible = "rockchip,rv1106-gmac", "snps,dwmac-4.20a"; 360 reg = <0xffa80000 0x10000>; 361 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 363 interrupt-names = "macirq", "eth_wake_irq"; 364 rockchip,grf = <&grf>; 365 clocks = <&cru CLK_GMAC0_TX_50M_O>, <&cru CLK_GMAC0_REF_50M>, 366 <&cru ACLK_MAC>, <&cru PCLK_MAC>; 367 clock-names = "stmmaceth", "clk_mac_ref", 368 "aclk_mac", "pclk_mac"; 369 resets = <&cru SRST_A_MAC>; 370 reset-names = "stmmaceth"; 371 372 snps,mixed-burst; 373 snps,tso; 374 375 snps,axi-config = <&stmmac_axi_setup>; 376 snps,mtl-rx-config = <&mtl_rx_setup>; 377 snps,mtl-tx-config = <&mtl_tx_setup>; 378 379 phy-mode = "rmii"; 380 clock_in_out = "input"; 381 phy-handle = <&rmii_phy>; 382 status = "disabled"; 383 384 mdio: mdio { 385 compatible = "snps,dwmac-mdio"; 386 #address-cells = <0x1>; 387 #size-cells = <0x0>; 388 rmii_phy: ethernet-phy@2 { 389 compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22"; 390 reg = <2>; 391 clocks = <&cru CLK_MACPHY>; 392 resets = <&cru SRST_MACPHY>; 393 phy-is-integrated; 394 }; 395 }; 396 397 stmmac_axi_setup: stmmac-axi-config { 398 snps,wr_osr_lmt = <4>; 399 snps,rd_osr_lmt = <8>; 400 snps,blen = <0 0 0 0 16 8 4>; 401 }; 402 403 mtl_rx_setup: rx-queues-config { 404 snps,rx-queues-to-use = <1>; 405 queue0 {}; 406 }; 407 408 mtl_tx_setup: tx-queues-config { 409 snps,tx-queues-to-use = <1>; 410 queue0 {}; 411 }; 412 }; 413 414 emmc: mmc@ffa90000 { 415 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 416 reg = <0xffa90000 0x4000>; 417 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&cru HCLK_EMMC>, <&cru CCLK_SRC_EMMC>, 419 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 420 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 421 fifo-depth = <0x100>; 422 max-frequency = <200000000>; 423 rockchip,use-v2-tuning; 424 status = "disabled"; 425 }; 426 427 sfc: spi@ffac0000 { 428 compatible = "rockchip,sfc"; 429 reg = <0xffac0000 0x4000>; 430 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 432 clock-names = "clk_sfc", "hclk_sfc"; 433 assigned-clocks = <&cru SCLK_SFC>; 434 assigned-clock-rates = <75000000>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 status = "disabled"; 438 }; 439 440 sdmmc: mmc@ffaa0000 { 441 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 442 reg = <0xffaa0000 0x4000>; 443 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>, 445 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 446 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 447 fifo-depth = <0x100>; 448 max-frequency = <200000000>; 449 status = "disabled"; 450 }; 451 452 i2s0_8ch: i2s@ffae0000 { 453 compatible = "rockchip,rv1106-i2s-tdm"; 454 reg = <0xffae0000 0x1000>; 455 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0>; 457 clock-names = "mclk_tx", "mclk_rx", "hclk"; 458 dmas = <&dmac 22>, <&dmac 21>; 459 dma-names = "tx", "rx"; 460 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 461 reset-names = "tx-m", "rx-m"; 462 rockchip,clk-trcm = <1>; 463 #sound-dai-cells = <0>; 464 status = "disabled"; 465 }; 466}; 467