1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5#include <dt-bindings/clock/rv1106-cru.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11#include <dt-bindings/soc/rockchip-system-status.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1106"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 csi2dphy0 = &csi2_dphy0; 24 csi2dphy1 = &csi2_dphy1; 25 csi2dphy2 = &csi2_dphy2; 26 ethernet0 = &gmac; 27 gpio0 = &gpio0; 28 gpio1 = &gpio1; 29 gpio2 = &gpio2; 30 gpio3 = &gpio3; 31 gpio4 = &gpio4; 32 i2c0 = &i2c0; 33 i2c1 = &i2c1; 34 i2c2 = &i2c2; 35 i2c3 = &i2c3; 36 i2c4 = &i2c4; 37 mmc0 = &emmc; 38 mmc1 = &sdmmc; 39 mmc2 = &sdio; 40 rkcif_mipi_lvds0 = &rkcif_mipi_lvds; 41 rkcif_mipi_lvds1 = &rkcif_mipi_lvds1; 42 serial0 = &uart0; 43 serial1 = &uart1; 44 serial2 = &uart2; 45 serial3 = &uart3; 46 serial4 = &uart4; 47 serial5 = &uart5; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &sfc; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 cpu0: cpu@f00 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a7"; 60 reg = <0xf00>; 61 }; 62 }; 63 64 arm-pmu { 65 compatible = "arm,cortex-a7-pmu"; 66 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 67 interrupt-affinity = <&cpu0>; 68 }; 69 70 cpuinfo { 71 compatible = "rockchip,cpuinfo"; 72 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 73 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 74 }; 75 76 /* dphy0 full mode */ 77 csi2_dphy0: csi2-dphy0 { 78 compatible = "rockchip,rv1106-csi2-dphy"; 79 rockchip,hw = <&csi2_dphy_hw>; 80 status = "disabled"; 81 }; 82 83 /* dphy1 split mode 01 */ 84 csi2_dphy1: csi2-dphy1 { 85 compatible = "rockchip,rv1106-csi2-dphy"; 86 rockchip,hw = <&csi2_dphy_hw>; 87 status = "disabled"; 88 }; 89 90 /* dphy2 split mode 23 */ 91 csi2_dphy2: csi2-dphy2 { 92 compatible = "rockchip,rv1106-csi2-dphy"; 93 rockchip,hw = <&csi2_dphy_hw>; 94 status = "disabled"; 95 }; 96 97 display_subsystem: display-subsystem { 98 compatible = "rockchip,display-subsystem"; 99 ports = <&vop_out>; 100 status = "disabled"; 101 }; 102 103 fiq_debugger: fiq-debugger { 104 compatible = "rockchip,fiq-debugger"; 105 rockchip,serial-id = <2>; 106 rockchip,wake-irq = <0>; 107 rockchip,irq-mode-enable = <0>; 108 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 109 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 110 status = "disabled"; 111 }; 112 113 mpp_srv: mpp-srv { 114 compatible = "rockchip,mpp-service"; 115 rockchip,taskqueue-count = <2>; 116 status = "disabled"; 117 }; 118 119 mpp_vcodec: mpp-vcodec { 120 compatible = "rockchip,vcodec"; 121 status = "disabled"; 122 }; 123 124 reserved-memory { 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges; 128 129 linux,cma { 130 compatible = "shared-dma-pool"; 131 inactive; 132 reusable; 133 size = <0x800000>; 134 linux,cma-default; 135 }; 136 }; 137 138 rkcif_dvp: rkcif-dvp { 139 compatible = "rockchip,rkcif-dvp"; 140 rockchip,hw = <&rkcif>; 141 status = "disabled"; 142 }; 143 144 rkcif_dvp_sditf: rkcif-dvp-sditf { 145 compatible = "rockchip,rkcif-sditf"; 146 rockchip,cif = <&rkcif_dvp>; 147 status = "disabled"; 148 }; 149 150 rkcif_mipi_lvds: rkcif-mipi-lvds { 151 compatible = "rockchip,rkcif-mipi-lvds"; 152 rockchip,hw = <&rkcif>; 153 status = "disabled"; 154 }; 155 156 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { 157 compatible = "rockchip,rkcif-sditf"; 158 rockchip,cif = <&rkcif_mipi_lvds>; 159 status = "disabled"; 160 }; 161 162 rkcif_mipi_lvds1: rkcif-mipi-lvds1 { 163 compatible = "rockchip,rkcif-mipi-lvds"; 164 rockchip,hw = <&rkcif>; 165 status = "disabled"; 166 }; 167 168 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { 169 compatible = "rockchip,rkcif-sditf"; 170 rockchip,cif = <&rkcif_mipi_lvds1>; 171 status = "disabled"; 172 }; 173 174 rkisp_vir0: rkisp-vir0 { 175 compatible = "rockchip,rkisp-vir"; 176 rockchip,hw = <&rkisp>; 177 dvbm = <&rkdvbm>; 178 status = "disabled"; 179 }; 180 181 rkisp_vir1: rkisp-vir1 { 182 compatible = "rockchip,rkisp-vir"; 183 rockchip,hw = <&rkisp>; 184 status = "disabled"; 185 }; 186 187 rkisp_vir2: rkisp-vir2 { 188 compatible = "rockchip,rkisp-vir"; 189 rockchip,hw = <&rkisp>; 190 status = "disabled"; 191 }; 192 193 rkisp_vir3: rkisp-vir3 { 194 compatible = "rockchip,rkisp-vir"; 195 rockchip,hw = <&rkisp>; 196 status = "disabled"; 197 }; 198 199 rockchip_system_monitor: rockchip-system-monitor { 200 compatible = "rockchip,system-monitor"; 201 202 rockchip,thermal-zone = "soc-thermal"; 203 }; 204 205 thermal_zones: thermal-zones { 206 soc_thermal: soc-thermal { 207 polling-delay-passive = <20>; /* milliseconds */ 208 polling-delay = <1000>; /* milliseconds */ 209 sustainable-power = <2100>; /* milliwatts */ 210 211 thermal-sensors = <&tsadc 0>; 212 trips { 213 threshold: trip-point-0 { 214 temperature = <75000>; 215 hysteresis = <2000>; 216 type = "passive"; 217 }; 218 target: trip-point-1 { 219 temperature = <85000>; 220 hysteresis = <2000>; 221 type = "passive"; 222 }; 223 soc_crit: soc-crit { 224 /* millicelsius */ 225 temperature = <115000>; 226 /* millicelsius */ 227 hysteresis = <2000>; 228 type = "critical"; 229 }; 230 }; 231 }; 232 }; 233 234 timer { 235 compatible = "arm,armv7-timer"; 236 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 237 clock-frequency = <24000000>; 238 }; 239 240 xin24m: oscillator { 241 compatible = "fixed-clock"; 242 clock-frequency = <24000000>; 243 clock-output-names = "xin24m"; 244 #clock-cells = <0>; 245 }; 246 247 grf: syscon@ff000000 { 248 compatible = "rockchip,rv1106-grf", "syscon", "simple-mfd"; 249 reg = <0xff000000 0x68000>; 250 251 grf_cru: grf-clock-controller { 252 compatible = "rockchip,rv1106-grf-cru"; 253 #clock-cells = <1>; 254 }; 255 256 reboot_mode: reboot-mode { 257 compatible = "syscon-reboot-mode"; 258 offset = <0x20200>; 259 mode-bootloader = <BOOT_BL_DOWNLOAD>; 260 mode-charge = <BOOT_CHARGING>; 261 mode-fastboot = <BOOT_FASTBOOT>; 262 mode-loader = <BOOT_BL_DOWNLOAD>; 263 mode-normal = <BOOT_NORMAL>; 264 mode-recovery = <BOOT_RECOVERY>; 265 mode-ums = <BOOT_UMS>; 266 mode-panic = <BOOT_PANIC>; 267 mode-watchdog = <BOOT_WATCHDOG>; 268 }; 269 270 rgb: rgb { 271 compatible = "rockchip,rv1106-rgb"; 272 status = "disabled"; 273 274 ports { 275 #address-cells = <1>; 276 #size-cells = <0>; 277 278 port@0 { 279 reg = <0>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 283 rgb_in_vop: endpoint@0 { 284 reg = <0>; 285 remote-endpoint = <&vop_out_rgb>; 286 }; 287 }; 288 }; 289 }; 290 }; 291 292 rtc: rtc@ff1c0000 { 293 compatible = "rockchip,rtc-1.0"; 294 reg = <0xff1c0000 0x1000>; 295 rockchip,grf = <&grf>; 296 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cru PCLK_VI_RTC_PHY>, <&cru PCLK_VI_RTC_TEST>; 298 clock-names = "pclk_phy", "pclk_test"; 299 assigned-clocks = <&cru PCLK_VI_RTC_PHY>; 300 assigned-clock-rates = <24000000>; 301 status = "disabled"; 302 }; 303 304 gic: interrupt-controller@ff1f0000 { 305 compatible = "arm,gic-400"; 306 interrupt-controller; 307 #interrupt-cells = <3>; 308 #address-cells = <0>; 309 310 reg = <0xff1f1000 0x1000>, 311 <0xff1f2000 0x2000>, 312 <0xff1f4000 0x2000>, 313 <0xff1f6000 0x2000>; 314 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 315 }; 316 317 arm-debug@ff200000 { 318 compatible = "rockchip,debug"; 319 reg = <0xff200000 0x1000>; 320 }; 321 322 i2c0: i2c@ff310000 { 323 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 324 reg = <0xff310000 0x1000>; 325 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 329 clock-names = "i2c", "pclk"; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&i2c0m0_xfer>; 332 status = "disabled"; 333 }; 334 335 i2c1: i2c@ff320000 { 336 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 337 reg = <0xff320000 0x1000>; 338 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 342 clock-names = "i2c", "pclk"; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&i2c1m0_xfer>; 345 status = "disabled"; 346 }; 347 348 dsm: codec-digital@ff340000 { 349 compatible = "rockchip,rv1106-codec-digital", "rockchip,codec-digital-v1"; 350 reg = <0xff340000 0x1000>; 351 clocks = <&cru MCLK_DSM>, <&cru PCLK_DSM>; 352 clock-names = "dac", "pclk"; 353 resets = <&cru SRST_M_DSM>; 354 reset-names = "reset" ; 355 rockchip,grf = <&grf>; 356 rockchip,pwm-output-mode; 357 #sound-dai-cells = <0>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&dsmaudio_pins>; 360 status = "disabled"; 361 }; 362 363 pwm0: pwm@ff350000 { 364 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 365 reg = <0xff350000 0x10>; 366 #pwm-cells = <3>; 367 pinctrl-names = "active"; 368 pinctrl-0 = <&pwm0m0_pins>; 369 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; 370 clock-names = "pwm", "pclk"; 371 status = "disabled"; 372 }; 373 374 pwm1: pwm@ff350010 { 375 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 376 reg = <0xff350010 0x10>; 377 #pwm-cells = <3>; 378 pinctrl-names = "active"; 379 pinctrl-0 = <&pwm1m0_pins>; 380 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; 381 clock-names = "pwm", "pclk"; 382 status = "disabled"; 383 }; 384 385 pwm2: pwm@ff350020 { 386 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 387 reg = <0xff350020 0x10>; 388 #pwm-cells = <3>; 389 pinctrl-names = "active"; 390 pinctrl-0 = <&pwm2m0_pins>; 391 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; 392 clock-names = "pwm", "pclk"; 393 status = "disabled"; 394 }; 395 396 pwm3: pwm@ff350030 { 397 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 398 reg = <0xff350030 0x10>; 399 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 401 #pwm-cells = <3>; 402 pinctrl-names = "active"; 403 pinctrl-0 = <&pwm3m0_pins>; 404 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; 405 clock-names = "pwm", "pclk"; 406 status = "disabled"; 407 }; 408 409 pwm4: pwm@ff360000 { 410 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 411 reg = <0xff360000 0x10>; 412 #pwm-cells = <3>; 413 pinctrl-names = "active"; 414 pinctrl-0 = <&pwm4m0_pins>; 415 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 416 clock-names = "pwm", "pclk"; 417 status = "disabled"; 418 }; 419 420 pwm5: pwm@ff360010 { 421 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 422 reg = <0xff360010 0x10>; 423 #pwm-cells = <3>; 424 pinctrl-names = "active"; 425 pinctrl-0 = <&pwm5m0_pins>; 426 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 427 clock-names = "pwm", "pclk"; 428 status = "disabled"; 429 }; 430 431 pwm6: pwm@ff360020 { 432 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 433 reg = <0xff360020 0x10>; 434 #pwm-cells = <3>; 435 pinctrl-names = "active"; 436 pinctrl-0 = <&pwm6m0_pins>; 437 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 438 clock-names = "pwm", "pclk"; 439 status = "disabled"; 440 }; 441 442 pwm7: pwm@ff360030 { 443 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 444 reg = <0xff360030 0x10>; 445 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 447 #pwm-cells = <3>; 448 pinctrl-names = "active"; 449 pinctrl-0 = <&pwm7m0_pins>; 450 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 451 clock-names = "pwm", "pclk"; 452 status = "disabled"; 453 }; 454 455 pmu_mailbox: mailbox@ff378000 { 456 compatible = "rockchip,rv1106-mailbox", 457 "rockchip,rk3368-mailbox"; 458 reg = <0xff378000 0x200>; 459 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&cru PCLK_PMU_MAILBOX>; 461 clock-names = "pclk_mailbox"; 462 #mbox-cells = <1>; 463 status = "disabled"; 464 }; 465 466 pmuioc: syscon@ff388000 { 467 compatible = "rockchip,rv1106-pmuioc", "syscon"; 468 reg = <0xff388000 0x1000>; 469 }; 470 471 cru: clock-controller@ff3a0000 { 472 compatible = "rockchip,rv1106-cru"; 473 reg = <0xff3a0000 0x20000>; 474 rockchip,grf = <&grf>; 475 #clock-cells = <1>; 476 #reset-cells = <1>; 477 478 assigned-clocks = 479 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 480 <&cru ARMCLK>, 481 <&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>, 482 <&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>, 483 <&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>, 484 <&cru HCLK_PMU_ROOT>; 485 assigned-clock-rates = 486 <1188000000>, <1000000000>, 487 <816000000>, 488 <400000000>, <200000000>, 489 <100000000>, <300000000>, 490 <100000000>, <100000000>, 491 <200000000>; 492 }; 493 494 saradc: saradc@ff3c0000 { 495 compatible = "rockchip,rk3588-saradc"; 496 reg = <0xff3c0000 0x100>; 497 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 498 #io-channel-cells = <1>; 499 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 500 clock-names = "saradc", "apb_pclk"; 501 resets = <&cru SRST_P_SARADC>; 502 reset-names = "saradc-apb"; 503 status = "disabled"; 504 }; 505 506 tsadc: tsadc@ff3c8000 { 507 compatible = "rockchip,rv1106-tsadc"; 508 reg = <0xff3c8000 0x1000>; 509 rockchip,grf = <&grf>; 510 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>; 512 clock-names = "tsadc", "apb_pclk", "tsen"; 513 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; 514 assigned-clock-rates = <1000000>, <12000000>; 515 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; 516 reset-names = "tsadc", "tsadc-apb"; 517 #thermal-sensor-cells = <1>; 518 rockchip,hw-tshut-temp = <120000>; 519 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 520 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 521 status = "disabled"; 522 }; 523 524 otp: otp@ff3d0000 { 525 compatible = "rockchip,rv1106-otp"; 526 reg = <0xff3d0000 0x4000>; 527 #address-cells = <1>; 528 #size-cells = <1>; 529 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, 530 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>, 531 <&cru CLK_OTPC_ARB>, <&cru CLK_PMC_OTP>; 532 clock-names = "usr", "sbpi", "apb", "phy", "arb", "pmc"; 533 resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>, 534 <&cru SRST_P_OTPC_NS>, <&cru SRST_P_OTP_MASK>, 535 <&cru SRST_OTPC_ARB>, <&cru SRST_PMC_OTP>; 536 reset-names = "usr", "sbpi", "apb", "phy", "arb", "pmc"; 537 538 /* Data cells */ 539 cpu_code: cpu-code@2 { 540 reg = <0x02 0x2>; 541 }; 542 otp_cpu_version: cpu-version@8 { 543 reg = <0x08 0x1>; 544 bits = <3 3>; 545 }; 546 otp_id: id@a { 547 reg = <0x0a 0x10>; 548 }; 549 cpu_leakage: cpu-leakage@1a { 550 reg = <0x1a 0x1>; 551 }; 552 log_leakage: log-leakage@1b { 553 reg = <0x1b 0x1>; 554 }; 555 }; 556 557 u2phy: usb2-phy@ff3e0000 { 558 compatible = "rockchip,rv1106-usb2phy"; 559 reg = <0xff3e0000 0x8000>; 560 rockchip,usbgrf = <&grf>; 561 clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>; 562 clock-names = "phyclk", "pclk"; 563 resets = <&cru SRST_USBPHY_POR>, <&cru SRST_P_USBPHY>; 564 reset-names = "u2phy", "u2phy-apb"; 565 #clock-cells = <0>; 566 status = "disabled"; 567 568 u2phy_otg: otg-port { 569 #phy-cells = <0>; 570 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "otg-bvalid", "otg-id", 575 "linestate", "disconnect"; 576 status = "disabled"; 577 }; 578 }; 579 580 csi2_dphy_hw: csi2-dphy-hw@ff3e8000 { 581 compatible = "rockchip,rv1106-csi2-dphy-hw"; 582 reg = <0xff3e8000 0x8000>; 583 clocks = <&cru PCLK_MIPICSIPHY>; 584 clock-names = "pclk"; 585 resets = <&cru SRST_P_MIPICSIPHY>; 586 reset-names = "srst_p_csiphy"; 587 rockchip,grf = <&grf>; 588 status = "disabled"; 589 }; 590 591 dmac: dma-controller@ff420000 { 592 compatible = "arm,pl330", "arm,primecell"; 593 reg = <0xff420000 0x4000>; 594 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 603 #dma-cells = <1>; 604 clocks = <&cru ACLK_DMAC>; 605 clock-names = "apb_pclk"; 606 arm,pl330-periph-burst; 607 }; 608 609 crypto: crypto@ff440000 { 610 compatible = "rockchip,crypto-v3"; 611 reg = <0xff440000 0x2000>; 612 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 614 <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 615 clock-names = "aclk", "hclk", "sclk", "pka"; 616 assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 617 assigned-clock-rates = <300000000>, <300000000>; 618 resets = <&cru SRST_CORE_CRYPTO>; 619 reset-names = "crypto-rst"; 620 status = "disabled"; 621 }; 622 623 rng: rng@ff448000 { 624 compatible = "rockchip,trngv1"; 625 reg = <0xff448000 0x200>; 626 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&cru HCLK_TRNG_NS>; 628 clock-names = "hclk_trng"; 629 resets = <&cru SRST_H_TRNG_NS>; 630 reset-names = "reset"; 631 status = "disabled"; 632 }; 633 634 i2c2: i2c@ff450000 { 635 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 636 reg = <0xff450000 0x1000>; 637 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 641 clock-names = "i2c", "pclk"; 642 pinctrl-names = "default"; 643 pinctrl-0 = <&i2c2m0_xfer>; 644 status = "disabled"; 645 }; 646 647 i2c3: i2c@ff460000 { 648 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 649 reg = <0xff460000 0x1000>; 650 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 654 clock-names = "i2c", "pclk"; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&i2c3m0_xfer>; 657 status = "disabled"; 658 }; 659 660 i2c4: i2c@ff470000 { 661 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 662 reg = <0xff470000 0x1000>; 663 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 667 clock-names = "i2c", "pclk"; 668 pinctrl-names = "default"; 669 pinctrl-0 = <&i2c4m0_xfer>; 670 status = "disabled"; 671 }; 672 673 pwm8: pwm@ff490000 { 674 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 675 reg = <0xff490000 0x10>; 676 #pwm-cells = <3>; 677 pinctrl-names = "active"; 678 pinctrl-0 = <&pwm8m0_pins>; 679 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 680 clock-names = "pwm", "pclk"; 681 status = "disabled"; 682 }; 683 684 pwm9: pwm@ff490010 { 685 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 686 reg = <0xff490010 0x10>; 687 #pwm-cells = <3>; 688 pinctrl-names = "active"; 689 pinctrl-0 = <&pwm9m0_pins>; 690 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 691 clock-names = "pwm", "pclk"; 692 status = "disabled"; 693 }; 694 695 pwm10: pwm@ff490020 { 696 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 697 reg = <0xff490020 0x10>; 698 #pwm-cells = <3>; 699 pinctrl-names = "active"; 700 pinctrl-0 = <&pwm10m0_pins>; 701 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 702 clock-names = "pwm", "pclk"; 703 status = "disabled"; 704 }; 705 706 pwm11: pwm@ff490030 { 707 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 708 reg = <0xff490030 0x10>; 709 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 711 #pwm-cells = <3>; 712 pinctrl-names = "active"; 713 pinctrl-0 = <&pwm11m0_pins>; 714 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 715 clock-names = "pwm", "pclk"; 716 status = "disabled"; 717 }; 718 719 uart0: serial@ff4a0000 { 720 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 721 reg = <0xff4a0000 0x100>; 722 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 723 reg-shift = <2>; 724 reg-io-width = <4>; 725 dmas = <&dmac 7>, <&dmac 6>; 726 clock-frequency = <24000000>; 727 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 728 clock-names = "baudclk", "apb_pclk"; 729 pinctrl-names = "default"; 730 pinctrl-0 = <&uart0m0_xfer>; 731 status = "disabled"; 732 }; 733 734 uart1: serial@ff4b0000 { 735 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 736 reg = <0xff4b0000 0x100>; 737 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 738 reg-shift = <2>; 739 reg-io-width = <4>; 740 dmas = <&dmac 9>, <&dmac 8>; 741 clock-frequency = <24000000>; 742 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 743 clock-names = "baudclk", "apb_pclk"; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; 746 status = "disabled"; 747 }; 748 749 uart2: serial@ff4c0000 { 750 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 751 reg = <0xff4c0000 0x100>; 752 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 753 reg-shift = <2>; 754 reg-io-width = <4>; 755 dmas = <&dmac 11>, <&dmac 10>; 756 clock-frequency = <24000000>; 757 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 758 clock-names = "baudclk", "apb_pclk"; 759 pinctrl-names = "default"; 760 pinctrl-0 = <&uart2m1_xfer>; 761 status = "disabled"; 762 }; 763 764 uart3: serial@ff4d0000 { 765 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 766 reg = <0xff4d0000 0x100>; 767 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 768 reg-shift = <2>; 769 reg-io-width = <4>; 770 dmas = <&dmac 13>, <&dmac 12>; 771 clock-frequency = <24000000>; 772 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 773 clock-names = "baudclk", "apb_pclk"; 774 pinctrl-names = "default"; 775 pinctrl-0 = <&uart3m0_xfer>; 776 status = "disabled"; 777 }; 778 779 uart4: serial@ff4e0000 { 780 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 781 reg = <0xff4e0000 0x100>; 782 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 783 reg-shift = <2>; 784 reg-io-width = <4>; 785 dmas = <&dmac 15>, <&dmac 14>; 786 clock-frequency = <24000000>; 787 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 788 clock-names = "baudclk", "apb_pclk"; 789 pinctrl-names = "default"; 790 pinctrl-0 = <&uart4m0_xfer>; 791 status = "disabled"; 792 }; 793 794 uart5: serial@ff4f0000 { 795 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 796 reg = <0xff4f0000 0x100>; 797 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 798 reg-shift = <2>; 799 reg-io-width = <4>; 800 dmas = <&dmac 17>, <&dmac 16>; 801 clock-frequency = <24000000>; 802 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 803 clock-names = "baudclk", "apb_pclk"; 804 pinctrl-names = "default"; 805 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>; 806 status = "disabled"; 807 }; 808 809 spi0: spi@ff500000 { 810 compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi"; 811 reg = <0xff500000 0x1000>; 812 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 816 clock-names = "spiclk", "apb_pclk"; 817 dmas = <&dmac 1>, <&dmac 0>; 818 dma-names = "tx", "rx"; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 821 status = "disabled"; 822 }; 823 824 spi1: spi@ff510000 { 825 compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi"; 826 reg = <0xff510000 0x1000>; 827 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 831 clock-names = "spiclk", "apb_pclk"; 832 dmas = <&dmac 3>, <&dmac 2>; 833 dma-names = "tx", "rx"; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 836 status = "disabled"; 837 }; 838 839 hw_decompress: decompress@ff520000 { 840 compatible = "rockchip,hw-decompress"; 841 reg = <0xff520000 0x1000>; 842 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 844 clock-names = "aclk", "dclk", "pclk"; 845 resets = <&cru SRST_D_DECOM>; 846 reset-names = "dresetn"; 847 status = "disabled"; 848 }; 849 850 ioc: syscon@ff538000 { 851 compatible = "rockchip,rv1106-ioc", "syscon"; 852 reg = <0xff538000 0x40000>; 853 }; 854 855 wdt: watchdog@ff5a0000 { 856 compatible = "rockchip,rv1106-wdt", "snps,dw-wdt"; 857 reg = <0xff5a0000 0x100>; 858 clocks = <&cru PCLK_WDT_NS>; 859 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 860 status = "disabled"; 861 }; 862 863 mailbox: mailbox@ff5c0000 { 864 compatible = "rockchip,rv1106-mailbox", 865 "rockchip,rk3368-mailbox"; 866 reg = <0xff5c0000 0x200>; 867 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cru PCLK_MAILBOX>; 869 clock-names = "pclk_mailbox"; 870 #mbox-cells = <1>; 871 status = "disabled"; 872 }; 873 874 npu: npu@ff660000 { 875 compatible = "rockchip,rv1106-rknpu"; 876 reg = <0xff660000 0x10000>; 877 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; 879 clock-names = "aclk", "hclk"; 880 resets = <&cru SRST_A_RKNN>, <&cru SRST_H_RKNN>; 881 reset-names = "srst_a", "srst_h"; 882 status = "disabled"; 883 }; 884 885 rga2: rga@ff980000 { 886 compatible = "rockchip,rga2_core0"; 887 reg = <0xff980000 0x1000>; 888 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>; 890 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; 891 status = "disabled"; 892 }; 893 894 vop: vop@ff990000 { 895 compatible = "rockchip,rv1106-vop"; 896 reg = <0xff990000 0x200>; 897 reg-names = "regs"; 898 rockchip,grf = <&grf>; 899 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 901 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 902 status = "disabled"; 903 904 vop_out: port { 905 #address-cells = <1>; 906 #size-cells = <0>; 907 908 vop_out_rgb: endpoint@0 { 909 reg = <0>; 910 remote-endpoint = <&rgb_in_vop>; 911 }; 912 }; 913 }; 914 915 sdio: mmc@ff9a0000 { 916 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 917 reg = <0xff9a0000 0x4000>; 918 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 920 <&grf_cru SCLK_SDIO_DRV>, <&grf_cru SCLK_SDIO_SAMPLE>; 921 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 922 fifo-depth = <0x100>; 923 max-frequency = <200000000>; 924 status = "disabled"; 925 }; 926 927 rkisp: rkisp@ffa00000 { 928 compatible = "rockchip,rv1106-rkisp"; 929 reg = <0xffa00000 0x7f00>; 930 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 933 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 934 clocks = <&cru ACLK_ISP3P2>, <&cru HCLK_ISP3P2>, 935 <&cru CLK_CORE_ISP3P2>, <&cru ISP0CLK_VICAP>; 936 clock-names = "aclk_isp", "hclk_isp", 937 "clk_isp_core", "clk_isp_core_vicap"; 938 status = "disabled"; 939 }; 940 941 rkcif: rkcif@ffa10000 { 942 compatible = "rockchip,rv1106-cif"; 943 reg = <0xffa10000 0x10000>; 944 reg-names = "cif_regs"; 945 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 946 interrupt-names = "cif-intr"; 947 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, 948 <&cru DCLK_VICAP>, <&cru PCLK_VICAP>, 949 <&cru I0CLK_VICAP>, <&cru I1CLK_VICAP>, 950 <&cru RX0PCLK_VICAP>, <&cru RX1PCLK_VICAP>, 951 <&cru ISP0CLK_VICAP>, <&cru SCLK_VICAP_M0>, 952 <&cru SCLK_VICAP_M1>, <&cru PCLK_VICAP_VEPU>; 953 clock-names = "aclk_cif","hclk_cif", 954 "dclk_cif", "pclk_cif", 955 "i0clk_cif", "i1clk_cif", 956 "rx0clk_cif", "rx1clk_cif", 957 "isp0clk_cif", "sclk_m0_cif", 958 "sclk_m1_cif", "pclk_vepu_cif"; 959 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, 960 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, 961 <&cru SRST_VICAP_I0>, <&cru SRST_VICAP_I1>, 962 <&cru SRST_VICAP_RX0>, <&cru SRST_VICAP_RX1>, 963 <&cru SRST_VICAP_ISP0>, <&cru SRST_P_VICAP_VEPU>; 964 reset-names = "rst_cif_a","rst_cif_h", 965 "rst_cif_d", "rst_cif_p", 966 "rst_cif_i0", "rst_cif_i1", 967 "rst_cif_rx0", "rst_cif_rx1", 968 "rst_cif_isp0", "rst_cif_pclk_vepu"; 969 rockchip,grf = <&grf>; 970 status = "disabled"; 971 }; 972 973 mipi0_csi2: mipi-csi2@ffa20000 { 974 compatible = "rockchip,rk3588-mipi-csi2"; 975 reg = <0xffa20000 0x10000>; 976 reg-names = "csihost_regs"; 977 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 979 interrupt-names = "csi-intr1", "csi-intr2"; 980 clocks = <&cru PCLK_CSIHOST0>, <&cru CLK_RXBYTECLKHS_0>; 981 clock-names = "pclk_csi2host", "clk_rxbyte_hs"; 982 resets = <&cru SRST_P_CSIHOST0>; 983 reset-names = "srst_csihost_p"; 984 status = "disabled"; 985 }; 986 987 mipi1_csi2: mipi-csi2@ffa30000 { 988 compatible = "rockchip,rk3588-mipi-csi2"; 989 reg = <0xffa30000 0x10000>; 990 reg-names = "csihost_regs"; 991 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 993 interrupt-names = "csi-intr1", "csi-intr2"; 994 clocks = <&cru PCLK_CSIHOST1>, <&cru CLK_RXBYTECLKHS_1>; 995 clock-names = "pclk_csi2host", "clk_rxbyte_hs"; 996 resets = <&cru SRST_P_CSIHOST1>; 997 reset-names = "srst_csihost_p"; 998 status = "disabled"; 999 }; 1000 1001 rkvenc: rkvenc@ffa50000 { 1002 compatible = "rockchip,rkv-encoder-rv1106"; 1003 reg = <0xffa50000 0x6000>; 1004 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1005 interrupt-names = "irq_rkvenc"; 1006 clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>, <&cru CLK_CORE_VEPU>; 1007 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1008 rockchip,normal-rates = <300000000>, <0>, <400000000>; 1009 assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>; 1010 assigned-clock-rates = <300000000>, <400000000>; 1011 resets = <&cru SRST_A_VEPU>, <&cru SRST_H_VEPU>, <&cru SRST_CORE_VEPU>; 1012 reset-names = "video_a", "video_h", "video_core"; 1013 rockchip,srv = <&mpp_srv>; 1014 rockchip,taskqueue-node = <0>; 1015 dvbm = <&rkdvbm>; 1016 status = "disabled"; 1017 }; 1018 1019 rkdvbm: rkdvbm@ffa70000 { 1020 compatible = "rockchip,rk-dvbm"; 1021 reg = <0xffa70000 0x90>; 1022 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1023 interrupt-names = "irq_rkdvbm"; 1024 clocks = <&cru CLK_CORE_VEPU_DVBM>; 1025 clock-names = "clk_core"; 1026 assigned-clocks = <&cru CLK_CORE_VEPU_DVBM>; 1027 assigned-clock-rates = <200000000>; 1028 resets = <&cru SRST_CORE_VEPU_DVBM>; 1029 reset-names = "dvbm_rst"; 1030 status = "disabled"; 1031 }; 1032 1033 gmac: ethernet@ffa80000 { 1034 compatible = "rockchip,rv1106-gmac", "snps,dwmac-4.20a"; 1035 reg = <0xffa80000 0x10000>; 1036 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1038 interrupt-names = "macirq", "eth_wake_irq"; 1039 rockchip,grf = <&grf>; 1040 clocks = <&cru CLK_GMAC0_TX_50M_O>, <&cru CLK_GMAC0_REF_50M>, 1041 <&cru ACLK_MAC>, <&cru PCLK_MAC>; 1042 clock-names = "stmmaceth", "clk_mac_ref", 1043 "aclk_mac", "pclk_mac"; 1044 resets = <&cru SRST_A_MAC>; 1045 reset-names = "stmmaceth"; 1046 1047 snps,mixed-burst; 1048 snps,tso; 1049 1050 snps,axi-config = <&stmmac_axi_setup>; 1051 snps,mtl-rx-config = <&mtl_rx_setup>; 1052 snps,mtl-tx-config = <&mtl_tx_setup>; 1053 1054 phy-mode = "rmii"; 1055 clock_in_out = "input"; 1056 phy-handle = <&rmii_phy>; 1057 status = "disabled"; 1058 1059 mdio: mdio { 1060 compatible = "snps,dwmac-mdio"; 1061 #address-cells = <0x1>; 1062 #size-cells = <0x0>; 1063 rmii_phy: ethernet-phy@2 { 1064 compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22"; 1065 reg = <2>; 1066 clocks = <&cru CLK_MACPHY>; 1067 resets = <&cru SRST_MACPHY>; 1068 phy-is-integrated; 1069 }; 1070 }; 1071 1072 stmmac_axi_setup: stmmac-axi-config { 1073 snps,wr_osr_lmt = <4>; 1074 snps,rd_osr_lmt = <8>; 1075 snps,blen = <0 0 0 0 16 8 4>; 1076 }; 1077 1078 mtl_rx_setup: rx-queues-config { 1079 snps,rx-queues-to-use = <1>; 1080 queue0 {}; 1081 }; 1082 1083 mtl_tx_setup: tx-queues-config { 1084 snps,tx-queues-to-use = <1>; 1085 queue0 {}; 1086 }; 1087 }; 1088 1089 emmc: mmc@ffa90000 { 1090 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 1091 reg = <0xffa90000 0x4000>; 1092 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&cru HCLK_EMMC>, <&cru CCLK_SRC_EMMC>, 1094 <&grf_cru SCLK_EMMC_DRV>, <&grf_cru SCLK_EMMC_SAMPLE>; 1095 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1096 fifo-depth = <0x100>; 1097 max-frequency = <200000000>; 1098 rockchip,use-v2-tuning; 1099 status = "disabled"; 1100 }; 1101 1102 sdmmc: mmc@ffaa0000 { 1103 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 1104 reg = <0xffaa0000 0x4000>; 1105 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1106 clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>, 1107 <&grf_cru SCLK_SDMMC_DRV>, <&grf_cru SCLK_SDMMC_SAMPLE>; 1108 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1109 cd-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 1110 fifo-depth = <0x100>; 1111 max-frequency = <200000000>; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; 1114 status = "disabled"; 1115 }; 1116 1117 sfc: spi@ffac0000 { 1118 compatible = "rockchip,sfc"; 1119 reg = <0xffac0000 0x4000>; 1120 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1122 clock-names = "clk_sfc", "hclk_sfc"; 1123 assigned-clocks = <&cru SCLK_SFC>; 1124 assigned-clock-rates = <75000000>; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 status = "disabled"; 1128 }; 1129 1130 rve: rve@ffad0000 { 1131 compatible = "rockchip,rve"; 1132 reg = <0xffad0000 0x1000>; 1133 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&cru ACLK_IVE>, <&cru HCLK_IVE>; 1135 clock-names = "aclk_rve", "hclk_rve"; 1136 status = "disabled"; 1137 }; 1138 1139 i2s0_8ch: i2s@ffae0000 { 1140 compatible = "rockchip,rv1106-i2s-tdm"; 1141 reg = <0xffae0000 0x1000>; 1142 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0>; 1144 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1145 dmas = <&dmac 22>, <&dmac 21>; 1146 dma-names = "tx", "rx"; 1147 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1148 reset-names = "tx-m", "rx-m"; 1149 rockchip,clk-trcm = <1>; 1150 #sound-dai-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 1154 usbdrd: usbdrd { 1155 compatible = "rockchip,rv1106-dwc3", "rockchip,rk3399-dwc3"; 1156 clocks = <&cru CLK_REF_USBOTG>, <&cru CLK_UTMI_USBOTG>, 1157 <&cru ACLK_USBOTG>; 1158 clock-names = "ref", "utmi", "bus"; 1159 #address-cells = <1>; 1160 #size-cells = <1>; 1161 ranges; 1162 status = "disabled"; 1163 1164 usbdrd_dwc3: usb@ffb00000 { 1165 compatible = "snps,dwc3"; 1166 reg = <0xffb00000 0x100000>; 1167 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1168 resets = <&cru SRST_A_USBOTG>; 1169 reset-names = "usb3-otg"; 1170 dr_mode = "otg"; 1171 maximum-speed = "high-speed"; 1172 phys = <&u2phy_otg>; 1173 phy-names = "usb2-phy"; 1174 phy_type = "utmi_wide"; 1175 snps,dis_enblslpm_quirk; 1176 snps,dis-u2-freeclk-exists-quirk; 1177 snps,dis_u2_susphy_quirk; 1178 snps,dis-del-phy-power-chg-quirk; 1179 snps,dis-tx-ipgap-linecheck-quirk; 1180 status = "disabled"; 1181 }; 1182 }; 1183 1184 pinctrl: pinctrl { 1185 compatible = "rockchip,rv1106-pinctrl"; 1186 rockchip,grf = <&ioc>; 1187 rockchip,pmu = <&pmuioc>; 1188 #address-cells = <1>; 1189 #size-cells = <1>; 1190 ranges; 1191 1192 gpio0: gpio@ff380000 { 1193 compatible = "rockchip,gpio-bank"; 1194 reg = <0xff380000 0x100>; 1195 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1196 clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>; 1197 1198 gpio-controller; 1199 #gpio-cells = <2>; 1200 gpio-ranges = <&pinctrl 0 0 32>; 1201 interrupt-controller; 1202 #interrupt-cells = <2>; 1203 }; 1204 1205 gpio1: gpio@ff530000 { 1206 compatible = "rockchip,gpio-bank"; 1207 reg = <0xff530000 0x100>; 1208 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1209 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1210 1211 gpio-controller; 1212 #gpio-cells = <2>; 1213 gpio-ranges = <&pinctrl 0 32 32>; 1214 interrupt-controller; 1215 #interrupt-cells = <2>; 1216 }; 1217 1218 gpio2: gpio@ff540000 { 1219 compatible = "rockchip,gpio-bank"; 1220 reg = <0xff540000 0x100>; 1221 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1223 1224 gpio-controller; 1225 #gpio-cells = <2>; 1226 gpio-ranges = <&pinctrl 0 64 32>; 1227 interrupt-controller; 1228 #interrupt-cells = <2>; 1229 }; 1230 1231 gpio3: gpio@ff550000 { 1232 compatible = "rockchip,gpio-bank"; 1233 reg = <0xff550000 0x100>; 1234 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1236 1237 gpio-controller; 1238 #gpio-cells = <2>; 1239 gpio-ranges = <&pinctrl 0 96 32>; 1240 interrupt-controller; 1241 #interrupt-cells = <2>; 1242 }; 1243 1244 gpio4: gpio@ff560000 { 1245 compatible = "rockchip,gpio-bank"; 1246 reg = <0xff560000 0x100>; 1247 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1248 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1249 1250 gpio-controller; 1251 #gpio-cells = <2>; 1252 gpio-ranges = <&pinctrl 0 128 32>; 1253 interrupt-controller; 1254 #interrupt-cells = <2>; 1255 }; 1256 }; 1257}; 1258 1259#include "rv1106-pinctrl.dtsi" 1260