1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5#include <dt-bindings/clock/rv1106-cru.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11#include <dt-bindings/soc/rockchip-system-status.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1106"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 csi2dphy0 = &csi2_dphy0; 24 csi2dphy1 = &csi2_dphy1; 25 csi2dphy2 = &csi2_dphy2; 26 ethernet0 = &gmac; 27 gpio0 = &gpio0; 28 gpio1 = &gpio1; 29 gpio2 = &gpio2; 30 gpio3 = &gpio3; 31 gpio4 = &gpio4; 32 i2c0 = &i2c0; 33 i2c1 = &i2c1; 34 i2c2 = &i2c2; 35 i2c3 = &i2c3; 36 i2c4 = &i2c4; 37 mmc0 = &emmc; 38 mmc1 = &sdmmc; 39 mmc2 = &sdio; 40 rkcif_mipi_lvds0 = &rkcif_mipi_lvds; 41 rkcif_mipi_lvds1 = &rkcif_mipi_lvds1; 42 serial0 = &uart0; 43 serial1 = &uart1; 44 serial2 = &uart2; 45 serial3 = &uart3; 46 serial4 = &uart4; 47 serial5 = &uart5; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &sfc; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 cpu0: cpu@f00 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a7"; 60 reg = <0xf00>; 61 }; 62 }; 63 64 arm-pmu { 65 compatible = "arm,cortex-a7-pmu"; 66 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 67 interrupt-affinity = <&cpu0>; 68 }; 69 70 cpuinfo { 71 compatible = "rockchip,cpuinfo"; 72 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 73 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 74 }; 75 76 /* dphy0 full mode */ 77 csi2_dphy0: csi2-dphy0 { 78 compatible = "rockchip,rv1106-csi2-dphy"; 79 rockchip,hw = <&csi2_dphy_hw>; 80 status = "disabled"; 81 }; 82 83 /* dphy1 split mode 01 */ 84 csi2_dphy1: csi2-dphy1 { 85 compatible = "rockchip,rv1106-csi2-dphy"; 86 rockchip,hw = <&csi2_dphy_hw>; 87 status = "disabled"; 88 }; 89 90 /* dphy2 split mode 23 */ 91 csi2_dphy2: csi2-dphy2 { 92 compatible = "rockchip,rv1106-csi2-dphy"; 93 rockchip,hw = <&csi2_dphy_hw>; 94 status = "disabled"; 95 }; 96 97 display_subsystem: display-subsystem { 98 compatible = "rockchip,display-subsystem"; 99 ports = <&vop_out>; 100 status = "disabled"; 101 }; 102 103 fiq_debugger: fiq-debugger { 104 compatible = "rockchip,fiq-debugger"; 105 rockchip,serial-id = <2>; 106 rockchip,wake-irq = <0>; 107 rockchip,irq-mode-enable = <0>; 108 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 109 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 110 status = "disabled"; 111 }; 112 113 mpp_srv: mpp-srv { 114 compatible = "rockchip,mpp-service"; 115 rockchip,taskqueue-count = <2>; 116 status = "disabled"; 117 }; 118 119 mpp_vcodec: mpp-vcodec { 120 compatible = "rockchip,vcodec"; 121 status = "disabled"; 122 }; 123 124 reserved-memory { 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges; 128 129 linux,cma { 130 compatible = "shared-dma-pool"; 131 inactive; 132 reusable; 133 size = <0x800000>; 134 linux,cma-default; 135 }; 136 }; 137 138 rkcif_dvp: rkcif-dvp { 139 compatible = "rockchip,rkcif-dvp"; 140 rockchip,hw = <&rkcif>; 141 status = "disabled"; 142 }; 143 144 rkcif_dvp_sditf: rkcif-dvp-sditf { 145 compatible = "rockchip,rkcif-sditf"; 146 rockchip,cif = <&rkcif_dvp>; 147 status = "disabled"; 148 }; 149 150 rkcif_mipi_lvds: rkcif-mipi-lvds { 151 compatible = "rockchip,rkcif-mipi-lvds"; 152 rockchip,hw = <&rkcif>; 153 status = "disabled"; 154 }; 155 156 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { 157 compatible = "rockchip,rkcif-sditf"; 158 rockchip,cif = <&rkcif_mipi_lvds>; 159 status = "disabled"; 160 }; 161 162 rkcif_mipi_lvds1: rkcif-mipi-lvds1 { 163 compatible = "rockchip,rkcif-mipi-lvds"; 164 rockchip,hw = <&rkcif>; 165 status = "disabled"; 166 }; 167 168 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { 169 compatible = "rockchip,rkcif-sditf"; 170 rockchip,cif = <&rkcif_mipi_lvds1>; 171 status = "disabled"; 172 }; 173 174 rkisp_vir0: rkisp-vir0 { 175 compatible = "rockchip,rkisp-vir"; 176 rockchip,hw = <&rkisp>; 177 dvbm = <&rkdvbm>; 178 status = "disabled"; 179 }; 180 181 rkisp_vir1: rkisp-vir1 { 182 compatible = "rockchip,rkisp-vir"; 183 rockchip,hw = <&rkisp>; 184 status = "disabled"; 185 }; 186 187 rkisp_vir2: rkisp-vir2 { 188 compatible = "rockchip,rkisp-vir"; 189 rockchip,hw = <&rkisp>; 190 status = "disabled"; 191 }; 192 193 rkisp_vir3: rkisp-vir3 { 194 compatible = "rockchip,rkisp-vir"; 195 rockchip,hw = <&rkisp>; 196 status = "disabled"; 197 }; 198 199 rockchip_system_monitor: rockchip-system-monitor { 200 compatible = "rockchip,system-monitor"; 201 202 rockchip,thermal-zone = "soc-thermal"; 203 }; 204 205 thermal_zones: thermal-zones { 206 soc_thermal: soc-thermal { 207 polling-delay-passive = <20>; /* milliseconds */ 208 polling-delay = <1000>; /* milliseconds */ 209 sustainable-power = <2100>; /* milliwatts */ 210 211 thermal-sensors = <&tsadc 0>; 212 trips { 213 threshold: trip-point-0 { 214 temperature = <75000>; 215 hysteresis = <2000>; 216 type = "passive"; 217 }; 218 target: trip-point-1 { 219 temperature = <85000>; 220 hysteresis = <2000>; 221 type = "passive"; 222 }; 223 soc_crit: soc-crit { 224 /* millicelsius */ 225 temperature = <115000>; 226 /* millicelsius */ 227 hysteresis = <2000>; 228 type = "critical"; 229 }; 230 }; 231 }; 232 }; 233 234 timer { 235 compatible = "arm,armv7-timer"; 236 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 237 clock-frequency = <24000000>; 238 }; 239 240 xin24m: oscillator { 241 compatible = "fixed-clock"; 242 clock-frequency = <24000000>; 243 clock-output-names = "xin24m"; 244 #clock-cells = <0>; 245 }; 246 247 grf: syscon@ff000000 { 248 compatible = "rockchip,rv1106-grf", "syscon", "simple-mfd"; 249 reg = <0xff000000 0x68000>; 250 251 grf_cru: grf-clock-controller { 252 compatible = "rockchip,rv1106-grf-cru"; 253 #clock-cells = <1>; 254 }; 255 256 reboot_mode: reboot-mode { 257 compatible = "syscon-reboot-mode"; 258 offset = <0x20200>; 259 mode-bootloader = <BOOT_BL_DOWNLOAD>; 260 mode-charge = <BOOT_CHARGING>; 261 mode-fastboot = <BOOT_FASTBOOT>; 262 mode-loader = <BOOT_BL_DOWNLOAD>; 263 mode-normal = <BOOT_NORMAL>; 264 mode-recovery = <BOOT_RECOVERY>; 265 mode-ums = <BOOT_UMS>; 266 mode-panic = <BOOT_PANIC>; 267 mode-watchdog = <BOOT_WATCHDOG>; 268 }; 269 270 rgb: rgb { 271 compatible = "rockchip,rv1106-rgb"; 272 status = "disabled"; 273 274 ports { 275 #address-cells = <1>; 276 #size-cells = <0>; 277 278 port@0 { 279 reg = <0>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 283 rgb_in_vop: endpoint@0 { 284 reg = <0>; 285 remote-endpoint = <&vop_out_rgb>; 286 }; 287 }; 288 }; 289 }; 290 }; 291 292 rtc: rtc@ff1c0000 { 293 compatible = "rockchip,rtc-1.0"; 294 reg = <0xff1c0000 0x1000>; 295 rockchip,grf = <&grf>; 296 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cru PCLK_VI_RTC_PHY>, <&cru PCLK_VI_RTC_TEST>; 298 clock-names = "pclk_phy", "pclk_test"; 299 assigned-clocks = <&cru PCLK_VI_RTC_PHY>; 300 assigned-clock-rates = <24000000>; 301 status = "disabled"; 302 }; 303 304 gic: interrupt-controller@ff1f0000 { 305 compatible = "arm,gic-400"; 306 interrupt-controller; 307 #interrupt-cells = <3>; 308 #address-cells = <0>; 309 310 reg = <0xff1f1000 0x1000>, 311 <0xff1f2000 0x2000>, 312 <0xff1f4000 0x2000>, 313 <0xff1f6000 0x2000>; 314 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 315 }; 316 317 arm-debug@ff200000 { 318 compatible = "rockchip,debug"; 319 reg = <0xff200000 0x1000>; 320 }; 321 322 i2c0: i2c@ff310000 { 323 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 324 reg = <0xff310000 0x1000>; 325 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 329 clock-names = "i2c", "pclk"; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&i2c0m0_xfer>; 332 status = "disabled"; 333 }; 334 335 i2c1: i2c@ff320000 { 336 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 337 reg = <0xff320000 0x1000>; 338 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 342 clock-names = "i2c", "pclk"; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&i2c1m0_xfer>; 345 status = "disabled"; 346 }; 347 348 dsm: codec-digital@ff340000 { 349 compatible = "rockchip,rv1106-codec-digital", "rockchip,codec-digital-v1"; 350 reg = <0xff340000 0x1000>; 351 clocks = <&cru MCLK_DSM>, <&cru PCLK_DSM>; 352 clock-names = "dac", "pclk"; 353 resets = <&cru SRST_M_DSM>; 354 reset-names = "reset" ; 355 rockchip,grf = <&grf>; 356 rockchip,pwm-output-mode; 357 #sound-dai-cells = <0>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&dsmaudio_pins>; 360 status = "disabled"; 361 }; 362 363 pwm0: pwm@ff350000 { 364 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 365 reg = <0xff350000 0x10>; 366 #pwm-cells = <3>; 367 pinctrl-names = "active"; 368 pinctrl-0 = <&pwm0m0_pins>; 369 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; 370 clock-names = "pwm", "pclk"; 371 status = "disabled"; 372 }; 373 374 pwm1: pwm@ff350010 { 375 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 376 reg = <0xff350010 0x10>; 377 #pwm-cells = <3>; 378 pinctrl-names = "active"; 379 pinctrl-0 = <&pwm1m0_pins>; 380 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; 381 clock-names = "pwm", "pclk"; 382 status = "disabled"; 383 }; 384 385 pwm2: pwm@ff350020 { 386 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 387 reg = <0xff350020 0x10>; 388 #pwm-cells = <3>; 389 pinctrl-names = "active"; 390 pinctrl-0 = <&pwm2m0_pins>; 391 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; 392 clock-names = "pwm", "pclk"; 393 status = "disabled"; 394 }; 395 396 pwm3: pwm@ff350030 { 397 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 398 reg = <0xff350030 0x10>; 399 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 401 #pwm-cells = <3>; 402 pinctrl-names = "active"; 403 pinctrl-0 = <&pwm3m0_pins>; 404 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; 405 clock-names = "pwm", "pclk"; 406 status = "disabled"; 407 }; 408 409 pwm4: pwm@ff360000 { 410 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 411 reg = <0xff360000 0x10>; 412 #pwm-cells = <3>; 413 pinctrl-names = "active"; 414 pinctrl-0 = <&pwm4m0_pins>; 415 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 416 clock-names = "pwm", "pclk"; 417 status = "disabled"; 418 }; 419 420 pwm5: pwm@ff360010 { 421 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 422 reg = <0xff360010 0x10>; 423 #pwm-cells = <3>; 424 pinctrl-names = "active"; 425 pinctrl-0 = <&pwm5m0_pins>; 426 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 427 clock-names = "pwm", "pclk"; 428 status = "disabled"; 429 }; 430 431 pwm6: pwm@ff360020 { 432 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 433 reg = <0xff360020 0x10>; 434 #pwm-cells = <3>; 435 pinctrl-names = "active"; 436 pinctrl-0 = <&pwm6m0_pins>; 437 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 438 clock-names = "pwm", "pclk"; 439 status = "disabled"; 440 }; 441 442 pwm7: pwm@ff360030 { 443 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 444 reg = <0xff360030 0x10>; 445 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 447 #pwm-cells = <3>; 448 pinctrl-names = "active"; 449 pinctrl-0 = <&pwm7m0_pins>; 450 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 451 clock-names = "pwm", "pclk"; 452 status = "disabled"; 453 }; 454 455 pmu_mailbox: mailbox@ff378000 { 456 compatible = "rockchip,rv1106-mailbox", 457 "rockchip,rk3368-mailbox"; 458 reg = <0xff378000 0x200>; 459 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&cru PCLK_PMU_MAILBOX>; 461 clock-names = "pclk_mailbox"; 462 #mbox-cells = <1>; 463 status = "disabled"; 464 }; 465 466 pmuioc: syscon@ff388000 { 467 compatible = "rockchip,rv1106-pmuioc", "syscon"; 468 reg = <0xff388000 0x1000>; 469 }; 470 471 cru: clock-controller@ff3a0000 { 472 compatible = "rockchip,rv1106-cru"; 473 reg = <0xff3a0000 0x20000>; 474 rockchip,grf = <&grf>; 475 #clock-cells = <1>; 476 #reset-cells = <1>; 477 478 assigned-clocks = 479 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 480 <&cru ARMCLK>, 481 <&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>, 482 <&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>, 483 <&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>, 484 <&cru HCLK_PMU_ROOT>; 485 assigned-clock-rates = 486 <1188000000>, <1000000000>, 487 <816000000>, 488 <400000000>, <200000000>, 489 <100000000>, <300000000>, 490 <100000000>, <100000000>, 491 <200000000>; 492 }; 493 494 saradc: saradc@ff3c0000 { 495 compatible = "rockchip,rv1106-saradc"; 496 reg = <0xff3c0000 0x100>; 497 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 498 #io-channel-cells = <1>; 499 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 500 clock-names = "saradc", "apb_pclk"; 501 resets = <&cru SRST_P_SARADC>; 502 reset-names = "saradc-apb"; 503 status = "disabled"; 504 }; 505 506 tsadc: tsadc@ff3c8000 { 507 compatible = "rockchip,rv1106-tsadc"; 508 reg = <0xff3c8000 0x1000>; 509 rockchip,grf = <&grf>; 510 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>; 512 clock-names = "tsadc", "apb_pclk", "tsen"; 513 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; 514 assigned-clock-rates = <1000000>, <12000000>; 515 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; 516 reset-names = "tsadc", "tsadc-apb"; 517 #thermal-sensor-cells = <1>; 518 rockchip,hw-tshut-temp = <120000>; 519 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 520 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 521 status = "disabled"; 522 }; 523 524 otp: otp@ff3d0000 { 525 compatible = "rockchip,rv1106-otp"; 526 reg = <0xff3d0000 0x4000>; 527 #address-cells = <1>; 528 #size-cells = <1>; 529 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, 530 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>, 531 <&cru CLK_OTPC_ARB>, <&cru CLK_PMC_OTP>; 532 clock-names = "usr", "sbpi", "apb", "phy", "arb", "pmc"; 533 resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>, 534 <&cru SRST_P_OTPC_NS>, <&cru SRST_P_OTP_MASK>, 535 <&cru SRST_OTPC_ARB>, <&cru SRST_PMC_OTP>; 536 reset-names = "usr", "sbpi", "apb", "phy", "arb", "pmc"; 537 538 /* Data cells */ 539 cpu_code: cpu-code@2 { 540 reg = <0x02 0x2>; 541 }; 542 otp_cpu_version: cpu-version@8 { 543 reg = <0x08 0x1>; 544 bits = <3 3>; 545 }; 546 otp_id: id@a { 547 reg = <0x0a 0x10>; 548 }; 549 cpu_leakage: cpu-leakage@1a { 550 reg = <0x1a 0x1>; 551 }; 552 log_leakage: log-leakage@1b { 553 reg = <0x1b 0x1>; 554 }; 555 macphy_bgs: macphy-bgs@2d { 556 reg = <0x2d 0x1>; 557 }; 558 macphy_txlevel: macphy-txlevel@2e { 559 reg = <0x2e 0x2>; 560 }; 561 }; 562 563 u2phy: usb2-phy@ff3e0000 { 564 compatible = "rockchip,rv1106-usb2phy"; 565 reg = <0xff3e0000 0x8000>; 566 rockchip,usbgrf = <&grf>; 567 clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>; 568 clock-names = "phyclk", "pclk"; 569 resets = <&cru SRST_USBPHY_POR>, <&cru SRST_P_USBPHY>; 570 reset-names = "u2phy", "u2phy-apb"; 571 #clock-cells = <0>; 572 status = "disabled"; 573 574 u2phy_otg: otg-port { 575 #phy-cells = <0>; 576 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 580 interrupt-names = "otg-bvalid", "otg-id", 581 "linestate", "disconnect"; 582 status = "disabled"; 583 }; 584 }; 585 586 csi2_dphy_hw: csi2-dphy-hw@ff3e8000 { 587 compatible = "rockchip,rv1106-csi2-dphy-hw"; 588 reg = <0xff3e8000 0x8000>; 589 clocks = <&cru PCLK_MIPICSIPHY>; 590 clock-names = "pclk"; 591 resets = <&cru SRST_P_MIPICSIPHY>; 592 reset-names = "srst_p_csiphy"; 593 rockchip,grf = <&grf>; 594 status = "disabled"; 595 }; 596 597 dmac: dma-controller@ff420000 { 598 compatible = "arm,pl330", "arm,primecell"; 599 reg = <0xff420000 0x4000>; 600 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 609 #dma-cells = <1>; 610 clocks = <&cru ACLK_DMAC>; 611 clock-names = "apb_pclk"; 612 arm,pl330-periph-burst; 613 }; 614 615 crypto: crypto@ff440000 { 616 compatible = "rockchip,crypto-v3"; 617 reg = <0xff440000 0x2000>; 618 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 620 <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 621 clock-names = "aclk", "hclk", "sclk", "pka"; 622 assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 623 assigned-clock-rates = <300000000>, <300000000>; 624 resets = <&cru SRST_CORE_CRYPTO>; 625 reset-names = "crypto-rst"; 626 status = "disabled"; 627 }; 628 629 rng: rng@ff448000 { 630 compatible = "rockchip,trngv1"; 631 reg = <0xff448000 0x200>; 632 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&cru HCLK_TRNG_NS>; 634 clock-names = "hclk_trng"; 635 resets = <&cru SRST_H_TRNG_NS>; 636 reset-names = "reset"; 637 status = "disabled"; 638 }; 639 640 i2c2: i2c@ff450000 { 641 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 642 reg = <0xff450000 0x1000>; 643 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 644 #address-cells = <1>; 645 #size-cells = <0>; 646 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 647 clock-names = "i2c", "pclk"; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&i2c2m0_xfer>; 650 status = "disabled"; 651 }; 652 653 i2c3: i2c@ff460000 { 654 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 655 reg = <0xff460000 0x1000>; 656 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 660 clock-names = "i2c", "pclk"; 661 pinctrl-names = "default"; 662 pinctrl-0 = <&i2c3m0_xfer>; 663 status = "disabled"; 664 }; 665 666 i2c4: i2c@ff470000 { 667 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 668 reg = <0xff470000 0x1000>; 669 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 673 clock-names = "i2c", "pclk"; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&i2c4m0_xfer>; 676 status = "disabled"; 677 }; 678 679 pwm8: pwm@ff490000 { 680 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 681 reg = <0xff490000 0x10>; 682 #pwm-cells = <3>; 683 pinctrl-names = "active"; 684 pinctrl-0 = <&pwm8m0_pins>; 685 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 686 clock-names = "pwm", "pclk"; 687 status = "disabled"; 688 }; 689 690 pwm9: pwm@ff490010 { 691 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 692 reg = <0xff490010 0x10>; 693 #pwm-cells = <3>; 694 pinctrl-names = "active"; 695 pinctrl-0 = <&pwm9m0_pins>; 696 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 697 clock-names = "pwm", "pclk"; 698 status = "disabled"; 699 }; 700 701 pwm10: pwm@ff490020 { 702 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 703 reg = <0xff490020 0x10>; 704 #pwm-cells = <3>; 705 pinctrl-names = "active"; 706 pinctrl-0 = <&pwm10m0_pins>; 707 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 708 clock-names = "pwm", "pclk"; 709 status = "disabled"; 710 }; 711 712 pwm11: pwm@ff490030 { 713 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 714 reg = <0xff490030 0x10>; 715 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 717 #pwm-cells = <3>; 718 pinctrl-names = "active"; 719 pinctrl-0 = <&pwm11m0_pins>; 720 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 721 clock-names = "pwm", "pclk"; 722 status = "disabled"; 723 }; 724 725 uart0: serial@ff4a0000 { 726 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 727 reg = <0xff4a0000 0x100>; 728 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 729 reg-shift = <2>; 730 reg-io-width = <4>; 731 dmas = <&dmac 7>, <&dmac 6>; 732 clock-frequency = <24000000>; 733 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 734 clock-names = "baudclk", "apb_pclk"; 735 pinctrl-names = "default"; 736 pinctrl-0 = <&uart0m0_xfer>; 737 status = "disabled"; 738 }; 739 740 uart1: serial@ff4b0000 { 741 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 742 reg = <0xff4b0000 0x100>; 743 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 744 reg-shift = <2>; 745 reg-io-width = <4>; 746 dmas = <&dmac 9>, <&dmac 8>; 747 clock-frequency = <24000000>; 748 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 749 clock-names = "baudclk", "apb_pclk"; 750 pinctrl-names = "default"; 751 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; 752 status = "disabled"; 753 }; 754 755 uart2: serial@ff4c0000 { 756 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 757 reg = <0xff4c0000 0x100>; 758 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 759 reg-shift = <2>; 760 reg-io-width = <4>; 761 dmas = <&dmac 11>, <&dmac 10>; 762 clock-frequency = <24000000>; 763 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 764 clock-names = "baudclk", "apb_pclk"; 765 pinctrl-names = "default"; 766 pinctrl-0 = <&uart2m1_xfer>; 767 status = "disabled"; 768 }; 769 770 uart3: serial@ff4d0000 { 771 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 772 reg = <0xff4d0000 0x100>; 773 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 774 reg-shift = <2>; 775 reg-io-width = <4>; 776 dmas = <&dmac 13>, <&dmac 12>; 777 clock-frequency = <24000000>; 778 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 779 clock-names = "baudclk", "apb_pclk"; 780 pinctrl-names = "default"; 781 pinctrl-0 = <&uart3m0_xfer>; 782 status = "disabled"; 783 }; 784 785 uart4: serial@ff4e0000 { 786 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 787 reg = <0xff4e0000 0x100>; 788 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 789 reg-shift = <2>; 790 reg-io-width = <4>; 791 dmas = <&dmac 15>, <&dmac 14>; 792 clock-frequency = <24000000>; 793 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 794 clock-names = "baudclk", "apb_pclk"; 795 pinctrl-names = "default"; 796 pinctrl-0 = <&uart4m0_xfer>; 797 status = "disabled"; 798 }; 799 800 uart5: serial@ff4f0000 { 801 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 802 reg = <0xff4f0000 0x100>; 803 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 804 reg-shift = <2>; 805 reg-io-width = <4>; 806 dmas = <&dmac 17>, <&dmac 16>; 807 clock-frequency = <24000000>; 808 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 809 clock-names = "baudclk", "apb_pclk"; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>; 812 status = "disabled"; 813 }; 814 815 spi0: spi@ff500000 { 816 compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi"; 817 reg = <0xff500000 0x1000>; 818 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 822 clock-names = "spiclk", "apb_pclk"; 823 dmas = <&dmac 1>, <&dmac 0>; 824 dma-names = "tx", "rx"; 825 pinctrl-names = "default"; 826 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 827 status = "disabled"; 828 }; 829 830 spi1: spi@ff510000 { 831 compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi"; 832 reg = <0xff510000 0x1000>; 833 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 837 clock-names = "spiclk", "apb_pclk"; 838 dmas = <&dmac 3>, <&dmac 2>; 839 dma-names = "tx", "rx"; 840 pinctrl-names = "default"; 841 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 842 status = "disabled"; 843 }; 844 845 hw_decompress: decompress@ff520000 { 846 compatible = "rockchip,hw-decompress"; 847 reg = <0xff520000 0x1000>; 848 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 850 clock-names = "aclk", "dclk", "pclk"; 851 resets = <&cru SRST_D_DECOM>; 852 reset-names = "dresetn"; 853 status = "disabled"; 854 }; 855 856 ioc: syscon@ff538000 { 857 compatible = "rockchip,rv1106-ioc", "syscon"; 858 reg = <0xff538000 0x40000>; 859 }; 860 861 wdt: watchdog@ff5a0000 { 862 compatible = "rockchip,rv1106-wdt", "snps,dw-wdt"; 863 reg = <0xff5a0000 0x100>; 864 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 865 clock-names = "tclk", "pclk"; 866 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 867 resets = <&cru SRST_P_WDT_NS>; 868 reset-names = "reset"; 869 status = "disabled"; 870 }; 871 872 mailbox: mailbox@ff5c0000 { 873 compatible = "rockchip,rv1106-mailbox", 874 "rockchip,rk3368-mailbox"; 875 reg = <0xff5c0000 0x200>; 876 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&cru PCLK_MAILBOX>; 878 clock-names = "pclk_mailbox"; 879 #mbox-cells = <1>; 880 status = "disabled"; 881 }; 882 883 npu: npu@ff660000 { 884 compatible = "rockchip,rv1106-rknpu"; 885 reg = <0xff660000 0x10000>; 886 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; 888 clock-names = "aclk", "hclk"; 889 resets = <&cru SRST_A_RKNN>, <&cru SRST_H_RKNN>; 890 reset-names = "srst_a", "srst_h"; 891 status = "disabled"; 892 }; 893 894 rga2: rga@ff980000 { 895 compatible = "rockchip,rga2_core0"; 896 reg = <0xff980000 0x1000>; 897 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>; 899 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; 900 status = "disabled"; 901 }; 902 903 vop: vop@ff990000 { 904 compatible = "rockchip,rv1106-vop"; 905 reg = <0xff990000 0x200>; 906 reg-names = "regs"; 907 rockchip,grf = <&grf>; 908 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 910 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 911 status = "disabled"; 912 913 vop_out: port { 914 #address-cells = <1>; 915 #size-cells = <0>; 916 917 vop_out_rgb: endpoint@0 { 918 reg = <0>; 919 remote-endpoint = <&rgb_in_vop>; 920 }; 921 }; 922 }; 923 924 sdio: mmc@ff9a0000 { 925 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 926 reg = <0xff9a0000 0x4000>; 927 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 929 <&grf_cru SCLK_SDIO_DRV>, <&grf_cru SCLK_SDIO_SAMPLE>; 930 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 931 fifo-depth = <0x100>; 932 max-frequency = <200000000>; 933 status = "disabled"; 934 }; 935 936 rkisp: rkisp@ffa00000 { 937 compatible = "rockchip,rv1106-rkisp"; 938 reg = <0xffa00000 0x7f00>; 939 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 942 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 943 clocks = <&cru ACLK_ISP3P2>, <&cru HCLK_ISP3P2>, 944 <&cru CLK_CORE_ISP3P2>, <&cru ISP0CLK_VICAP>; 945 clock-names = "aclk_isp", "hclk_isp", 946 "clk_isp_core", "clk_isp_core_vicap"; 947 status = "disabled"; 948 }; 949 950 rkcif: rkcif@ffa10000 { 951 compatible = "rockchip,rv1106-cif"; 952 reg = <0xffa10000 0x10000>; 953 reg-names = "cif_regs"; 954 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 955 interrupt-names = "cif-intr"; 956 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, 957 <&cru DCLK_VICAP>, <&cru PCLK_VICAP>, 958 <&cru I0CLK_VICAP>, <&cru I1CLK_VICAP>, 959 <&cru RX0PCLK_VICAP>, <&cru RX1PCLK_VICAP>, 960 <&cru ISP0CLK_VICAP>, <&cru SCLK_VICAP_M0>, 961 <&cru SCLK_VICAP_M1>, <&cru PCLK_VICAP_VEPU>; 962 clock-names = "aclk_cif","hclk_cif", 963 "dclk_cif", "pclk_cif", 964 "i0clk_cif", "i1clk_cif", 965 "rx0clk_cif", "rx1clk_cif", 966 "isp0clk_cif", "sclk_m0_cif", 967 "sclk_m1_cif", "pclk_vepu_cif"; 968 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, 969 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, 970 <&cru SRST_VICAP_I0>, <&cru SRST_VICAP_I1>, 971 <&cru SRST_VICAP_RX0>, <&cru SRST_VICAP_RX1>, 972 <&cru SRST_VICAP_ISP0>, <&cru SRST_P_VICAP_VEPU>; 973 reset-names = "rst_cif_a","rst_cif_h", 974 "rst_cif_d", "rst_cif_p", 975 "rst_cif_i0", "rst_cif_i1", 976 "rst_cif_rx0", "rst_cif_rx1", 977 "rst_cif_isp0", "rst_cif_pclk_vepu"; 978 rockchip,grf = <&grf>; 979 status = "disabled"; 980 }; 981 982 mipi0_csi2: mipi-csi2@ffa20000 { 983 compatible = "rockchip,rk3588-mipi-csi2"; 984 reg = <0xffa20000 0x10000>; 985 reg-names = "csihost_regs"; 986 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 988 interrupt-names = "csi-intr1", "csi-intr2"; 989 clocks = <&cru PCLK_CSIHOST0>, <&cru CLK_RXBYTECLKHS_0>; 990 clock-names = "pclk_csi2host", "clk_rxbyte_hs"; 991 resets = <&cru SRST_P_CSIHOST0>; 992 reset-names = "srst_csihost_p"; 993 status = "disabled"; 994 }; 995 996 mipi1_csi2: mipi-csi2@ffa30000 { 997 compatible = "rockchip,rk3588-mipi-csi2"; 998 reg = <0xffa30000 0x10000>; 999 reg-names = "csihost_regs"; 1000 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1002 interrupt-names = "csi-intr1", "csi-intr2"; 1003 clocks = <&cru PCLK_CSIHOST1>, <&cru CLK_RXBYTECLKHS_1>; 1004 clock-names = "pclk_csi2host", "clk_rxbyte_hs"; 1005 resets = <&cru SRST_P_CSIHOST1>; 1006 reset-names = "srst_csihost_p"; 1007 status = "disabled"; 1008 }; 1009 1010 rkvenc: rkvenc@ffa50000 { 1011 compatible = "rockchip,rkv-encoder-rv1106"; 1012 reg = <0xffa50000 0x6000>; 1013 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1014 interrupt-names = "irq_rkvenc"; 1015 clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>, <&cru CLK_CORE_VEPU>; 1016 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1017 rockchip,normal-rates = <300000000>, <0>, <400000000>; 1018 assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>; 1019 assigned-clock-rates = <300000000>, <400000000>; 1020 resets = <&cru SRST_A_VEPU>, <&cru SRST_H_VEPU>, <&cru SRST_CORE_VEPU>; 1021 reset-names = "video_a", "video_h", "video_core"; 1022 rockchip,srv = <&mpp_srv>; 1023 rockchip,taskqueue-node = <0>; 1024 dvbm = <&rkdvbm>; 1025 status = "disabled"; 1026 }; 1027 1028 rkdvbm: rkdvbm@ffa70000 { 1029 compatible = "rockchip,rk-dvbm"; 1030 reg = <0xffa70000 0x90>; 1031 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1032 interrupt-names = "irq_rkdvbm"; 1033 clocks = <&cru CLK_CORE_VEPU_DVBM>; 1034 clock-names = "clk_core"; 1035 assigned-clocks = <&cru CLK_CORE_VEPU_DVBM>; 1036 assigned-clock-rates = <200000000>; 1037 resets = <&cru SRST_CORE_VEPU_DVBM>; 1038 reset-names = "dvbm_rst"; 1039 status = "disabled"; 1040 }; 1041 1042 gmac: ethernet@ffa80000 { 1043 compatible = "rockchip,rv1106-gmac", "snps,dwmac-4.20a"; 1044 reg = <0xffa80000 0x10000>; 1045 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1047 interrupt-names = "macirq", "eth_wake_irq"; 1048 rockchip,grf = <&grf>; 1049 clocks = <&cru CLK_GMAC0_TX_50M_O>, <&cru CLK_GMAC0_REF_50M>, 1050 <&cru ACLK_MAC>, <&cru PCLK_MAC>; 1051 clock-names = "stmmaceth", "clk_mac_ref", 1052 "aclk_mac", "pclk_mac"; 1053 resets = <&cru SRST_A_MAC>; 1054 reset-names = "stmmaceth"; 1055 1056 snps,mixed-burst; 1057 snps,tso; 1058 1059 tx-dma-size = <256>; 1060 rx-dma-size = <16>; 1061 1062 snps,axi-config = <&stmmac_axi_setup>; 1063 snps,mtl-rx-config = <&mtl_rx_setup>; 1064 snps,mtl-tx-config = <&mtl_tx_setup>; 1065 1066 phy-mode = "rmii"; 1067 clock_in_out = "input"; 1068 phy-handle = <&rmii_phy>; 1069 1070 nvmem-cells = <&macphy_bgs>; 1071 nvmem-cell-names = "bgs"; 1072 status = "disabled"; 1073 1074 mdio: mdio { 1075 compatible = "snps,dwmac-mdio"; 1076 #address-cells = <0x1>; 1077 #size-cells = <0x0>; 1078 rmii_phy: ethernet-phy@2 { 1079 compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22"; 1080 reg = <2>; 1081 clocks = <&cru CLK_MACPHY>; 1082 resets = <&cru SRST_MACPHY>; 1083 phy-is-integrated; 1084 nvmem-cells = <&macphy_txlevel>; 1085 nvmem-cell-names = "txlevel"; 1086 }; 1087 }; 1088 1089 stmmac_axi_setup: stmmac-axi-config { 1090 snps,wr_osr_lmt = <4>; 1091 snps,rd_osr_lmt = <8>; 1092 snps,blen = <0 0 0 0 16 8 4>; 1093 }; 1094 1095 mtl_rx_setup: rx-queues-config { 1096 snps,rx-queues-to-use = <1>; 1097 queue0 { 1098 status = "okay"; 1099 }; 1100 }; 1101 1102 mtl_tx_setup: tx-queues-config { 1103 snps,tx-queues-to-use = <1>; 1104 queue0 { 1105 status = "okay"; 1106 }; 1107 }; 1108 }; 1109 1110 emmc: mmc@ffa90000 { 1111 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 1112 reg = <0xffa90000 0x4000>; 1113 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&cru HCLK_EMMC>, <&cru CCLK_SRC_EMMC>, 1115 <&grf_cru SCLK_EMMC_DRV>, <&grf_cru SCLK_EMMC_SAMPLE>; 1116 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1117 fifo-depth = <0x100>; 1118 max-frequency = <200000000>; 1119 rockchip,use-v2-tuning; 1120 status = "disabled"; 1121 }; 1122 1123 sdmmc: mmc@ffaa0000 { 1124 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 1125 reg = <0xffaa0000 0x4000>; 1126 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>, 1128 <&grf_cru SCLK_SDMMC_DRV>, <&grf_cru SCLK_SDMMC_SAMPLE>; 1129 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1130 cd-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 1131 fifo-depth = <0x100>; 1132 max-frequency = <200000000>; 1133 pinctrl-names = "default", "idle"; 1134 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; 1135 pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>; 1136 status = "disabled"; 1137 }; 1138 1139 sfc: spi@ffac0000 { 1140 compatible = "rockchip,sfc"; 1141 reg = <0xffac0000 0x4000>; 1142 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1144 clock-names = "clk_sfc", "hclk_sfc"; 1145 assigned-clocks = <&cru SCLK_SFC>; 1146 assigned-clock-rates = <75000000>; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 status = "disabled"; 1150 }; 1151 1152 rve: rve@ffad0000 { 1153 compatible = "rockchip,rve"; 1154 reg = <0xffad0000 0x1000>; 1155 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1156 clocks = <&cru ACLK_IVE>, <&cru HCLK_IVE>; 1157 clock-names = "aclk_rve", "hclk_rve"; 1158 status = "disabled"; 1159 }; 1160 1161 i2s0_8ch: i2s@ffae0000 { 1162 compatible = "rockchip,rv1106-i2s-tdm"; 1163 reg = <0xffae0000 0x1000>; 1164 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1165 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0>; 1166 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1167 dmas = <&dmac 22>, <&dmac 21>; 1168 dma-names = "tx", "rx"; 1169 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1170 reset-names = "tx-m", "rx-m"; 1171 rockchip,clk-trcm = <1>; 1172 #sound-dai-cells = <0>; 1173 status = "disabled"; 1174 }; 1175 1176 usbdrd: usbdrd { 1177 compatible = "rockchip,rv1106-dwc3", "rockchip,rk3399-dwc3"; 1178 clocks = <&cru CLK_REF_USBOTG>, <&cru CLK_UTMI_USBOTG>, 1179 <&cru ACLK_USBOTG>; 1180 clock-names = "ref", "utmi", "bus"; 1181 #address-cells = <1>; 1182 #size-cells = <1>; 1183 ranges; 1184 status = "disabled"; 1185 1186 usbdrd_dwc3: usb@ffb00000 { 1187 compatible = "snps,dwc3"; 1188 reg = <0xffb00000 0x100000>; 1189 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1190 resets = <&cru SRST_A_USBOTG>; 1191 reset-names = "usb3-otg"; 1192 dr_mode = "otg"; 1193 maximum-speed = "high-speed"; 1194 phys = <&u2phy_otg>; 1195 phy-names = "usb2-phy"; 1196 phy_type = "utmi_wide"; 1197 snps,dis_enblslpm_quirk; 1198 snps,dis-u2-freeclk-exists-quirk; 1199 snps,dis_u2_susphy_quirk; 1200 snps,dis-del-phy-power-chg-quirk; 1201 snps,dis-tx-ipgap-linecheck-quirk; 1202 status = "disabled"; 1203 }; 1204 }; 1205 1206 pinctrl: pinctrl { 1207 compatible = "rockchip,rv1106-pinctrl"; 1208 rockchip,grf = <&ioc>; 1209 rockchip,pmu = <&pmuioc>; 1210 #address-cells = <1>; 1211 #size-cells = <1>; 1212 ranges; 1213 1214 gpio0: gpio@ff380000 { 1215 compatible = "rockchip,gpio-bank"; 1216 reg = <0xff380000 0x100>; 1217 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1218 clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>; 1219 1220 gpio-controller; 1221 #gpio-cells = <2>; 1222 gpio-ranges = <&pinctrl 0 0 32>; 1223 interrupt-controller; 1224 #interrupt-cells = <2>; 1225 }; 1226 1227 gpio1: gpio@ff530000 { 1228 compatible = "rockchip,gpio-bank"; 1229 reg = <0xff530000 0x100>; 1230 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1232 1233 gpio-controller; 1234 #gpio-cells = <2>; 1235 gpio-ranges = <&pinctrl 0 32 32>; 1236 interrupt-controller; 1237 #interrupt-cells = <2>; 1238 }; 1239 1240 gpio2: gpio@ff540000 { 1241 compatible = "rockchip,gpio-bank"; 1242 reg = <0xff540000 0x100>; 1243 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1244 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1245 1246 gpio-controller; 1247 #gpio-cells = <2>; 1248 gpio-ranges = <&pinctrl 0 64 32>; 1249 interrupt-controller; 1250 #interrupt-cells = <2>; 1251 }; 1252 1253 gpio3: gpio@ff550000 { 1254 compatible = "rockchip,gpio-bank"; 1255 reg = <0xff550000 0x100>; 1256 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1258 1259 gpio-controller; 1260 #gpio-cells = <2>; 1261 gpio-ranges = <&pinctrl 0 96 32>; 1262 interrupt-controller; 1263 #interrupt-cells = <2>; 1264 }; 1265 1266 gpio4: gpio@ff560000 { 1267 compatible = "rockchip,gpio-bank"; 1268 reg = <0xff560000 0x100>; 1269 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1270 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1271 1272 gpio-controller; 1273 #gpio-cells = <2>; 1274 gpio-ranges = <&pinctrl 0 128 32>; 1275 interrupt-controller; 1276 #interrupt-cells = <2>; 1277 }; 1278 }; 1279}; 1280 1281#include "rv1106-pinctrl.dtsi" 1282