1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5#include <dt-bindings/clock/rv1106-cru.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11#include <dt-bindings/soc/rockchip-system-status.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1106"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 serial0 = &uart0; 30 serial1 = &uart1; 31 serial2 = &uart2; 32 serial3 = &uart3; 33 serial4 = &uart4; 34 serial5 = &uart5; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu0: cpu@f00 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a7"; 44 reg = <0xf00>; 45 }; 46 }; 47 48 arm-pmu { 49 compatible = "arm,cortex-a7-pmu"; 50 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 51 interrupt-affinity = <&cpu0>; 52 }; 53 54 fiq_debugger: fiq-debugger { 55 compatible = "rockchip,fiq-debugger"; 56 rockchip,serial-id = <2>; 57 rockchip,wake-irq = <0>; 58 rockchip,irq-mode-enable = <0>; 59 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 60 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 61 status = "disabled"; 62 }; 63 64 reserved-memory { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 ranges; 68 69 linux,cma { 70 compatible = "shared-dma-pool"; 71 inactive; 72 reusable; 73 size = <0x800000>; 74 linux,cma-default; 75 }; 76 }; 77 78 timer { 79 compatible = "arm,armv7-timer"; 80 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 81 clock-frequency = <24000000>; 82 }; 83 84 xin24m: oscillator { 85 compatible = "fixed-clock"; 86 clock-frequency = <24000000>; 87 clock-output-names = "xin24m"; 88 #clock-cells = <0>; 89 }; 90 91 grf: syscon@ff000000 { 92 compatible = "rockchip,rv1106-grf", "syscon", "simple-mfd"; 93 reg = <0xff000000 0x68000>; 94 }; 95 96 rtc: rtc@ff1c0000 { 97 compatible = "rockchip,rtc-1.0"; 98 reg = <0xff1c0000 0x1000>; 99 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 100 clocks = <&cru PCLK_VI_RTC_PHY>; 101 clock-names = "pclk"; 102 status = "disabled"; 103 }; 104 105 gic: interrupt-controller@ff1f0000 { 106 compatible = "arm,gic-400"; 107 interrupt-controller; 108 #interrupt-cells = <3>; 109 #address-cells = <0>; 110 111 reg = <0xff1f1000 0x1000>, 112 <0xff1f2000 0x2000>, 113 <0xff1f4000 0x2000>, 114 <0xff1f6000 0x2000>; 115 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 116 }; 117 118 arm-debug@ff200000 { 119 compatible = "rockchip,debug"; 120 reg = <0xff200000 0x1000>; 121 }; 122 123 i2c0: i2c@ff310000 { 124 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 125 reg = <0xff310000 0x1000>; 126 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 127 #address-cells = <1>; 128 #size-cells = <0>; 129 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 130 clock-names = "i2c", "pclk"; 131 status = "disabled"; 132 }; 133 134 i2c1: i2c@ff320000 { 135 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 136 reg = <0xff320000 0x1000>; 137 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 141 clock-names = "i2c", "pclk"; 142 status = "disabled"; 143 }; 144 145 dsm: codec-digital@ff340000 { 146 compatible = "rockchip,rv1106-codec-digital", "rockchip,codec-digital-v1"; 147 reg = <0xff340000 0x1000>; 148 clocks = <&cru MCLK_DSM>, <&cru PCLK_DSM>; 149 clock-names = "dac", "pclk"; 150 resets = <&cru SRST_M_DSM>; 151 reset-names = "reset" ; 152 rockchip,grf = <&grf>; 153 rockchip,pwm-output-mode; 154 #sound-dai-cells = <0>; 155 status = "disabled"; 156 }; 157 158 cru: clock-controller@ff3a0000 { 159 compatible = "rockchip,rv1106-cru"; 160 reg = <0xff3a0000 0x20000>; 161 rockchip,grf = <&grf>; 162 #clock-cells = <1>; 163 #reset-cells = <1>; 164 165 assigned-clocks = 166 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 167 <&cru ARMCLK>, 168 <&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>, 169 <&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>, 170 <&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>, 171 <&cru HCLK_PMU_ROOT>; 172 assigned-clock-rates = 173 <1188000000>, <1000000000>, 174 <816000000>, 175 <400000000>, <200000000>, 176 <100000000>, <300000000>, 177 <100000000>, <100000000>, 178 <200000000>; 179 }; 180 181 dmac: dma-controller@ff420000 { 182 compatible = "arm,pl330", "arm,primecell"; 183 reg = <0xff420000 0x4000>; 184 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 193 #dma-cells = <1>; 194 clocks = <&cru ACLK_DMAC>; 195 clock-names = "apb_pclk"; 196 arm,pl330-periph-burst; 197 }; 198 199 i2c2: i2c@ff450000 { 200 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 201 reg = <0xff450000 0x1000>; 202 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 206 clock-names = "i2c", "pclk"; 207 status = "disabled"; 208 }; 209 210 i2c3: i2c@ff460000 { 211 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 212 reg = <0xff460000 0x1000>; 213 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 217 clock-names = "i2c", "pclk"; 218 status = "disabled"; 219 }; 220 221 i2c4: i2c@ff470000 { 222 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 223 reg = <0xff470000 0x1000>; 224 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 228 clock-names = "i2c", "pclk"; 229 status = "disabled"; 230 }; 231 232 uart0: serial@ff4a0000 { 233 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 234 reg = <0xff4a0000 0x100>; 235 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 236 reg-shift = <2>; 237 reg-io-width = <4>; 238 dmas = <&dmac 7>, <&dmac 6>; 239 clock-frequency = <24000000>; 240 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 241 clock-names = "baudclk", "apb_pclk"; 242 status = "disabled"; 243 }; 244 245 uart1: serial@ff4b0000 { 246 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 247 reg = <0xff4b0000 0x100>; 248 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 249 reg-shift = <2>; 250 reg-io-width = <4>; 251 dmas = <&dmac 9>, <&dmac 8>; 252 clock-frequency = <24000000>; 253 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 254 clock-names = "baudclk", "apb_pclk"; 255 status = "disabled"; 256 }; 257 258 uart2: serial@ff4c0000 { 259 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 260 reg = <0xff4c0000 0x100>; 261 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 262 reg-shift = <2>; 263 reg-io-width = <4>; 264 dmas = <&dmac 11>, <&dmac 10>; 265 clock-frequency = <24000000>; 266 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 267 clock-names = "baudclk", "apb_pclk"; 268 status = "disabled"; 269 }; 270 271 uart3: serial@ff4d0000 { 272 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 273 reg = <0xff4d0000 0x100>; 274 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 275 reg-shift = <2>; 276 reg-io-width = <4>; 277 dmas = <&dmac 13>, <&dmac 12>; 278 clock-frequency = <24000000>; 279 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 280 clock-names = "baudclk", "apb_pclk"; 281 status = "disabled"; 282 }; 283 284 uart4: serial@ff4e0000 { 285 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 286 reg = <0xff4e0000 0x100>; 287 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 288 reg-shift = <2>; 289 reg-io-width = <4>; 290 dmas = <&dmac 15>, <&dmac 14>; 291 clock-frequency = <24000000>; 292 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 293 clock-names = "baudclk", "apb_pclk"; 294 status = "disabled"; 295 }; 296 297 uart5: serial@ff4f0000 { 298 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 299 reg = <0xff4f0000 0x100>; 300 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 301 reg-shift = <2>; 302 reg-io-width = <4>; 303 dmas = <&dmac 17>, <&dmac 16>; 304 clock-frequency = <24000000>; 305 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 306 clock-names = "baudclk", "apb_pclk"; 307 status = "disabled"; 308 }; 309 310 sdio: mmc@ff9a0000 { 311 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 312 reg = <0xff9a0000 0x4000>; 313 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 315 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 316 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 317 fifo-depth = <0x100>; 318 max-frequency = <200000000>; 319 status = "disabled"; 320 }; 321 322 gmac: ethernet@ffa80000 { 323 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; 324 reg = <0xffa80000 010000>; 325 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 327 interrupt-names = "macirq", "eth_wake_irq"; 328 rockchip,grf = <&grf>; 329 clocks = <&cru CLK_GMAC0_TX_50M_O>, <&cru CLK_GMAC0_REF_50M>, 330 <&cru ACLK_MAC>, <&cru PCLK_MAC>; 331 clock-names = "stmmaceth", "clk_mac_ref", 332 "aclk_mac", "pclk_mac"; 333 resets = <&cru SRST_A_MAC>; 334 reset-names = "stmmaceth"; 335 336 snps,mixed-burst; 337 snps,tso; 338 339 snps,axi-config = <&stmmac_axi_setup>; 340 snps,mtl-rx-config = <&mtl_rx_setup>; 341 snps,mtl-tx-config = <&mtl_tx_setup>; 342 343 phy-mode = "rmii"; 344 phy-handle = <&rmii_phy>; 345 status = "disabled"; 346 347 mdio: mdio { 348 compatible = "snps,dwmac-mdio"; 349 #address-cells = <0x1>; 350 #size-cells = <0x0>; 351 rmii_phy: ethernet-phy@2 { 352 compatible = "ethernet-phy-ieee802.3-c22"; 353 reg = <2>; 354 clocks = <&cru CLK_MACPHY>; 355 resets = <&cru SRST_MACPHY>; 356 phy-is-integrated; 357 }; 358 }; 359 360 stmmac_axi_setup: stmmac-axi-config { 361 snps,wr_osr_lmt = <4>; 362 snps,rd_osr_lmt = <8>; 363 snps,blen = <0 0 0 0 16 8 4>; 364 }; 365 366 mtl_rx_setup: rx-queues-config { 367 snps,rx-queues-to-use = <1>; 368 queue0 {}; 369 }; 370 371 mtl_tx_setup: tx-queues-config { 372 snps,tx-queues-to-use = <1>; 373 queue0 {}; 374 }; 375 }; 376 377 emmc: mmc@ffa90000 { 378 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 379 reg = <0xffa90000 0x4000>; 380 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&cru HCLK_EMMC>, <&cru CCLK_SRC_EMMC>, 382 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 383 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 384 fifo-depth = <0x100>; 385 max-frequency = <200000000>; 386 rockchip,use-v2-tuning; 387 status = "disabled"; 388 }; 389 390 sdmmc: mmc@ffaa0000 { 391 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 392 reg = <0xffaa0000 0x4000>; 393 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>, 395 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 396 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 397 fifo-depth = <0x100>; 398 max-frequency = <200000000>; 399 status = "disabled"; 400 }; 401 402 i2s0_8ch: i2s@ffae0000 { 403 compatible = "rockchip,rv1106-i2s-tdm"; 404 reg = <0xffae0000 0x1000>; 405 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0>; 407 clock-names = "mclk_tx", "mclk_rx", "hclk"; 408 dmas = <&dmac 22>, <&dmac 21>; 409 dma-names = "tx", "rx"; 410 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 411 reset-names = "tx-m", "rx-m"; 412 rockchip,clk-trcm = <1>; 413 #sound-dai-cells = <0>; 414 status = "disabled"; 415 }; 416}; 417