1/* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc1 = &sdmmc; 10 mmc0 = &emmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc; 16 }; 17}; 18 19 20&emmc { 21 mmc-ecsd = <0x0020f000>; 22 u-boot,dm-spl; 23 status = "okay"; 24}; 25 26&cru { 27 u-boot,dm-spl; 28 status = "okay"; 29}; 30 31&gmac { 32 u-boot,dm-spl; 33 status = "okay"; 34}; 35 36&grf { 37 u-boot,dm-spl; 38 status = "okay"; 39}; 40 41&mdio { 42 u-boot,dm-spl; 43 status = "okay"; 44}; 45 46&rmii_phy { 47 u-boot,dm-spl; 48 status = "okay"; 49}; 50 51&sdmmc { 52 u-boot,dm-spl; 53 status = "okay"; 54}; 55 56&crypto { 57 u-boot,dm-spl; 58 clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 59 clock-frequency = <300000000>, <300000000>; 60 status = "okay"; 61}; 62 63&rng { 64 u-boot,dm-spl; 65 status = "okay"; 66}; 67 68&saradc { 69 u-boot,dm-pre-reloc; 70 status = "okay"; 71}; 72 73&sfc { 74 u-boot,dm-spl; 75 status = "okay"; 76 77 #address-cells = <1>; 78 #size-cells = <0>; 79 spi_nand: flash@0 { 80 u-boot,dm-spl; 81 compatible = "spi-nand"; 82 reg = <0>; 83 spi-tx-bus-width = <1>; 84 spi-rx-bus-width = <4>; 85 spi-max-frequency = <80000000>; 86 }; 87 88 spi_nor: flash@1 { 89 u-boot,dm-spl; 90 compatible = "jedec,spi-nor"; 91 label = "sfc_nor"; 92 reg = <0>; 93 spi-tx-bus-width = <1>; 94 spi-rx-bus-width = <4>; 95 spi-max-frequency = <100000000>; 96 }; 97}; 98