1/* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc1 = &sdmmc; 10 mmc0 = &emmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc; 16 }; 17 18 secure_otp: secure_otp@ff3fd8000 { 19 compatible = "rockchip,rv1106-secure-otp"; 20 reg = <0xff3d8000 0x4000>; 21 secure_conf = <0xff07a018>; 22 cru_rst_addr = <0xff3bca08>; 23 mask_addr = <0xff3dc000>; 24 u-boot,dm-spl; 25 status = "okay"; 26 }; 27}; 28 29&emmc { 30 mmc-ecsd = <0x0020f000>; 31 u-boot,dm-spl; 32 status = "okay"; 33}; 34 35&cru { 36 u-boot,dm-spl; 37 status = "okay"; 38}; 39 40&gmac { 41 u-boot,dm-spl; 42 status = "okay"; 43}; 44 45&grf { 46 u-boot,dm-spl; 47 status = "okay"; 48}; 49 50&grf_cru { 51 u-boot,dm-spl; 52 status = "okay"; 53}; 54 55&mdio { 56 u-boot,dm-spl; 57 status = "okay"; 58}; 59 60&rmii_phy { 61 u-boot,dm-spl; 62 status = "okay"; 63}; 64 65&sdmmc { 66 u-boot,dm-spl; 67 status = "okay"; 68}; 69 70&sdmmc0 { 71 u-boot,dm-spl; 72}; 73 74&sdmmc0_bus4 { 75 u-boot,dm-spl; 76}; 77 78&sdmmc0_clk { 79 u-boot,dm-spl; 80}; 81 82&sdmmc0_cmd { 83 u-boot,dm-spl; 84}; 85 86&sdmmc0_det { 87 u-boot,dm-spl; 88}; 89 90&pinctrl { 91 u-boot,dm-spl; 92 status = "okay"; 93}; 94 95&ioc { 96 u-boot,dm-spl; 97 status = "okay"; 98}; 99 100&pmuioc { 101 u-boot,dm-spl; 102 status = "okay"; 103}; 104 105&pcfg_pull_up_drv_level_2 { 106 u-boot,dm-spl; 107}; 108 109&pcfg_pull_up { 110 u-boot,dm-spl; 111}; 112 113&gpio3 { 114 u-boot,dm-spl; 115 status = "okay"; 116}; 117 118&crypto { 119 u-boot,dm-spl; 120 clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 121 clock-frequency = <300000000>, <300000000>; 122 status = "okay"; 123}; 124 125&rng { 126 u-boot,dm-spl; 127 status = "okay"; 128}; 129 130&saradc { 131 u-boot,dm-pre-reloc; 132 status = "okay"; 133}; 134 135&sfc { 136 u-boot,dm-spl; 137 status = "okay"; 138 139 #address-cells = <1>; 140 #size-cells = <0>; 141 spi_nand: flash@0 { 142 u-boot,dm-spl; 143 compatible = "spi-nand"; 144 reg = <0>; 145 spi-tx-bus-width = <1>; 146 spi-rx-bus-width = <4>; 147 spi-max-frequency = <80000000>; 148 }; 149 150 spi_nor: flash@1 { 151 u-boot,dm-spl; 152 compatible = "jedec,spi-nor"; 153 label = "sfc_nor"; 154 reg = <0>; 155 spi-tx-bus-width = <1>; 156 spi-rx-bus-width = <4>; 157 spi-max-frequency = <100000000>; 158 }; 159}; 160