xref: /rk3399_rockchip-uboot/arch/arm/dts/rv1106-u-boot.dtsi (revision 5a318a778e0429ea8772dae79ff990c55efed3f1) 
1/*
2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		mmc1 = &sdmmc;
10		mmc0 = &emmc;
11	};
12
13	chosen {
14		stdout-path = &uart2;
15		u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc;
16	};
17
18	secure-otp@ff3fd8000 {
19		compatible = "rockchip,rv1106-secure-otp";
20		reg = <0xff3d8000 0x4000>;
21		secure_conf = <0xff07a018>;
22		cru_rst_addr = <0xff3bca08>;
23		mask_addr = <0xff3dc000>;
24		u-boot,dm-spl;
25		status = "okay";
26	};
27};
28
29&hw_decompress {
30	u-boot,dm-spl;
31	status = "okay";
32};
33
34&emmc {
35	mmc-ecsd = <0x3F000>;
36	bus-width = <8>;
37	mmc-hs200-1_8v;
38	u-boot,dm-spl;
39	status = "okay";
40};
41
42&cru {
43	u-boot,dm-spl;
44	status = "okay";
45};
46
47&gmac {
48	u-boot,dm-spl;
49	status = "okay";
50};
51
52&grf {
53	u-boot,dm-spl;
54	status = "okay";
55};
56
57&grf_cru {
58	u-boot,dm-spl;
59	status = "okay";
60};
61
62&mdio {
63	u-boot,dm-spl;
64	status = "okay";
65};
66
67&rmii_phy {
68	u-boot,dm-spl;
69	status = "okay";
70};
71
72&sdmmc {
73	u-boot,dm-spl;
74	pwr-en-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
75	status = "okay";
76};
77
78&sdmmc0 {
79	u-boot,dm-spl;
80};
81
82&sdmmc0_bus4 {
83	u-boot,dm-spl;
84};
85
86&sdmmc0_clk {
87	u-boot,dm-spl;
88};
89
90&sdmmc0_cmd {
91	u-boot,dm-spl;
92};
93
94&sdmmc0_det {
95	u-boot,dm-spl;
96};
97
98&sdmmc0_idle_pins {
99	u-boot,dm-spl;
100};
101
102&sdmmc1m1_idle_pins {
103	u-boot,dm-spl;
104};
105
106&pinctrl {
107	u-boot,dm-spl;
108	status = "okay";
109};
110
111&ioc {
112	u-boot,dm-spl;
113	status = "okay";
114};
115
116&pmuioc {
117	u-boot,dm-spl;
118	status = "okay";
119};
120
121&pcfg_pull_up_drv_level_2 {
122	u-boot,dm-spl;
123};
124
125&pcfg_pull_up {
126	u-boot,dm-spl;
127};
128
129&pcfg_pull_down{
130	u-boot,dm-spl;
131};
132
133&gpio0 {
134	u-boot,dm-spl;
135	status = "okay";
136};
137
138&gpio1 {
139	u-boot,dm-pre-reloc;
140	status = "okay";
141};
142
143&gpio2 {
144	u-boot,dm-pre-reloc;
145	status = "okay";
146};
147
148&gpio3 {
149	u-boot,dm-spl;
150	status = "okay";
151};
152
153&gpio4 {
154	u-boot,dm-pre-reloc;
155	status = "okay";
156};
157
158&crypto {
159	u-boot,dm-spl;
160	clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
161	clock-frequency = <300000000>, <300000000>;
162	status = "okay";
163};
164
165&rng {
166	u-boot,dm-spl;
167	status = "okay";
168};
169
170&saradc {
171	u-boot,dm-pre-reloc;
172	status = "okay";
173};
174
175&sfc {
176	u-boot,dm-spl;
177	status = "okay";
178
179	#address-cells = <1>;
180	#size-cells = <0>;
181	spi_nand: flash@0 {
182		u-boot,dm-spl;
183		compatible = "spi-nand";
184		reg = <0>;
185		spi-tx-bus-width = <1>;
186		spi-rx-bus-width = <4>;
187		spi-max-frequency = <80000000>;
188	};
189
190	spi_nor: flash@1 {
191		u-boot,dm-spl;
192		compatible = "jedec,spi-nor";
193		label = "sfc_nor";
194		reg = <0>;
195		spi-tx-bus-width = <1>;
196		spi-rx-bus-width = <4>;
197		spi-max-frequency = <100000000>;
198	};
199};
200
201&u2phy {
202	u-boot,dm-pre-reloc;
203	status = "okay";
204};
205
206&u2phy_otg {
207	u-boot,dm-pre-reloc;
208	status = "okay";
209};
210