1/* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc1 = &sdmmc; 10 mmc0 = &emmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc; 16 }; 17 18 secure_otp: secure_otp@ff3fd8000 { 19 compatible = "rockchip,rv1106-secure-otp"; 20 reg = <0xff3d8000 0x4000>; 21 secure_conf = <0xff07a018>; 22 cru_rst_addr = <0xff3bca08>; 23 mask_addr = <0xff3dc000>; 24 u-boot,dm-spl; 25 status = "okay"; 26 }; 27}; 28 29&emmc { 30 mmc-ecsd = <0x3fe00>; 31 bus-width = <8>; 32 mmc-hs200-1_8v; 33 u-boot,dm-spl; 34 status = "okay"; 35}; 36 37&cru { 38 u-boot,dm-spl; 39 status = "okay"; 40}; 41 42&gmac { 43 u-boot,dm-spl; 44 status = "okay"; 45}; 46 47&grf { 48 u-boot,dm-spl; 49 status = "okay"; 50}; 51 52&grf_cru { 53 u-boot,dm-spl; 54 status = "okay"; 55}; 56 57&mdio { 58 u-boot,dm-spl; 59 status = "okay"; 60}; 61 62&rmii_phy { 63 u-boot,dm-spl; 64 status = "okay"; 65}; 66 67&sdmmc { 68 u-boot,dm-spl; 69 status = "okay"; 70}; 71 72&sdmmc0 { 73 u-boot,dm-spl; 74}; 75 76&sdmmc0_bus4 { 77 u-boot,dm-spl; 78}; 79 80&sdmmc0_clk { 81 u-boot,dm-spl; 82}; 83 84&sdmmc0_cmd { 85 u-boot,dm-spl; 86}; 87 88&sdmmc0_det { 89 u-boot,dm-spl; 90}; 91 92&pinctrl { 93 u-boot,dm-spl; 94 status = "okay"; 95}; 96 97&ioc { 98 u-boot,dm-spl; 99 status = "okay"; 100}; 101 102&pmuioc { 103 u-boot,dm-spl; 104 status = "okay"; 105}; 106 107&pcfg_pull_up_drv_level_2 { 108 u-boot,dm-spl; 109}; 110 111&pcfg_pull_up { 112 u-boot,dm-spl; 113}; 114 115&gpio3 { 116 u-boot,dm-spl; 117 status = "okay"; 118}; 119 120&crypto { 121 u-boot,dm-spl; 122 clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 123 clock-frequency = <300000000>, <300000000>; 124 status = "okay"; 125}; 126 127&rng { 128 u-boot,dm-spl; 129 status = "okay"; 130}; 131 132&saradc { 133 u-boot,dm-pre-reloc; 134 status = "okay"; 135}; 136 137&sfc { 138 u-boot,dm-spl; 139 status = "okay"; 140 141 #address-cells = <1>; 142 #size-cells = <0>; 143 spi_nand: flash@0 { 144 u-boot,dm-spl; 145 compatible = "spi-nand"; 146 reg = <0>; 147 spi-tx-bus-width = <1>; 148 spi-rx-bus-width = <4>; 149 spi-max-frequency = <80000000>; 150 }; 151 152 spi_nor: flash@1 { 153 u-boot,dm-spl; 154 compatible = "jedec,spi-nor"; 155 label = "sfc_nor"; 156 reg = <0>; 157 spi-tx-bus-width = <1>; 158 spi-rx-bus-width = <4>; 159 spi-max-frequency = <100000000>; 160 }; 161}; 162