1/* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc1 = &sdmmc; 10 mmc0 = &emmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc; 16 }; 17}; 18 19 20&emmc { 21 mmc-ecsd = <0x0020f000>; 22 u-boot,dm-spl; 23 status = "okay"; 24}; 25 26&cru { 27 u-boot,dm-spl; 28 status = "okay"; 29}; 30 31&gmac { 32 u-boot,dm-spl; 33 status = "okay"; 34}; 35 36&grf { 37 u-boot,dm-spl; 38 status = "okay"; 39}; 40 41&grf_cru { 42 u-boot,dm-spl; 43 status = "okay"; 44}; 45 46&mdio { 47 u-boot,dm-spl; 48 status = "okay"; 49}; 50 51&rmii_phy { 52 u-boot,dm-spl; 53 status = "okay"; 54}; 55 56&sdmmc { 57 u-boot,dm-spl; 58 status = "okay"; 59}; 60 61&crypto { 62 u-boot,dm-spl; 63 clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 64 clock-frequency = <300000000>, <300000000>; 65 status = "okay"; 66}; 67 68&rng { 69 u-boot,dm-spl; 70 status = "okay"; 71}; 72 73&saradc { 74 u-boot,dm-pre-reloc; 75 status = "okay"; 76}; 77 78&sfc { 79 u-boot,dm-spl; 80 status = "okay"; 81 82 #address-cells = <1>; 83 #size-cells = <0>; 84 spi_nand: flash@0 { 85 u-boot,dm-spl; 86 compatible = "spi-nand"; 87 reg = <0>; 88 spi-tx-bus-width = <1>; 89 spi-rx-bus-width = <4>; 90 spi-max-frequency = <80000000>; 91 }; 92 93 spi_nor: flash@1 { 94 u-boot,dm-spl; 95 compatible = "jedec,spi-nor"; 96 label = "sfc_nor"; 97 reg = <0>; 98 spi-tx-bus-width = <1>; 99 spi-rx-bus-width = <4>; 100 spi-max-frequency = <100000000>; 101 }; 102}; 103