1/* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc1 = &sdmmc; 10 mmc0 = &emmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc; 16 }; 17}; 18 19 20&emmc { 21 mmc-ecsd = <0x0020f000>; 22 u-boot,dm-spl; 23 status = "okay"; 24}; 25 26&cru { 27 u-boot,dm-spl; 28 status = "okay"; 29}; 30 31&gmac { 32 u-boot,dm-spl; 33 status = "okay"; 34}; 35 36&grf { 37 u-boot,dm-spl; 38 status = "okay"; 39}; 40 41&mdio { 42 u-boot,dm-spl; 43 status = "okay"; 44}; 45 46&rmii_phy { 47 u-boot,dm-spl; 48 status = "okay"; 49}; 50 51&sdmmc { 52 u-boot,dm-spl; 53 status = "okay"; 54}; 55 56&saradc { 57 u-boot,dm-pre-reloc; 58 status = "okay"; 59}; 60 61&sfc { 62 u-boot,dm-spl; 63 status = "okay"; 64 65 #address-cells = <1>; 66 #size-cells = <0>; 67 spi_nand: flash@0 { 68 u-boot,dm-spl; 69 compatible = "spi-nand"; 70 reg = <0>; 71 spi-tx-bus-width = <1>; 72 spi-rx-bus-width = <4>; 73 spi-max-frequency = <80000000>; 74 }; 75 76 spi_nor: flash@1 { 77 u-boot,dm-spl; 78 compatible = "jedec,spi-nor"; 79 label = "sfc_nor"; 80 reg = <0>; 81 spi-tx-bus-width = <1>; 82 spi-rx-bus-width = <4>; 83 spi-max-frequency = <100000000>; 84 }; 85}; 86