xref: /rk3399_rockchip-uboot/arch/arm/dts/rv1106-u-boot.dtsi (revision 11b25801bd4e56894e87abd893d0b2c620bc8e17) 
1/*
2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		mmc1 = &sdmmc;
10		mmc0 = &emmc;
11	};
12
13	chosen {
14		stdout-path = &uart2;
15		u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc;
16	};
17
18	secure-otp@ff3fd8000 {
19		compatible = "rockchip,rv1106-secure-otp";
20		reg = <0xff3d8000 0x4000>;
21		secure_conf = <0xff07a018>;
22		cru_rst_addr = <0xff3bca08>;
23		mask_addr = <0xff3dc000>;
24		u-boot,dm-spl;
25		status = "okay";
26	};
27};
28
29&emmc {
30	mmc-ecsd = <0x3F000>;
31	bus-width = <8>;
32	mmc-hs200-1_8v;
33	u-boot,dm-spl;
34	status = "okay";
35};
36
37&cru {
38	u-boot,dm-spl;
39	status = "okay";
40};
41
42&gmac {
43	u-boot,dm-spl;
44	status = "okay";
45};
46
47&grf {
48	u-boot,dm-spl;
49	status = "okay";
50};
51
52&grf_cru {
53	u-boot,dm-spl;
54	status = "okay";
55};
56
57&mdio {
58	u-boot,dm-spl;
59	status = "okay";
60};
61
62&rmii_phy {
63	u-boot,dm-spl;
64	status = "okay";
65};
66
67&sdmmc {
68	u-boot,dm-spl;
69	pwr-en-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
70	status = "okay";
71};
72
73&sdmmc0 {
74	u-boot,dm-spl;
75};
76
77&sdmmc0_bus4 {
78	u-boot,dm-spl;
79};
80
81&sdmmc0_clk {
82	u-boot,dm-spl;
83};
84
85&sdmmc0_cmd {
86	u-boot,dm-spl;
87};
88
89&sdmmc0_det {
90	u-boot,dm-spl;
91};
92
93&sdmmc0_idle_pins {
94	u-boot,dm-spl;
95};
96
97&sdmmc1m1_idle_pins {
98	u-boot,dm-spl;
99};
100
101&pinctrl {
102	u-boot,dm-spl;
103	status = "okay";
104};
105
106&ioc {
107	u-boot,dm-spl;
108	status = "okay";
109};
110
111&pmuioc {
112	u-boot,dm-spl;
113	status = "okay";
114};
115
116&pcfg_pull_up_drv_level_2 {
117	u-boot,dm-spl;
118};
119
120&pcfg_pull_up {
121	u-boot,dm-spl;
122};
123
124&pcfg_pull_down{
125	u-boot,dm-spl;
126};
127
128&gpio0 {
129	u-boot,dm-spl;
130	status = "okay";
131};
132
133&gpio1 {
134	u-boot,dm-pre-reloc;
135	status = "okay";
136};
137
138&gpio2 {
139	u-boot,dm-pre-reloc;
140	status = "okay";
141};
142
143&gpio3 {
144	u-boot,dm-spl;
145	status = "okay";
146};
147
148&gpio4 {
149	u-boot,dm-pre-reloc;
150	status = "okay";
151};
152
153&crypto {
154	u-boot,dm-spl;
155	clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
156	clock-frequency = <300000000>, <300000000>;
157	status = "okay";
158};
159
160&rng {
161	u-boot,dm-spl;
162	status = "okay";
163};
164
165&saradc {
166	u-boot,dm-pre-reloc;
167	status = "okay";
168};
169
170&sfc {
171	u-boot,dm-spl;
172	status = "okay";
173
174	#address-cells = <1>;
175	#size-cells = <0>;
176	spi_nand: flash@0 {
177		u-boot,dm-spl;
178		compatible = "spi-nand";
179		reg = <0>;
180		spi-tx-bus-width = <1>;
181		spi-rx-bus-width = <4>;
182		spi-max-frequency = <80000000>;
183	};
184
185	spi_nor: flash@1 {
186		u-boot,dm-spl;
187		compatible = "jedec,spi-nor";
188		label = "sfc_nor";
189		reg = <0>;
190		spi-tx-bus-width = <1>;
191		spi-rx-bus-width = <4>;
192		spi-max-frequency = <100000000>;
193	};
194};
195
196&u2phy {
197	u-boot,dm-pre-reloc;
198	status = "okay";
199};
200
201&u2phy_otg {
202	u-boot,dm-pre-reloc;
203	status = "okay";
204};
205