1/* 2 * (C) Copyright 2024 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 / { 8 aliases { 9 mmc1 = &sdmmc0; 10 mmc0 = &emmc; 11 }; 12 13 chosen { 14 stdout-path = &uart0; 15 u-boot,spl-boot-order = &sdmmc0, &spi_nand, &spi_nor, &emmc; 16 }; 17}; 18 19&emmc { 20 u-boot,dm-spl; 21 status = "okay"; 22}; 23 24&cru { 25 u-boot,dm-spl; 26 status = "okay"; 27}; 28 29&grf { 30 u-boot,dm-spl; 31 status = "okay"; 32}; 33 34&pinctrl { 35 u-boot,dm-spl; 36 status = "okay"; 37}; 38 39&sdmmc0 { 40 u-boot,dm-spl; 41 pwr-en-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 42 pinctrl-names = "default", "idle"; 43 pinctrl-0 = <&sdmmc0_clk_pins &sdmmc0_cmd_pins &sdmmc0_det_pins &sdmmc0_bus4_pins>; 44 status = "okay"; 45}; 46 47&sdmmc0_pins { 48 u-boot,dm-spl; 49}; 50 51&sdmmc0_clk_pins { 52 u-boot,dm-spl; 53}; 54 55&sdmmc0_cmd_pins { 56 u-boot,dm-spl; 57}; 58 59&sdmmc0_det_pins { 60 u-boot,dm-spl; 61}; 62 63&sdmmc0_bus4_pins { 64 u-boot,dm-spl; 65}; 66 67&ioc { 68 u-boot,dm-spl; 69 status = "okay"; 70}; 71 72&pcfg_pull_up_drv_level_2 { 73 u-boot,dm-spl; 74}; 75 76&pcfg_pull_up { 77 u-boot,dm-spl; 78}; 79 80&gpio0 { 81 u-boot,dm-spl; 82 status = "okay"; 83}; 84 85&gpio1 { 86 u-boot,dm-pre-reloc; 87 status = "okay"; 88}; 89 90&gpio2 { 91 u-boot,dm-pre-reloc; 92 status = "okay"; 93}; 94 95 96&crypto { 97 u-boot,dm-spl; 98 status = "okay"; 99}; 100 101&rng { 102 u-boot,dm-spl; 103 status = "okay"; 104}; 105 106&saradc { 107 u-boot,dm-pre-reloc; 108 status = "okay"; 109}; 110 111&sfc { 112 u-boot,dm-spl; 113 status = "okay"; 114 115 #address-cells = <1>; 116 #size-cells = <0>; 117 spi_nand: flash@0 { 118 u-boot,dm-spl; 119 compatible = "spi-nand"; 120 reg = <0>; 121 spi-tx-bus-width = <1>; 122 spi-rx-bus-width = <4>; 123 spi-max-frequency = <80000000>; 124 }; 125 126 spi_nor: flash@1 { 127 u-boot,dm-spl; 128 compatible = "jedec,spi-nor"; 129 label = "sfc_nor"; 130 reg = <0>; 131 spi-tx-bus-width = <1>; 132 spi-rx-bus-width = <4>; 133 spi-max-frequency = <80000000>; 134 }; 135}; 136