1/* 2 * (C) Copyright 2024 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 / { 8 aliases { 9 mmc1 = &sdmmc0; 10 mmc0 = &emmc; 11 }; 12 13 chosen { 14 stdout-path = &uart0; 15 u-boot,spl-boot-order = &sdmmc0, &spi_nand, &spi_nor, &emmc; 16 }; 17}; 18 19&hw_decompress { 20 u-boot,dm-spl; 21 status = "okay"; 22}; 23 24&emmc { 25 u-boot,dm-spl; 26 status = "okay"; 27}; 28 29&cru { 30 u-boot,dm-spl; 31 status = "okay"; 32}; 33 34&grf { 35 u-boot,dm-spl; 36 status = "okay"; 37}; 38 39&pinctrl { 40 u-boot,dm-spl; 41 status = "okay"; 42}; 43 44&sdmmc0 { 45 u-boot,dm-spl; 46 pinctrl-names = "default", "idle"; 47 pinctrl-0 = <&sdmmc0_clk_pins &sdmmc0_cmd_pins &sdmmc0_det_pins &sdmmc0_bus4_pins>; 48 status = "okay"; 49}; 50 51&sdmmc0_pins { 52 u-boot,dm-spl; 53}; 54 55&sdmmc0_clk_pins { 56 u-boot,dm-spl; 57}; 58 59&sdmmc0_cmd_pins { 60 u-boot,dm-spl; 61}; 62 63&sdmmc0_det_pins { 64 u-boot,dm-spl; 65}; 66 67&sdmmc0_bus4_pins { 68 u-boot,dm-spl; 69}; 70 71&ioc { 72 u-boot,dm-spl; 73 status = "okay"; 74}; 75 76&pcfg_pull_up_drv_level_2 { 77 u-boot,dm-spl; 78}; 79 80&pcfg_pull_up { 81 u-boot,dm-spl; 82}; 83 84&gpio0 { 85 u-boot,dm-spl; 86 status = "okay"; 87}; 88 89&gpio1 { 90 u-boot,dm-pre-reloc; 91 status = "okay"; 92}; 93 94&gpio2 { 95 u-boot,dm-pre-reloc; 96 status = "okay"; 97}; 98 99 100&crypto { 101 u-boot,dm-spl; 102 status = "okay"; 103}; 104 105&rng { 106 u-boot,dm-spl; 107 status = "okay"; 108}; 109 110&saradc { 111 u-boot,dm-pre-reloc; 112 status = "okay"; 113}; 114 115&sfc { 116 u-boot,dm-spl; 117 status = "okay"; 118 119 #address-cells = <1>; 120 #size-cells = <0>; 121 spi_nand: flash@0 { 122 u-boot,dm-spl; 123 compatible = "spi-nand"; 124 reg = <0>; 125 spi-tx-bus-width = <1>; 126 spi-rx-bus-width = <4>; 127 spi-max-frequency = <80000000>; 128 }; 129 130 spi_nor: flash@1 { 131 u-boot,dm-spl; 132 compatible = "jedec,spi-nor"; 133 label = "sfc_nor"; 134 reg = <0>; 135 spi-tx-bus-width = <1>; 136 spi-rx-bus-width = <4>; 137 spi-max-frequency = <80000000>; 138 }; 139}; 140