1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rk3588-power.h> 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 compatible = "rockchip,rk3588"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 ethernet1 = &gmac1; 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 i2c4 = &i2c4; 27 i2c5 = &i2c5; 28 i2c6 = &i2c6; 29 i2c7 = &i2c7; 30 i2c8 = &i2c8; 31 serial0 = &uart0; 32 serial1 = &uart1; 33 serial2 = &uart2; 34 serial3 = &uart3; 35 serial4 = &uart4; 36 serial5 = &uart5; 37 serial6 = &uart6; 38 serial7 = &uart7; 39 serial8 = &uart8; 40 serial9 = &uart9; 41 spi0 = &spi0; 42 spi1 = &spi1; 43 spi2 = &spi2; 44 spi3 = &spi3; 45 spi4 = &spi4; 46 spi5 = &sfc; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu-map { 54 cluster0 { 55 core0 { 56 cpu = <&cpu_l0>; 57 }; 58 core1 { 59 cpu = <&cpu_l1>; 60 }; 61 core2 { 62 cpu = <&cpu_l2>; 63 }; 64 core3 { 65 cpu = <&cpu_l3>; 66 }; 67 }; 68 cluster1 { 69 core0 { 70 cpu = <&cpu_b0>; 71 }; 72 core1 { 73 cpu = <&cpu_b1>; 74 }; 75 }; 76 cluster2 { 77 core0 { 78 cpu = <&cpu_b2>; 79 }; 80 core1 { 81 cpu = <&cpu_b3>; 82 }; 83 }; 84 }; 85 86 cpu_l0: cpu@0 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a55"; 89 reg = <0x0>; 90 enable-method = "psci"; 91 capacity-dmips-mhz = <530>; 92 }; 93 94 cpu_l1: cpu@100 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a55"; 97 reg = <0x100>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <530>; 100 }; 101 102 cpu_l2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a55"; 105 reg = <0x200>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <530>; 108 }; 109 110 cpu_l3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 capacity-dmips-mhz = <530>; 116 }; 117 118 cpu_b0: cpu@400 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a76"; 121 reg = <0x400>; 122 enable-method = "psci"; 123 capacity-dmips-mhz = <1024>; 124 }; 125 126 cpu_b1: cpu@500 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a76"; 129 reg = <0x500>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <1024>; 132 }; 133 134 cpu_b2: cpu@600 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a76"; 137 reg = <0x600>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 }; 141 142 cpu_b3: cpu@700 { 143 device_type = "cpu"; 144 compatible = "arm,cortex-a76"; 145 reg = <0x700>; 146 enable-method = "psci"; 147 capacity-dmips-mhz = <1024>; 148 }; 149 }; 150 151 arm_pmu: arm-pmu { 152 compatible = "arm,armv8-pmuv3"; 153 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_LOW>; 154 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>, 155 <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 156 }; 157 158 firmware: firmware { 159 optee: optee { 160 compatible = "linaro,optee-tz"; 161 method = "smc"; 162 }; 163 164 scmi: scmi { 165 compatible = "arm,scmi-smc"; 166 shmem = <&scmi_shmem>; 167 arm,smc-id = <0x82000010>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 scmi_clk: protocol@14 { 172 reg = <0x14>; 173 #clock-cells = <1>; 174 175 assigned-clocks = <&scmi_clk SCMI_SPLL>; 176 assigned-clock-rates = <700000000>; 177 }; 178 179 scmi_reset: protocol@16 { 180 reg = <0x16>; 181 #reset-cells = <1>; 182 }; 183 }; 184 185 sdei: sdei { 186 compatible = "arm,sdei-1.0"; 187 method = "smc"; 188 }; 189 }; 190 191 psci: psci { 192 compatible = "arm,psci-1.0"; 193 method = "smc"; 194 }; 195 196 spll: spll { 197 compatible = "fixed-clock"; 198 #clock-cells = <0>; 199 clock-frequency = <702000000>; 200 clock-output-names = "spll"; 201 }; 202 203 timer { 204 compatible = "arm,armv8-timer"; 205 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 207 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 209 }; 210 211 xin32k: xin32k { 212 compatible = "fixed-clock"; 213 #clock-cells = <0>; 214 clock-frequency = <32768>; 215 clock-output-names = "xin32k"; 216 }; 217 218 xin24m: xin24m { 219 compatible = "fixed-clock"; 220 #clock-cells = <0>; 221 clock-frequency = <24000000>; 222 clock-output-names = "xin24m"; 223 }; 224 225 sram: sram@10f000 { 226 compatible = "mmio-sram"; 227 reg = <0x0 0x0010f000 0x0 0x100>; 228 #address-cells = <1>; 229 #size-cells = <1>; 230 ranges = <0 0x0 0x0010f000 0x100>; 231 232 scmi_shmem: scmi_shmem@0 { 233 compatible = "arm,scmi-shmem"; 234 reg = <0x0 0x100>; 235 }; 236 }; 237 238 usbdrd3_0: usbdrd3_0 { 239 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 240 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 241 <&cru ACLK_USB3OTG0>; 242 clock-names = "ref", "suspend", "bus"; 243 #address-cells = <2>; 244 #size-cells = <2>; 245 ranges; 246 status = "disabled"; 247 248 usbdrd_dwc3_0: usb@fc000000 { 249 compatible = "snps,dwc3"; 250 reg = <0x0 0xfc000000 0x0 0x400000>; 251 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 252 power-domains = <&power RK3588_PD_USB>; 253 resets = <&cru SRST_A_USB3OTG0>; 254 reset-names = "usb3-otg"; 255 dr_mode = "otg"; 256 phy_type = "utmi_wide"; 257 snps,dis_enblslpm_quirk; 258 snps,dis-u1-entry-quirk; 259 snps,dis-u2-entry-quirk; 260 snps,dis-u2-freeclk-exists-quirk; 261 snps,dis-del-phy-power-chg-quirk; 262 snps,dis-tx-ipgap-linecheck-quirk; 263 status = "disabled"; 264 }; 265 }; 266 267 usb_host0_ehci: usb@fc800000 { 268 compatible = "generic-ehci"; 269 reg = <0x0 0xfc800000 0x0 0x40000>; 270 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; 272 clock-names = "usbhost", "arbiter"; 273 power-domains = <&power RK3588_PD_USB>; 274 status = "disabled"; 275 }; 276 277 usb_host0_ohci: usb@fc840000 { 278 compatible = "generic-ohci"; 279 reg = <0x0 0xfc840000 0x0 0x40000>; 280 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; 282 clock-names = "usbhost", "arbiter"; 283 power-domains = <&power RK3588_PD_USB>; 284 status = "disabled"; 285 }; 286 287 usb_host1_ehci: usb@fc880000 { 288 compatible = "generic-ehci"; 289 reg = <0x0 0xfc880000 0x0 0x40000>; 290 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; 292 clock-names = "usbhost", "arbiter"; 293 power-domains = <&power RK3588_PD_USB>; 294 status = "disabled"; 295 }; 296 297 usb_host1_ohci: usb@fc8c0000 { 298 compatible = "generic-ohci"; 299 reg = <0x0 0xfc8c0000 0x0 0x40000>; 300 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; 302 clock-names = "usbhost", "arbiter"; 303 power-domains = <&power RK3588_PD_USB>; 304 status = "disabled"; 305 }; 306 307 mmu600_pcie: iommu@fc900000 { 308 compatible = "arm,smmu-v3"; 309 reg = <0x0 0xfc900000 0x0 0x200000>; 310 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 315 #iommu-cells = <1>; 316 status = "disabled"; 317 }; 318 319 mmu600_php: iommu@fcb00000 { 320 compatible = "arm,smmu-v3"; 321 reg = <0x0 0xfcb00000 0x0 0x200000>; 322 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 326 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 327 #iommu-cells = <1>; 328 status = "disabled"; 329 }; 330 331 usbhost3_0: usbhost3_0 { 332 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 333 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 334 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>; 335 clock-names = "ref", "suspend", "bus", "utmi"; 336 #address-cells = <2>; 337 #size-cells = <2>; 338 ranges; 339 status = "disabled"; 340 341 usbhost_dwc3_0: usb@fcd00000 { 342 compatible = "snps,dwc3"; 343 reg = <0x0 0xfcd00000 0x0 0x400000>; 344 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 345 power-domains = <&power RK3588_PD_PHP>; 346 resets = <&cru SRST_A_USB3OTG2>; 347 reset-names = "usb3-host"; 348 dr_mode = "host"; 349 phy_type = "utmi_wide"; 350 snps,dis_enblslpm_quirk; 351 snps,dis-u2-freeclk-exists-quirk; 352 snps,dis-del-phy-power-chg-quirk; 353 snps,dis-tx-ipgap-linecheck-quirk; 354 status = "disabled"; 355 }; 356 }; 357 358 sys_grf: syscon@fd58c000 { 359 compatible = "rockchip,rk3588-sys-grf", "syscon"; 360 reg = <0x0 0xfd58c000 0x0 0x1000>; 361 }; 362 363 vo0_grf: syscon@fd5a6000 { 364 compatible = "rockchip,rk3588-vo-grf", "syscon"; 365 reg = <0x0 0xfd5a6000 0x0 0x2000>; 366 }; 367 368 vo1_grf: syscon@fd5a8000 { 369 compatible = "rockchip,rk3588-vo-grf", "syscon"; 370 reg = <0x0 0xfd5a8000 0x0 0x100>; 371 }; 372 373 usb_grf: syscon@fd5ac000 { 374 compatible = "rockchip,rk3588-usb-grf", "syscon"; 375 reg = <0x0 0xfd5ac000 0x0 0x4000>; 376 }; 377 378 php_grf: syscon@fd5b0000 { 379 compatible = "rockchip,rk3588-php-grf", "syscon"; 380 reg = <0x0 0xfd5b0000 0x0 0x1000>; 381 }; 382 383 pipe_phy0_grf: syscon@fd5bc000 { 384 compatible = "rockchip,pipe-phy-grf", "syscon"; 385 reg = <0x0 0xfd5bc000 0x0 0x100>; 386 }; 387 388 pipe_phy2_grf: syscon@fd5c4000 { 389 compatible = "rockchip,pipe-phy-grf", "syscon"; 390 reg = <0x0 0xfd5c4000 0x0 0x100>; 391 }; 392 393 usbdpphy0_grf: syscon@fd5c8000 { 394 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 395 reg = <0x0 0xfd5c8000 0x0 0x4000>; 396 }; 397 398 usb2phy0_grf: syscon@fd5d0000 { 399 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 400 "simple-mfd"; 401 reg = <0x0 0xfd5d0000 0x0 0x4000>; 402 #address-cells = <1>; 403 #size-cells = <1>; 404 405 u2phy0: usb2-phy@0 { 406 compatible = "rockchip,rk3588-usb2phy"; 407 reg = <0x0 0x10>; 408 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 410 clock-names = "phyclk"; 411 #clock-cells = <0>; 412 status = "disabled"; 413 414 u2phy0_otg: otg-port { 415 #phy-cells = <0>; 416 status = "disabled"; 417 }; 418 }; 419 }; 420 421 usb2phy2_grf: syscon@fd5d8000 { 422 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 423 "simple-mfd"; 424 reg = <0x0 0xfd5d8000 0x0 0x4000>; 425 #address-cells = <1>; 426 #size-cells = <1>; 427 428 u2phy2: usb2-phy@8000 { 429 compatible = "rockchip,rk3588-usb2phy"; 430 reg = <0x8000 0x10>; 431 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 433 clock-names = "phyclk"; 434 #clock-cells = <0>; 435 status = "disabled"; 436 437 u2phy2_host: host-port { 438 #phy-cells = <0>; 439 status = "disabled"; 440 }; 441 }; 442 }; 443 444 usb2phy3_grf: syscon@fd5dc000 { 445 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 446 "simple-mfd"; 447 reg = <0x0 0xfd5dc000 0x0 0x4000>; 448 #address-cells = <1>; 449 #size-cells = <1>; 450 451 u2phy3: usb2-phy@c000 { 452 compatible = "rockchip,rk3588-usb2phy"; 453 reg = <0xc000 0x10>; 454 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 456 clock-names = "phyclk"; 457 #clock-cells = <0>; 458 status = "disabled"; 459 460 u2phy3_host: host-port { 461 #phy-cells = <0>; 462 status = "disabled"; 463 }; 464 }; 465 }; 466 467 hdptxphy0_grf: syscon@fd5e0000 { 468 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 469 reg = <0x0 0xfd5e0000 0x0 0x100>; 470 }; 471 472 ioc: syscon@fd5f0000 { 473 compatible = "rockchip,rk3588-ioc", "syscon"; 474 reg = <0x0 0xfd5f0000 0x0 0x10000>; 475 }; 476 477 syssram: sram@fd600000 { 478 compatible = "mmio-sram"; 479 reg = <0x0 0xfd600000 0x0 0x100000>; 480 481 #address-cells = <1>; 482 #size-cells = <1>; 483 ranges = <0x0 0x0 0xfd600000 0x100000>; 484 }; 485 486 cru: clock-controller@fd7c0000 { 487 compatible = "rockchip,rk3588-cru"; 488 rockchip,grf = <&php_grf>; 489 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 490 #clock-cells = <1>; 491 #reset-cells = <1>; 492 493 assigned-clocks = 494 <&cru PLL_PPLL>, <&cru PLL_CPLL>, 495 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 496 <&cru ARMCLK_L>, <&cru ARMCLK_B01>, 497 <&cru ACLK_CENTER_ROOT>, <&cru PCLK_CENTER_ROOT>, 498 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 499 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 500 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 501 <&cru HCLK_PMU_CM0_ROOT>; 502 assigned-clock-rates = 503 <100000000>, <1500000000>, 504 <850000000>, <1188000000>, 505 <816000000>, <1008000000>, 506 <600000000>, <200000000>, 507 <400000000>, <500000000>, 508 <800000000>, <100000000>, 509 <400000000>, <100000000>, 510 <200000000>; 511 }; 512 513 i2c0: i2c@fd880000 { 514 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 515 reg = <0x0 0xfd880000 0x0 0x1000>; 516 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 517 clock-names = "i2c", "pclk"; 518 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 519 pinctrl-names = "default"; 520 pinctrl-0 = <&i2c0m0_xfer>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 status = "disabled"; 524 }; 525 526 uart0: serial@fd890000 { 527 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 528 reg = <0x0 0xfd890000 0x0 0x100>; 529 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 531 clock-names = "baudclk", "apb_pclk"; 532 reg-shift = <2>; 533 reg-io-width = <4>; 534 dmas = <&dmac0 6>, <&dmac0 7>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&uart0m0_xfer>; 537 status = "disabled"; 538 }; 539 540 pwm0: pwm@fd8b0000 { 541 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 542 reg = <0x0 0xfd8b0000 0x0 0x10>; 543 #pwm-cells = <3>; 544 pinctrl-names = "active"; 545 pinctrl-0 = <&pwm0m0_pins>; 546 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 547 clock-names = "pwm", "pclk"; 548 status = "disabled"; 549 }; 550 551 pwm1: pwm@fd8b0010 { 552 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 553 reg = <0x0 0xfd8b0010 0x0 0x10>; 554 #pwm-cells = <3>; 555 pinctrl-names = "active"; 556 pinctrl-0 = <&pwm1m0_pins>; 557 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 558 clock-names = "pwm", "pclk"; 559 status = "disabled"; 560 }; 561 562 pwm2: pwm@fd8b0020 { 563 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 564 reg = <0x0 0xfd8b0020 0x0 0x10>; 565 #pwm-cells = <3>; 566 pinctrl-names = "active"; 567 pinctrl-0 = <&pwm2m0_pins>; 568 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 569 clock-names = "pwm", "pclk"; 570 status = "disabled"; 571 }; 572 573 pwm3: pwm@fd8b0030 { 574 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 575 reg = <0x0 0xfd8b0030 0x0 0x10>; 576 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 578 #pwm-cells = <3>; 579 pinctrl-names = "active"; 580 pinctrl-0 = <&pwm3m0_pins>; 581 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 582 clock-names = "pwm", "pclk"; 583 status = "disabled"; 584 }; 585 586 pmu: power-management@fd8d8000 { 587 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 588 reg = <0x0 0xfd8d8000 0x0 0x400>; 589 590 power: power-controller { 591 compatible = "rockchip,rk3588-power-controller"; 592 #power-domain-cells = <1>; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 status = "okay"; 596 597 /* These power domains are grouped by VD_NPU */ 598 power-domain@RK3588_PD_NPU { 599 reg = <RK3588_PD_NPU>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 603 power-domain@RK3588_PD_NPUTOP { 604 reg = <RK3588_PD_NPUTOP>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 608 power-domain@RK3588_PD_NPU1 { 609 reg = <RK3588_PD_NPU1>; 610 }; 611 power-domain@RK3588_PD_NPU2 { 612 reg = <RK3588_PD_NPU2>; 613 }; 614 }; 615 }; 616 /* These power domains are grouped by VD_GPU */ 617 power-domain@RK3588_PD_GPU { 618 reg = <RK3588_PD_GPU>; 619 }; 620 /* These power domains are grouped by VD_VCODEC */ 621 power-domain@RK3588_PD_VCODEC { 622 reg = <RK3588_PD_VCODEC>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 626 power-domain@RK3588_PD_RKVDEC0 { 627 reg = <RK3588_PD_RKVDEC0>; 628 }; 629 power-domain@RK3588_PD_RKVDEC1 { 630 reg = <RK3588_PD_RKVDEC1>; 631 }; 632 power-domain@RK3588_PD_VENC0 { 633 reg = <RK3588_PD_VENC0>; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 637 power-domain@RK3588_PD_VENC1 { 638 reg = <RK3588_PD_VENC1>; 639 }; 640 }; 641 }; 642 /* These power domains are grouped by VD_LOGIC */ 643 power-domain@RK3588_PD_VDPU { 644 reg = <RK3588_PD_VDPU>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 648 power-domain@RK3588_PD_RGA30 { 649 reg = <RK3588_PD_RGA30>; 650 }; 651 power-domain@RK3588_PD_av1 { 652 reg = <RK3588_PD_AV1>; 653 }; 654 }; 655 power-domain@RK3588_PD_VOP { 656 reg = <RK3588_PD_VOP>; 657 }; 658 power-domain@RK3588_PD_VO0 { 659 reg = <RK3588_PD_VO0>; 660 }; 661 power-domain@RK3588_PD_VO1 { 662 reg = <RK3588_PD_VO1>; 663 }; 664 power-domain@RK3588_PD_VI { 665 reg = <RK3588_PD_VI>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 669 power-domain@RK3588_PD_ISP1 { 670 reg = <RK3588_PD_ISP1>; 671 }; 672 power-domain@RK3588_PD_FEC { 673 reg = <RK3588_PD_FEC>; 674 }; 675 }; 676 power-domain@RK3588_PD_RGA31 { 677 reg = <RK3588_PD_RGA31>; 678 }; 679 power-domain@RK3588_PD_USB { 680 reg = <RK3588_PD_USB>; 681 }; 682 power-domain@RK3588_PD_PHP { 683 reg = <RK3588_PD_PHP>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 687 power-domain@RK3588_PD_GMAC { 688 reg = <RK3588_PD_GMAC>; 689 }; 690 power-domain@RK3588_PD_PCIE { 691 reg = <RK3588_PD_PCIE>; 692 }; 693 }; 694 power-domain@RK3588_PD_NVM { 695 reg = <RK3588_PD_NVM>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 699 power-domain@RK3588_PD_NVM0 { 700 reg = <RK3588_PD_NVM0>; 701 }; 702 }; 703 power-domain@RK3588_PD_SDIO { 704 reg = <RK3588_PD_SDIO>; 705 }; 706 power-domain@RK3588_PD_AUDIO { 707 reg = <RK3588_PD_AUDIO>; 708 }; 709 power-domain@RK3588_PD_SDMMC { 710 reg = <RK3588_PD_SDMMC>; 711 }; 712 }; 713 }; 714 715 pvtm@fda40000 { 716 compatible = "rockchip,rk3588-bigcore0-pvtm"; 717 reg = <0x0 0xfda40000 0x0 0x100>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 pvtm@0 { 721 reg = <0>; 722 clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>; 723 clock-names = "clk", "pclk"; 724 }; 725 }; 726 727 pvtm@fda50000 { 728 compatible = "rockchip,rk3588-bigcore1-pvtm"; 729 reg = <0x0 0xfda50000 0x0 0x100>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 pvtm@1 { 733 reg = <1>; 734 clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>; 735 clock-names = "clk", "pclk"; 736 }; 737 }; 738 739 pvtm@fda60000 { 740 compatible = "rockchip,rk3588-litcore-pvtm"; 741 reg = <0x0 0xfda60000 0x0 0x100>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 pvtm@2 { 745 reg = <2>; 746 clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>; 747 clock-names = "clk", "pclk"; 748 }; 749 }; 750 751 pvtm@fdaf0000 { 752 compatible = "rockchip,rk3588-npu-pvtm"; 753 reg = <0x0 0xfdaf0000 0x0 0x100>; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 pvtm@3 { 757 reg = <3>; 758 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>; 759 clock-names = "clk", "pclk"; 760 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; 761 reset-names = "rts", "rst-p"; 762 }; 763 }; 764 765 pvtm@fdb30000 { 766 compatible = "rockchip,rk3588-gpu-pvtm"; 767 reg = <0x0 0xfdb30000 0x0 0x100>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 pvtm@4 { 771 reg = <4>; 772 clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>; 773 clock-names = "clk", "pclk"; 774 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; 775 reset-names = "rts", "rst-p"; 776 }; 777 }; 778 779 npu0_mmu: iommu@fdab9000 { 780 compatible = "rockchip,iommu-v2"; 781 reg = <0x0 0xfdab9000 0x0 0x100>, <0x0 0xfdaba000 0x0 0x100>; 782 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 783 interrupt-names = "npu0_mmu"; 784 clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>; 785 clock-names = "aclk", "iface"; 786 power-domains = <&power RK3588_PD_NPUTOP>; 787 #iommu-cells = <0>; 788 status = "disabled"; 789 }; 790 791 npu1_mmu: iommu@fdaca000 { 792 compatible = "rockchip,iommu-v2"; 793 reg = <0x0 0xfdaca000 0x0 0x100>; 794 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 795 interrupt-names = "npu1_mmu"; 796 clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>; 797 clock-names = "aclk", "iface"; 798 power-domains = <&power RK3588_PD_NPU1>; 799 #iommu-cells = <0>; 800 status = "disabled"; 801 }; 802 803 npu2_mmu: iommu@fdada000 { 804 compatible = "rockchip,iommu-v2"; 805 reg = <0x0 0xfdada000 0x0 0x100>; 806 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 807 interrupt-names = "npu2_mmu"; 808 clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>; 809 clock-names = "aclk", "iface"; 810 power-domains = <&power RK3588_PD_NPU2>; 811 #iommu-cells = <0>; 812 status = "disabled"; 813 }; 814 815 vdpu_mmu: iommu@fdb50800 { 816 compatible = "rockchip,iommu-v2"; 817 reg = <0x0 0xfdb50800 0x0 0x40>; 818 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 819 interrupt-names = "irq_vdpu_mmu"; 820 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 821 clock-names = "aclk", "iface"; 822 power-domains = <&power RK3588_PD_VDPU>; 823 #iommu-cells = <0>; 824 status = "disabled"; 825 }; 826 827 rga3_0_mmu: iommu@fdb60f00 { 828 compatible = "rockchip,iommu-v2"; 829 reg = <0x0 0xfdb60f00 0x0 0x100>; 830 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 831 interrupt-names = "rga3_0_mmu"; 832 clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; 833 clock-names = "aclk", "iface"; 834 power-domains = <&power RK3588_PD_RGA30>; 835 #iommu-cells = <0>; 836 status = "disabled"; 837 }; 838 839 rga3_1_mmu: iommu@fdb70f00 { 840 compatible = "rockchip,iommu-v2"; 841 reg = <0x0 0xfdb70f00 0x0 0x100>; 842 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 843 interrupt-names = "rga3_1_mmu"; 844 clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; 845 clock-names = "aclk", "iface"; 846 power-domains = <&power RK3588_PD_RGA31>; 847 #iommu-cells = <0>; 848 status = "disabled"; 849 }; 850 851 jpegd_mmu: iommu@fdb90480 { 852 compatible = "rockchip,iommu-v2"; 853 reg = <0x0 0xfdb90480 0x0 0x40>; 854 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 855 interrupt-names = "irq_jpegd_mmu"; 856 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 857 clock-names = "aclk", "iface"; 858 power-domains = <&power RK3588_PD_VDPU>; 859 #iommu-cells = <0>; 860 status = "disabled"; 861 }; 862 863 jpege0_mmu: iommu@fdba0800 { 864 compatible = "rockchip,iommu-v2"; 865 reg = <0x0 0xfdba0800 0x0 0x40>; 866 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 867 interrupt-names = "irq_jpege0_mmu"; 868 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 869 clock-names = "aclk", "iface"; 870 power-domains = <&power RK3588_PD_VDPU>; 871 #iommu-cells = <0>; 872 status = "disabled"; 873 }; 874 875 jpege1_mmu: iommu@fdba4800 { 876 compatible = "rockchip,iommu-v2"; 877 reg = <0x0 0xfdba4800 0x0 0x40>; 878 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 879 interrupt-names = "irq_jpege1_mmu"; 880 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 881 clock-names = "aclk", "iface"; 882 power-domains = <&power RK3588_PD_VDPU>; 883 #iommu-cells = <0>; 884 status = "disabled"; 885 }; 886 887 jpege2_mmu: iommu@fdba8800 { 888 compatible = "rockchip,iommu-v2"; 889 reg = <0x0 0xfdba8800 0x0 0x40>; 890 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 891 interrupt-names = "irq_jpege2_mmu"; 892 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 893 clock-names = "aclk", "iface"; 894 power-domains = <&power RK3588_PD_VDPU>; 895 #iommu-cells = <0>; 896 status = "disabled"; 897 }; 898 899 jpege3_mmu: iommu@fdbac800 { 900 compatible = "rockchip,iommu-v2"; 901 reg = <0x0 0xfdbac800 0x0 0x40>; 902 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 903 interrupt-names = "irq_jpege3_mmu"; 904 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 905 clock-names = "aclk", "iface"; 906 power-domains = <&power RK3588_PD_VDPU>; 907 #iommu-cells = <0>; 908 status = "disabled"; 909 }; 910 911 iep_mmu: iommu@fdbb0800 { 912 compatible = "rockchip,iommu-v2"; 913 reg = <0x0 0xfdbb0800 0x0 0x100>; 914 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "irq_iep_mmu"; 916 clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>; 917 clock-names = "aclk", "iface"; 918 #iommu-cells = <0>; 919 power-domains = <&power RK3588_PD_VDPU>; 920 status = "disabled"; 921 }; 922 923 rkvenc0_mmu: iommu@fdbdf000 { 924 compatible = "rockchip,iommu-v2"; 925 reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>; 926 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 928 interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1"; 929 clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>; 930 clock-names = "aclk", "iface"; 931 rockchip,disable-mmu-reset; 932 rockchip,enable-cmd-retry; 933 #iommu-cells = <0>; 934 power-domains = <&power RK3588_PD_VENC0>; 935 status = "disabled"; 936 }; 937 938 rkvenc1_mmu: iommu@fdbef000 { 939 compatible = "rockchip,iommu-v2"; 940 reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>; 941 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 943 interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1"; 944 clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>; 945 lock-names = "aclk", "iface"; 946 rockchip,disable-mmu-reset; 947 rockchip,enable-cmd-retry; 948 #iommu-cells = <0>; 949 power-domains = <&power RK3588_PD_VENC1>; 950 status = "disabled"; 951 }; 952 953 rkvdec0_mmu: iommu@fdc38700 { 954 compatible = "rockchip,iommu-v2"; 955 reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; 956 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 957 interrupt-names = "irq_rkvdec0_mmu"; 958 locks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; 959 clock-names = "aclk", "iface"; 960 rockchip,disable-mmu-reset; 961 rockchip,enable-cmd-retry; 962 #iommu-cells = <0>; 963 power-domains = <&power RK3588_PD_RKVDEC0>; 964 status = "disabled"; 965 }; 966 967 rkvdec1_mmu: iommu@fdc48700 { 968 compatible = "rockchip,iommu-v2"; 969 reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>; 970 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 971 interrupt-names = "irq_rkvdec1_mmu"; 972 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; 973 clock-names = "aclk", "iface"; 974 rockchip,disable-mmu-reset; 975 rockchip,enable-cmd-retry; 976 #iommu-cells = <0>; 977 power-domains = <&power RK3588_PD_RKVDEC1>; 978 status = "disabled"; 979 }; 980 981 isp0_mmu: iommu@fdcb7f00 { 982 compatible = "rockchip,iommu-v2"; 983 reg = <0x0 0xfdcb7f00 0x0 0x100>; 984 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 985 interrupt-names = "isp0_mmu"; 986 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; 987 clock-names = "aclk", "iface"; 988 power-domains = <&power RK3588_PD_VI>; 989 #iommu-cells = <0>; 990 rockchip,disable-mmu-reset; 991 status = "disabled"; 992 }; 993 994 isp1_mmu: iommu@fdcc7f00 { 995 compatible = "rockchip,iommu-v2"; 996 reg = <0x0 0xfdcc7f00 0x0 0x100>; 997 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 998 interrupt-names = "isp1_mmu"; 999 clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; 1000 clock-names = "aclk", "iface"; 1001 power-domains = <&power RK3588_PD_ISP1>; 1002 #iommu-cells = <0>; 1003 rockchip,disable-mmu-reset; 1004 status = "disabled"; 1005 }; 1006 1007 fec0_mmu: iommu@fdcd0f00 { 1008 compatible = "rockchip,iommu-v2"; 1009 reg = <0x0 0xfdcd0f00 0x0 0x100>; 1010 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1011 interrupt-names = "fec0_mmu"; 1012 clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>; 1013 clock-names = "aclk", "iface"; 1014 power-domains = <&power RK3588_PD_FEC>; 1015 #iommu-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 fec1_mmu: iommu@fdcd8f00 { 1020 compatible = "rockchip,iommu-v2"; 1021 reg = <0x0 0xfdcd8f00 0x0 0x100>; 1022 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1023 interrupt-names = "fec1_mmu"; 1024 clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>; 1025 clock-names = "aclk", "iface"; 1026 power-domains = <&power RK3588_PD_FEC>; 1027 #iommu-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 vop_mmu: iommu@fdd97e00 { 1032 compatible = "rockchip,iommu-v2"; 1033 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1034 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1035 interrupt-names = "vop_mmu"; 1036 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1037 clock-names = "aclk", "iface"; 1038 #iommu-cells = <0>; 1039 rockchip,disable-device-link-resume; 1040 status = "disabled"; 1041 }; 1042 1043 spdif_tx2: spdif-tx@fddb0000 { 1044 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1045 reg = <0x0 0xfddb0000 0x0 0x1000>; 1046 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1047 dmas = <&dmac1 6>; 1048 dma-names = "tx"; 1049 clock-names = "mclk", "hclk"; 1050 clocks = <&cru MCLK_SPDIF2_DP0>, <&cru HCLK_SPDIF2_DP0>; 1051 #sound-dai-cells = <0>; 1052 status = "disabled"; 1053 }; 1054 1055 i2s4_8ch: i2s@fddc0000 { 1056 compatible = "rockchip,rk3588-i2s-tdm"; 1057 reg = <0x0 0xfddc0000 0x0 0x1000>; 1058 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1060 clock-names = "mclk_tx", "hclk"; 1061 dmas = <&dmac2 0>; 1062 dma-names = "tx"; 1063 resets = <&cru SRST_M_I2S4_8CH_TX>; 1064 reset-names = "tx-m"; 1065 #sound-dai-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 spdif_tx3: spdif-tx@fdde0000 { 1070 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1071 reg = <0x0 0xfdde0000 0x0 0x1000>; 1072 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 1073 dmas = <&dmac1 7>; 1074 dma-names = "tx"; 1075 clock-names = "mclk", "hclk"; 1076 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; 1077 #sound-dai-cells = <0>; 1078 status = "disabled"; 1079 }; 1080 1081 i2s5_8ch: i2s@fddf0000 { 1082 compatible = "rockchip,rk3588-i2s-tdm"; 1083 reg = <0x0 0xfddf0000 0x0 0x1000>; 1084 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1086 clock-names = "mclk_tx", "hclk"; 1087 dmas = <&dmac2 2>; 1088 dma-names = "tx"; 1089 resets = <&cru SRST_M_I2S5_8CH_TX>; 1090 reset-names = "tx-m"; 1091 #sound-dai-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 i2s9_8ch: i2s@fddfc000 { 1096 compatible = "rockchip,rk3588-i2s-tdm"; 1097 reg = <0x0 0xfddfc000 0x0 0x1000>; 1098 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1100 clock-names = "mclk_rx", "hclk"; 1101 dmas = <&dmac2 23>; 1102 dma-names = "rx"; 1103 resets = <&cru SRST_M_I2S9_8CH_RX>; 1104 reset-names = "rx-m"; 1105 #sound-dai-cells = <0>; 1106 status = "disabled"; 1107 }; 1108 1109 spdif_rx0: spdif-rx@fde08000 { 1110 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; 1111 reg = <0x0 0xfde08000 0x0 0x1000>; 1112 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>; 1114 clock-names = "mclk", "hclk"; 1115 dmas = <&dmac0 21>; 1116 dma-names = "rx"; 1117 resets = <&cru SRST_M_SPDIFRX0>; 1118 reset-names = "spdifrx-m"; 1119 #sound-dai-cells = <0>; 1120 status = "disabled"; 1121 }; 1122 1123 edp0: edp@fdec0000 { 1124 compatible = "rockchip,rk3588-edp"; 1125 reg = <0x0 0xfdec0000 0x0 0x1000>; 1126 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, 1128 <&cru CLK_EDP0_200M>; 1129 clock-names = "dp", "pclk", "spdif"; 1130 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; 1131 reset-names = "dp", "apb"; 1132 phys = <&hdptxphy0>; 1133 phy-names = "dp"; 1134 power-domains = <&power RK3588_PD_VO1>; 1135 rockchip,grf = <&vo1_grf>; 1136 status = "disabled"; 1137 }; 1138 1139 pcie2x1l1: pcie@fe180000 { 1140 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 1141 #address-cells = <3>; 1142 #size-cells = <2>; 1143 bus-range = <0x30 0x3f>; 1144 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1145 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1146 <&cru CLK_PCIE_AUX3>; 1147 clock-names = "aclk_mst", "aclk_slv", 1148 "aclk_dbi", "pclk", "aux"; 1149 device_type = "pci"; 1150 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1155 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1156 #interrupt-cells = <1>; 1157 interrupt-map-mask = <0 0 0 7>; 1158 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1159 <0 0 0 2 &pcie2x1l1_intc 1>, 1160 <0 0 0 3 &pcie2x1l1_intc 2>, 1161 <0 0 0 4 &pcie2x1l1_intc 3>; 1162 linux,pci-domain = <3>; 1163 num-ib-windows = <8>; 1164 num-ob-windows = <8>; 1165 max-link-speed = <2>; 1166 msi-map = <0x3000 &its 0x3000 0x1000>; 1167 num-lanes = <1>; 1168 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1169 phy-names = "pcie-phy"; 1170 power-domains = <&power RK3588_PD_PHP>; 1171 ranges = <0x00000800 0x0 0xc0000000 0x9 0xc0000000 0x0 0x100000 1172 0x81000000 0x0 0xc0100000 0x9 0xc0100000 0x0 0x100000 1173 0x83000000 0x0 0xc0200000 0x9 0xc0200000 0x0 0x3fe00000>; 1174 reg = <0xa 0x40c00000 0x0 0x400000>, 1175 <0x0 0xfe180000 0x0 0x10000>; 1176 reg-names = "pcie-dbi", "pcie-apb"; 1177 resets = <&cru SRST_PCIE3_POWER_UP>; 1178 reset-names = "pipe"; 1179 status = "disabled"; 1180 1181 pcie2x1l1_intc: legacy-interrupt-controller { 1182 interrupt-controller; 1183 #address-cells = <0>; 1184 #interrupt-cells = <1>; 1185 interrupt-parent = <&gic>; 1186 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>; 1187 }; 1188 }; 1189 1190 pcie2x1l2: pcie@fe190000 { 1191 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 1192 #address-cells = <3>; 1193 #size-cells = <2>; 1194 bus-range = <0x40 0x4f>; 1195 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1196 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1197 <&cru CLK_PCIE_AUX4>; 1198 clock-names = "aclk_mst", "aclk_slv", 1199 "aclk_dbi", "pclk", "aux"; 1200 device_type = "pci"; 1201 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1206 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1207 #interrupt-cells = <1>; 1208 interrupt-map-mask = <0 0 0 7>; 1209 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1210 <0 0 0 2 &pcie2x1l2_intc 1>, 1211 <0 0 0 3 &pcie2x1l2_intc 2>, 1212 <0 0 0 4 &pcie2x1l2_intc 3>; 1213 linux,pci-domain = <4>; 1214 num-ib-windows = <8>; 1215 num-ob-windows = <8>; 1216 max-link-speed = <2>; 1217 msi-map = <0x4000 &its 0x4000 0x1000>; 1218 num-lanes = <1>; 1219 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1220 phy-names = "pcie-phy"; 1221 power-domains = <&power RK3588_PD_PHP>; 1222 ranges = <0x00000800 0x0 0xe0000000 0xa 0x00000000 0x0 0x100000 1223 0x81000000 0x0 0xe0100000 0xa 0x00100000 0x0 0x100000 1224 0x83000000 0x0 0xe0200000 0xa 0x00200000 0x0 0x3fe00000>; 1225 reg = <0xa 0x41000000 0x0 0x400000>, 1226 <0x0 0xfe190000 0x0 0x10000>; 1227 reg-names = "pcie-dbi", "pcie-apb"; 1228 resets = <&cru SRST_PCIE4_POWER_UP>; 1229 reset-names = "pipe"; 1230 status = "disabled"; 1231 1232 pcie2x1l2_intc: legacy-interrupt-controller { 1233 interrupt-controller; 1234 #address-cells = <0>; 1235 #interrupt-cells = <1>; 1236 interrupt-parent = <&gic>; 1237 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>; 1238 }; 1239 }; 1240 1241 gmac1: ethernet@fe1c0000 { 1242 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1243 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1244 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1246 interrupt-names = "macirq", "eth_wake_irq"; 1247 rockchip,grf = <&sys_grf>; 1248 rockchip,php_grf = <&php_grf>; 1249 clocks = <&cru CLK_GMAC1>, <&cru ACLK_GMAC1>, 1250 <&cru PCLK_GMAC1>, <&cru CLK_GMAC1_PTP_REF>; 1251 clock-names = "stmmaceth", "aclk_mac", 1252 "pclk_mac", "ptp_ref"; 1253 resets = <&cru SRST_A_GMAC1>; 1254 reset-names = "stmmaceth"; 1255 1256 snps,mixed-burst; 1257 snps,tso; 1258 1259 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1260 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1261 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1262 status = "disabled"; 1263 1264 mdio1: mdio { 1265 compatible = "snps,dwmac-mdio"; 1266 #address-cells = <0x1>; 1267 #size-cells = <0x0>; 1268 }; 1269 1270 gmac1_stmmac_axi_setup: stmmac-axi-config { 1271 snps,wr_osr_lmt = <4>; 1272 snps,rd_osr_lmt = <8>; 1273 snps,blen = <0 0 0 0 16 8 4>; 1274 }; 1275 1276 gmac1_mtl_rx_setup: rx-queues-config { 1277 snps,rx-queues-to-use = <2>; 1278 queue0 {}; 1279 queue1 {}; 1280 }; 1281 1282 gmac1_mtl_tx_setup: tx-queues-config { 1283 snps,tx-queues-to-use = <2>; 1284 queue0 {}; 1285 queue1 {}; 1286 }; 1287 }; 1288 1289 sata0: sata@fe210000 { 1290 compatible = "snps,dwc-ahci"; 1291 reg = <0 0xfe210000 0 0x1000>; 1292 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1293 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>; 1294 clock-names = "sata", "pmalive", "rxoob", "ref"; 1295 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; 1296 interrupt-names = "hostc"; 1297 phys = <&combphy0_ps PHY_TYPE_SATA>; 1298 phy-names = "sata-phy"; 1299 ports-implemented = <0x1>; 1300 power-domains = <&power RK3588_PD_PHP>; 1301 status = "disabled"; 1302 }; 1303 1304 sata2: sata@fe230000 { 1305 compatible = "snps,dwc-ahci"; 1306 reg = <0 0xfe230000 0 0x1000>; 1307 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1308 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>; 1309 clock-names = "sata", "pmalive", "rxoob", "ref"; 1310 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; 1311 interrupt-names = "hostc"; 1312 phys = <&combphy2_psu PHY_TYPE_SATA>; 1313 phy-names = "sata-phy"; 1314 ports-implemented = <0x1>; 1315 power-domains = <&power RK3588_PD_PHP>; 1316 status = "disabled"; 1317 }; 1318 1319 sfc: spi@fe2b0000 { 1320 compatible = "rockchip,sfc"; 1321 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1322 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1323 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1324 clock-names = "clk_sfc", "hclk_sfc"; 1325 assigned-clocks = <&cru SCLK_SFC>; 1326 assigned-clock-rates = <100000000>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 status = "disabled"; 1330 }; 1331 1332 sdmmc: mmc@fe2c0000 { 1333 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1334 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1335 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1336 clocks = <&scmi_clk SCMI_CCLK_SD>, <&scmi_clk SCMI_HCLK_SD>, 1337 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1338 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; 1339 fifo-depth = <0x100>; 1340 max-frequency = <200000000>; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1343 status = "disabled"; 1344 }; 1345 1346 sdio: mmc@fe2d0000 { 1347 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1348 reg = <0x0 0xfe2d0000 0x0 0x4000>; 1349 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1350 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1351 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1352 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1353 fifo-depth = <0x100>; 1354 max-frequency = <200000000>; 1355 status = "disabled"; 1356 }; 1357 1358 sdhci: mmc@fe2e0000 { 1359 compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci"; 1360 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1361 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1362 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>; 1363 assigned-clock-rates = <200000000>, <24000000>; 1364 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1365 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1366 <&cru TMCLK_EMMC>; 1367 clock-names = "core", "bus", "axi", "block", "timer"; 1368 max-frequency = <200000000>; 1369 status = "disabled"; 1370 }; 1371 1372 i2s0_8ch: i2s@fe470000 { 1373 compatible = "rockchip,rk3588-i2s-tdm"; 1374 reg = <0x0 0xfe470000 0x0 0x1000>; 1375 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 1376 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1377 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1378 dmas = <&dmac0 0>, <&dmac0 1>; 1379 dma-names = "tx", "rx"; 1380 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1381 reset-names = "tx-m", "rx-m"; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&i2s0_lrck 1384 &i2s0_sclk 1385 &i2s0_sdi0 1386 &i2s0_sdi1 1387 &i2s0_sdi2 1388 &i2s0_sdi3 1389 &i2s0_sdo0 1390 &i2s0_sdo1 1391 &i2s0_sdo2 1392 &i2s0_sdo3>; 1393 #sound-dai-cells = <0>; 1394 status = "disabled"; 1395 }; 1396 1397 i2s1_8ch: i2s@fe480000 { 1398 compatible = "rockchip,rk3588-i2s-tdm"; 1399 reg = <0x0 0xfe480000 0x0 0x1000>; 1400 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 1401 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1402 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1403 dmas = <&dmac0 2>, <&dmac0 3>; 1404 dma-names = "tx", "rx"; 1405 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1406 reset-names = "tx-m", "rx-m"; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&i2s1m0_lrck 1409 &i2s1m0_sclk 1410 &i2s1m0_sdi0 1411 &i2s1m0_sdi1 1412 &i2s1m0_sdi2 1413 &i2s1m0_sdi3 1414 &i2s1m0_sdo0 1415 &i2s1m0_sdo1 1416 &i2s1m0_sdo2 1417 &i2s1m0_sdo3>; 1418 #sound-dai-cells = <0>; 1419 status = "disabled"; 1420 }; 1421 1422 i2s2_2ch: i2s@fe490000 { 1423 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1424 reg = <0x0 0xfe490000 0x0 0x1000>; 1425 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1427 clock-names = "i2s_clk", "i2s_hclk"; 1428 dmas = <&dmac1 0>, <&dmac1 1>; 1429 dma-names = "tx", "rx"; 1430 pinctrl-names = "default"; 1431 pinctrl-0 = <&i2s2m1_lrck 1432 &i2s2m1_sclk 1433 &i2s2m1_sdi 1434 &i2s2m1_sdo>; 1435 #sound-dai-cells = <0>; 1436 status = "disabled"; 1437 }; 1438 1439 i2s3_2ch: i2s@fe4a0000 { 1440 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1441 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1442 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1443 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1444 clock-names = "i2s_clk", "i2s_hclk"; 1445 dmas = <&dmac1 2>, <&dmac1 3>; 1446 dma-names = "tx", "rx"; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&i2s3_lrck 1449 &i2s3_sclk 1450 &i2s3_sdi 1451 &i2s3_sdo>; 1452 #sound-dai-cells = <0>; 1453 status = "disabled"; 1454 }; 1455 1456 pdm0: pdm@fe4b0000 { 1457 compatible = "rockchip,rk3588-pdm"; 1458 reg = <0x0 0xfe4b0000 0x0 0x1000>; 1459 clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>; 1460 clock-names = "pdm_clk", "pdm_hclk"; 1461 dmas = <&dmac0 4>; 1462 dma-names = "rx"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&pdm0m0_clk 1465 &pdm0m0_clk1 1466 &pdm0m0_sdi0 1467 &pdm0m0_sdi1 1468 &pdm0m0_sdi2 1469 &pdm0m0_sdi3>; 1470 #sound-dai-cells = <0>; 1471 status = "disabled"; 1472 }; 1473 1474 pdm1: pdm@fe4c0000 { 1475 compatible = "rockchip,rk3588-pdm"; 1476 reg = <0x0 0xfe4c0000 0x0 0x1000>; 1477 clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>; 1478 clock-names = "pdm_clk", "pdm_hclk"; 1479 dmas = <&dmac1 4>; 1480 dma-names = "rx"; 1481 pinctrl-names = "default"; 1482 pinctrl-0 = <&pdm1m0_clk 1483 &pdm1m0_clk1 1484 &pdm1m0_sdi0 1485 &pdm1m0_sdi1 1486 &pdm1m0_sdi2 1487 &pdm1m0_sdi3>; 1488 #sound-dai-cells = <0>; 1489 status = "disabled"; 1490 }; 1491 1492 vad: vad@fe4d0000 { 1493 compatible = "rockchip,rk3588-vad"; 1494 reg = <0x0 0xfe4d0000 0x0 0x1000>; 1495 reg-names = "vad"; 1496 clocks = <&cru HCLK_VAD>; 1497 clock-names = "hclk"; 1498 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1499 rockchip,audio-src = <0>; 1500 rockchip,det-channel = <0>; 1501 rockchip,mode = <0>; 1502 #sound-dai-cells = <0>; 1503 status = "disabled"; 1504 }; 1505 1506 spdif_tx0: spdif-tx@fe4e0000 { 1507 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1508 reg = <0x0 0xfe4e0000 0x0 0x1000>; 1509 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1510 dmas = <&dmac0 5>; 1511 dma-names = "tx"; 1512 clock-names = "mclk", "hclk"; 1513 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; 1514 pinctrl-names = "default"; 1515 pinctrl-0 = <&spdif0m0_tx>; 1516 #sound-dai-cells = <0>; 1517 status = "disabled"; 1518 }; 1519 1520 spdif_tx1: spdif-tx@fe4f0000 { 1521 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1522 reg = <0x0 0xfe4f0000 0x0 0x1000>; 1523 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1524 dmas = <&dmac1 5>; 1525 dma-names = "tx"; 1526 clock-names = "mclk", "hclk"; 1527 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; 1528 pinctrl-names = "default"; 1529 pinctrl-0 = <&spdif1m0_tx>; 1530 #sound-dai-cells = <0>; 1531 status = "disabled"; 1532 }; 1533 1534 acdcdig_dsm: codec-digital@fe500000 { 1535 compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1"; 1536 reg = <0x0 0xfe500000 0x0 0x1000>; 1537 clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>; 1538 clock-names = "dac", "pclk"; 1539 resets = <&cru SRST_DAC_ACDCDIG>; 1540 reset-names = "reset" ; 1541 rockchip,grf = <&sys_grf>; 1542 rockchip,pwm-output-mode; 1543 pinctrl-names = "default"; 1544 pinctrl-0 = <&auddsm_pins>; 1545 #sound-dai-cells = <0>; 1546 status = "disabled"; 1547 }; 1548 1549 hwlock: hwspinlock@fe5a0000 { 1550 compatible = "rockchip,hwspinlock"; 1551 reg = <0 0xfe5a0000 0 0x100>; 1552 #hwlock-cells = <1>; 1553 }; 1554 1555 gic: interrupt-controller@fe600000 { 1556 compatible = "arm,gic-v3"; 1557 #interrupt-cells = <3>; 1558 #address-cells = <2>; 1559 #size-cells = <2>; 1560 ranges; 1561 interrupt-controller; 1562 1563 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1564 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1565 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1566 its: interrupt-controller@fe640000 { 1567 compatible = "arm,gic-v3-its"; 1568 msi-controller; 1569 #msi-cells = <1>; 1570 reg = <0x0 0xfe640000 0x0 0x20000>; 1571 }; 1572 }; 1573 1574 dmac0: dma-controller@fea10000 { 1575 compatible = "arm,pl330", "arm,primecell"; 1576 reg = <0x0 0xfea10000 0x0 0x4000>; 1577 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1579 clocks = <&cru ACLK_DMAC0>; 1580 clock-names = "apb_pclk"; 1581 #dma-cells = <1>; 1582 arm,pl330-periph-burst; 1583 }; 1584 1585 dmac1: dma-controller@fea30000 { 1586 compatible = "arm,pl330", "arm,primecell"; 1587 reg = <0x0 0xfea30000 0x0 0x4000>; 1588 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1590 clocks = <&cru ACLK_DMAC1>; 1591 clock-names = "apb_pclk"; 1592 #dma-cells = <1>; 1593 arm,pl330-periph-burst; 1594 }; 1595 1596 can0: can@fea50000 { 1597 compatible = "rockchip,canfd-1.0"; 1598 reg = <0x0 0xfea50000 0x0 0x1000>; 1599 iinterrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 1600 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 1601 clock-names = "baudclk", "apb_pclk"; 1602 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 1603 reset-names = "can", "can-apb"; 1604 pinctrl-names = "default"; 1605 pinctrl-0 = <&can0m0_pins>; 1606 tx-fifo-depth = <1>; 1607 rx-fifo-depth = <6>; 1608 status = "disabled"; 1609 }; 1610 1611 can1: can@fea60000 { 1612 compatible = "rockchip,canfd-1.0"; 1613 reg = <0x0 0xfea60000 0x0 0x1000>; 1614 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 1615 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 1616 clock-names = "baudclk", "apb_pclk"; 1617 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 1618 reset-names = "can", "can-apb"; 1619 pinctrl-names = "default"; 1620 pinctrl-0 = <&can1m0_pins>; 1621 tx-fifo-depth = <1>; 1622 rx-fifo-depth = <6>; 1623 status = "disabled"; 1624 }; 1625 1626 can2: can@fea70000 { 1627 compatible = "rockchip,canfd-1.0"; 1628 reg = <0x0 0xfea70000 0x0 0x1000>; 1629 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1630 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 1631 clock-names = "baudclk", "apb_pclk"; 1632 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; 1633 reset-names = "can", "can-apb"; 1634 pinctrl-names = "default"; 1635 pinctrl-0 = <&can2m0_pins>; 1636 tx-fifo-depth = <1>; 1637 rx-fifo-depth = <6>; 1638 status = "disabled"; 1639 }; 1640 1641 hw_decompress: decompress@fea80000 { 1642 compatible = "rockchip,hw-decompress"; 1643 reg = <0x0 0xfea80000 0x0 0x1000>; 1644 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1645 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 1646 clock-names = "aclk", "dclk", "pclk"; 1647 resets = <&cru SRST_D_DECOM>; 1648 reset-names = "dresetn"; 1649 status = "disabled"; 1650 }; 1651 1652 i2c1: i2c@fea90000 { 1653 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1654 reg = <0x0 0xfea90000 0x0 0x1000>; 1655 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1656 clock-names = "i2c", "pclk"; 1657 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 1658 pinctrl-names = "default"; 1659 pinctrl-0 = <&i2c1m0_xfer>; 1660 #address-cells = <1>; 1661 #size-cells = <0>; 1662 status = "disabled"; 1663 }; 1664 1665 i2c2: i2c@feaa0000 { 1666 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1667 reg = <0x0 0xfeaa0000 0x0 0x1000>; 1668 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1669 clock-names = "i2c", "pclk"; 1670 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 1671 pinctrl-names = "default"; 1672 pinctrl-0 = <&i2c2m0_xfer>; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 status = "disabled"; 1676 }; 1677 1678 i2c3: i2c@feab0000 { 1679 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1680 reg = <0x0 0xfeab0000 0x0 0x1000>; 1681 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1682 clock-names = "i2c", "pclk"; 1683 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 1684 pinctrl-names = "default"; 1685 pinctrl-0 = <&i2c3m0_xfer>; 1686 #address-cells = <1>; 1687 #size-cells = <0>; 1688 status = "disabled"; 1689 }; 1690 1691 i2c4: i2c@feac0000 { 1692 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1693 reg = <0x0 0xfeac0000 0x0 0x1000>; 1694 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1695 clock-names = "i2c", "pclk"; 1696 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1697 pinctrl-names = "default"; 1698 pinctrl-0 = <&i2c4m0_xfer>; 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 status = "disabled"; 1702 }; 1703 1704 i2c5: i2c@fead0000 { 1705 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1706 reg = <0x0 0xfead0000 0x0 0x1000>; 1707 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1708 clock-names = "i2c", "pclk"; 1709 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&i2c5m0_xfer>; 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 status = "disabled"; 1715 }; 1716 1717 rktimer: timer@feae0000 { 1718 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 1719 reg = <0x0 0xfeae0000 0x0 0x20>; 1720 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 1721 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 1722 clock-names = "pclk", "timer"; 1723 }; 1724 1725 wdt: watchdog@feaf0000 { 1726 compatible = "snps,dw-wdt"; 1727 reg = <0x0 0xfeaf0000 0x0 0x100>; 1728 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1729 clock-names = "tclk", "pclk"; 1730 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1731 status = "disabled"; 1732 }; 1733 1734 spi0: spi@feb00000 { 1735 compatible = "rockchip,rk3066-spi"; 1736 reg = <0x0 0xfeb00000 0x0 0x1000>; 1737 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1741 clock-names = "spiclk", "apb_pclk"; 1742 dmas = <&dmac0 14>, <&dmac0 15>; 1743 dma-names = "tx", "rx"; 1744 pinctrl-names = "default", "high_speed"; 1745 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1746 pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>; 1747 num-cs = <2>; 1748 status = "disabled"; 1749 }; 1750 1751 spi1: spi@feb10000 { 1752 compatible = "rockchip,rk3066-spi"; 1753 reg = <0x0 0xfeb10000 0x0 0x1000>; 1754 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1755 #address-cells = <1>; 1756 #size-cells = <0>; 1757 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1758 clock-names = "spiclk", "apb_pclk"; 1759 dmas = <&dmac0 16>, <&dmac0 17>; 1760 dma-names = "tx", "rx"; 1761 pinctrl-names = "default", "high_speed"; 1762 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 1763 pinctrl-1 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins_hs>; 1764 num-cs = <2>; 1765 status = "disabled"; 1766 }; 1767 1768 spi2: spi@feb20000 { 1769 compatible = "rockchip,rk3066-spi"; 1770 reg = <0x0 0xfeb20000 0x0 0x1000>; 1771 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1775 clock-names = "spiclk", "apb_pclk"; 1776 dmas = <&dmac1 15>, <&dmac1 16>; 1777 dma-names = "tx", "rx"; 1778 pinctrl-names = "default", "high_speed"; 1779 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1780 pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>; 1781 num-cs = <2>; 1782 status = "disabled"; 1783 }; 1784 1785 spi3: spi@feb30000 { 1786 compatible = "rockchip,rk3066-spi"; 1787 reg = <0x0 0xfeb30000 0x0 0x1000>; 1788 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1792 clock-names = "spiclk", "apb_pclk"; 1793 dmas = <&dmac1 17>, <&dmac1 18>; 1794 dma-names = "tx", "rx"; 1795 pinctrl-names = "default", "high_speed"; 1796 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 1797 pinctrl-1 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins_hs>; 1798 num-cs = <2>; 1799 status = "disabled"; 1800 }; 1801 1802 uart1: serial@feb40000 { 1803 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1804 reg = <0x0 0xfeb40000 0x0 0x100>; 1805 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1806 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1807 clock-names = "baudclk", "apb_pclk"; 1808 reg-shift = <2>; 1809 reg-io-width = <4>; 1810 dmas = <&dmac0 8>, <&dmac0 9>; 1811 pinctrl-names = "default"; 1812 pinctrl-0 = <&uart1m0_xfer>; 1813 status = "disabled"; 1814 }; 1815 1816 uart2: serial@feb50000 { 1817 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1818 reg = <0x0 0xfeb50000 0x0 0x100>; 1819 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 1820 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1821 clock-names = "baudclk", "apb_pclk"; 1822 reg-shift = <2>; 1823 reg-io-width = <4>; 1824 dmas = <&dmac0 10>, <&dmac0 11>; 1825 pinctrl-names = "default"; 1826 pinctrl-0 = <&uart2m0_xfer>; 1827 status = "disabled"; 1828 }; 1829 1830 uart3: serial@feb60000 { 1831 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1832 reg = <0x0 0xfeb60000 0x0 0x100>; 1833 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 1834 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1835 clock-names = "baudclk", "apb_pclk"; 1836 reg-shift = <2>; 1837 reg-io-width = <4>; 1838 dmas = <&dmac0 12>, <&dmac0 13>; 1839 pinctrl-names = "default"; 1840 pinctrl-0 = <&uart3m0_xfer>; 1841 status = "disabled"; 1842 }; 1843 1844 uart4: serial@feb70000 { 1845 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1846 reg = <0x0 0xfeb70000 0x0 0x100>; 1847 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1848 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1849 clock-names = "baudclk", "apb_pclk"; 1850 reg-shift = <2>; 1851 reg-io-width = <4>; 1852 dmas = <&dmac1 9>, <&dmac1 10>; 1853 pinctrl-names = "default"; 1854 pinctrl-0 = <&uart4m0_xfer>; 1855 status = "disabled"; 1856 }; 1857 1858 uart5: serial@feb80000 { 1859 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1860 reg = <0x0 0xfeb80000 0x0 0x100>; 1861 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 1862 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1863 clock-names = "baudclk", "apb_pclk"; 1864 reg-shift = <2>; 1865 reg-io-width = <4>; 1866 dmas = <&dmac1 11>, <&dmac1 12>; 1867 pinctrl-names = "default"; 1868 pinctrl-0 = <&uart5m0_xfer>; 1869 status = "disabled"; 1870 }; 1871 1872 uart6: serial@feb90000 { 1873 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1874 reg = <0x0 0xfeb90000 0x0 0x100>; 1875 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 1876 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1877 clock-names = "baudclk", "apb_pclk"; 1878 reg-shift = <2>; 1879 reg-io-width = <4>; 1880 dmas = <&dmac1 13>, <&dmac1 14>; 1881 pinctrl-names = "default"; 1882 pinctrl-0 = <&uart6m0_xfer>; 1883 status = "disabled"; 1884 }; 1885 1886 uart7: serial@feba0000 { 1887 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1888 reg = <0x0 0xfeba0000 0x0 0x100>; 1889 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 1890 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1891 clock-names = "baudclk", "apb_pclk"; 1892 reg-shift = <2>; 1893 reg-io-width = <4>; 1894 dmas = <&dmac2 7>, <&dmac2 8>; 1895 pinctrl-names = "default"; 1896 pinctrl-0 = <&uart7m0_xfer>; 1897 status = "disabled"; 1898 }; 1899 1900 uart8: serial@febb0000 { 1901 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1902 reg = <0x0 0xfebb0000 0x0 0x100>; 1903 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 1904 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1905 clock-names = "baudclk", "apb_pclk"; 1906 reg-shift = <2>; 1907 reg-io-width = <4>; 1908 dmas = <&dmac2 9>, <&dmac2 10>; 1909 pinctrl-names = "default"; 1910 pinctrl-0 = <&uart8m0_xfer>; 1911 status = "disabled"; 1912 }; 1913 1914 uart9: serial@febc0000 { 1915 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1916 reg = <0x0 0xfebc0000 0x0 0x100>; 1917 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 1918 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1919 clock-names = "baudclk", "apb_pclk"; 1920 reg-shift = <2>; 1921 reg-io-width = <4>; 1922 dmas = <&dmac2 11>, <&dmac2 12>; 1923 pinctrl-names = "default"; 1924 pinctrl-0 = <&uart9m0_xfer>; 1925 status = "disabled"; 1926 }; 1927 1928 pwm4: pwm@febd0000 { 1929 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1930 reg = <0x0 0xfebd0000 0x0 0x10>; 1931 #pwm-cells = <3>; 1932 pinctrl-names = "active"; 1933 pinctrl-0 = <&pwm4m0_pins>; 1934 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1935 clock-names = "pwm", "pclk"; 1936 status = "disabled"; 1937 }; 1938 1939 pwm5: pwm@febd0010 { 1940 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1941 reg = <0x0 0xfebd0010 0x0 0x10>; 1942 #pwm-cells = <3>; 1943 pinctrl-names = "active"; 1944 pinctrl-0 = <&pwm5m0_pins>; 1945 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1946 clock-names = "pwm", "pclk"; 1947 status = "disabled"; 1948 }; 1949 1950 pwm6: pwm@febd0020 { 1951 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1952 reg = <0x0 0xfebd0020 0x0 0x10>; 1953 #pwm-cells = <3>; 1954 pinctrl-names = "active"; 1955 pinctrl-0 = <&pwm6m0_pins>; 1956 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1957 clock-names = "pwm", "pclk"; 1958 status = "disabled"; 1959 }; 1960 1961 pwm7: pwm@febd0030 { 1962 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1963 reg = <0x0 0xfebd0030 0x0 0x10>; 1964 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 1966 #pwm-cells = <3>; 1967 pinctrl-names = "active"; 1968 pinctrl-0 = <&pwm7m0_pins>; 1969 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1970 clock-names = "pwm", "pclk"; 1971 status = "disabled"; 1972 }; 1973 1974 pwm8: pwm@febe0000 { 1975 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1976 reg = <0x0 0xfebe0000 0x0 0x10>; 1977 #pwm-cells = <3>; 1978 pinctrl-names = "active"; 1979 pinctrl-0 = <&pwm8m0_pins>; 1980 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1981 clock-names = "pwm", "pclk"; 1982 status = "disabled"; 1983 }; 1984 1985 pwm9: pwm@febe0010 { 1986 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1987 reg = <0x0 0xfebe0010 0x0 0x10>; 1988 #pwm-cells = <3>; 1989 pinctrl-names = "active"; 1990 pinctrl-0 = <&pwm9m0_pins>; 1991 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1992 clock-names = "pwm", "pclk"; 1993 status = "disabled"; 1994 }; 1995 1996 pwm10: pwm@febe0020 { 1997 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1998 reg = <0x0 0xfebe0020 0x0 0x10>; 1999 #pwm-cells = <3>; 2000 pinctrl-names = "active"; 2001 pinctrl-0 = <&pwm10m0_pins>; 2002 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2003 clock-names = "pwm", "pclk"; 2004 status = "disabled"; 2005 }; 2006 2007 pwm11: pwm@febe0030 { 2008 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2009 reg = <0x0 0xfebe0030 0x0 0x10>; 2010 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 2012 #pwm-cells = <3>; 2013 pinctrl-names = "active"; 2014 pinctrl-0 = <&pwm11m0_pins>; 2015 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2016 clock-names = "pwm", "pclk"; 2017 status = "disabled"; 2018 }; 2019 2020 pwm12: pwm@febf0000 { 2021 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2022 reg = <0x0 0xfebf0000 0x0 0x10>; 2023 #pwm-cells = <3>; 2024 pinctrl-names = "active"; 2025 pinctrl-0 = <&pwm12m0_pins>; 2026 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2027 clock-names = "pwm", "pclk"; 2028 status = "disabled"; 2029 }; 2030 2031 pwm13: pwm@febf0010 { 2032 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2033 reg = <0x0 0xfebf0010 0x0 0x10>; 2034 #pwm-cells = <3>; 2035 pinctrl-names = "active"; 2036 pinctrl-0 = <&pwm13m0_pins>; 2037 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2038 clock-names = "pwm", "pclk"; 2039 status = "disabled"; 2040 }; 2041 2042 pwm14: pwm@febf0020 { 2043 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2044 reg = <0x0 0xfebf0020 0x0 0x10>; 2045 #pwm-cells = <3>; 2046 pinctrl-names = "active"; 2047 pinctrl-0 = <&pwm14m0_pins>; 2048 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2049 clock-names = "pwm", "pclk"; 2050 status = "disabled"; 2051 }; 2052 2053 pwm15: pwm@febf0030 { 2054 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2055 reg = <0x0 0xfebf0030 0x0 0x10>; 2056 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 2058 #pwm-cells = <3>; 2059 pinctrl-names = "active"; 2060 pinctrl-0 = <&pwm15m0_pins>; 2061 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2062 clock-names = "pwm", "pclk"; 2063 status = "disabled"; 2064 }; 2065 2066 tsadc: tsadc@fec00000 { 2067 compatible = "rockchip,rk3588-tsadc"; 2068 reg = <0x0 0xfec00000 0x0 0x400>; 2069 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 2070 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2071 clock-names = "tsadc", "apb_pclk"; 2072 assigned-clocks = <&cru CLK_TSADC>; 2073 assigned-clock-rates = <2000000>; 2074 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; 2075 reset-names = "tsadc", "tsadc-apb"; 2076 #thermal-sensor-cells = <1>; 2077 rockchip,hw-tshut-temp = <120000>; 2078 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 2079 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2080 pinctrl-names = "gpio", "otpout"; 2081 pinctrl-0 = <&tsadc_gpio_func>; 2082 pinctrl-1 = <&tsadc_shut_org>; 2083 status = "disabled"; 2084 }; 2085 2086 saradc: saradc@fec10000 { 2087 compatible = "rockchip,rk3588-saradc"; 2088 reg = <0x0 0xfec10000 0x0 0x10000>; 2089 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; 2090 #io-channel-cells = <1>; 2091 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2092 clock-names = "saradc", "apb_pclk"; 2093 resets = <&cru SRST_P_SARADC>; 2094 reset-names = "saradc-apb"; 2095 status = "disabled"; 2096 }; 2097 2098 mailbox0: mailbox@fec60000 { 2099 compatible = "rockchip,rk3588-mailbox", 2100 "rockchip,rk3368-mailbox"; 2101 reg = <0x0 0xfec60000 0x0 0x200>; 2102 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 2106 clocks = <&cru PCLK_MAILBOX0>; 2107 clock-names = "pclk_mailbox"; 2108 #mbox-cells = <1>; 2109 status = "disabled"; 2110 }; 2111 2112 mailbox1: mailbox@fec70000 { 2113 compatible = "rockchip,rk3588-mailbox", 2114 "rockchip,rk3368-mailbox"; 2115 reg = <0x0 0xfec70000 0x0 0x200>; 2116 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2120 clocks = <&cru PCLK_MAILBOX1>; 2121 clock-names = "pclk_mailbox"; 2122 #mbox-cells = <1>; 2123 status = "disabled"; 2124 }; 2125 2126 i2c6: i2c@fec80000 { 2127 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2128 reg = <0x0 0xfec80000 0x0 0x1000>; 2129 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2130 clock-names = "i2c", "pclk"; 2131 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 2132 pinctrl-names = "default"; 2133 pinctrl-0 = <&i2c6m0_xfer>; 2134 #address-cells = <1>; 2135 #size-cells = <0>; 2136 status = "disabled"; 2137 }; 2138 2139 i2c7: i2c@fec90000 { 2140 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2141 reg = <0x0 0xfec90000 0x0 0x1000>; 2142 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2143 clock-names = "i2c", "pclk"; 2144 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 2145 pinctrl-names = "default"; 2146 pinctrl-0 = <&i2c7m0_xfer>; 2147 #address-cells = <1>; 2148 #size-cells = <0>; 2149 status = "disabled"; 2150 }; 2151 2152 i2c8: i2c@feca0000 { 2153 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2154 reg = <0x0 0xfeca0000 0x0 0x1000>; 2155 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2156 clock-names = "i2c", "pclk"; 2157 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 2158 pinctrl-names = "default"; 2159 pinctrl-0 = <&i2c8m0_xfer>; 2160 #address-cells = <1>; 2161 #size-cells = <0>; 2162 status = "disabled"; 2163 }; 2164 2165 spi4: spi@fecb0000 { 2166 compatible = "rockchip,rk3066-spi"; 2167 reg = <0x0 0xfecb0000 0x0 0x1000>; 2168 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2169 #address-cells = <1>; 2170 #size-cells = <0>; 2171 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2172 clock-names = "spiclk", "apb_pclk"; 2173 dmas = <&dmac2 13>, <&dmac2 14>; 2174 dma-names = "tx", "rx"; 2175 pinctrl-names = "default", "high_speed"; 2176 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2177 pinctrl-1 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins_hs>; 2178 num-cs = <2>; 2179 status = "disabled"; 2180 }; 2181 2182 otp: otp@fecc0000 { 2183 compatible = "rockchip,rk3588-otp"; 2184 reg = <0x0 0xfecc0000 0x0 0x400>; 2185 #address-cells = <1>; 2186 #size-cells = <1>; 2187 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2188 <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>; 2189 clock-names = "otpc", "apb", "arb", "phy"; 2190 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2191 <&cru SRST_OTPC_ARB>; 2192 reset-names = "otpc", "apb", "arb"; 2193 }; 2194 2195 mailbox2: mailbox@fece0000 { 2196 compatible = "rockchip,rk3588-mailbox", 2197 "rockchip,rk3368-mailbox"; 2198 reg = <0x0 0xfece0000 0x0 0x200>; 2199 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 2200 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 2201 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 2202 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2203 clocks = <&cru PCLK_MAILBOX2>; 2204 clock-names = "pclk_mailbox"; 2205 #mbox-cells = <1>; 2206 status = "disabled"; 2207 }; 2208 2209 dmac2: dma-controller@fed10000 { 2210 compatible = "arm,pl330", "arm,primecell"; 2211 reg = <0x0 0xfed10000 0x0 0x4000>; 2212 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2214 clocks = <&cru ACLK_DMAC2>; 2215 clock-names = "apb_pclk"; 2216 #dma-cells = <1>; 2217 arm,pl330-periph-burst; 2218 }; 2219 2220 hdptxphy0: phy@fed60000 { 2221 compatible = "rockchip,rk3588-hdptx-phy"; 2222 reg = <0x0 0xfed60000 0x0 0x2000>; 2223 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 2224 clock-names = "ref", "apb"; 2225 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 2226 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 2227 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 2228 <&cru SRST_HDPTX0_LCPLL>; 2229 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 2230 "lcpll"; 2231 rockchip,grf = <&hdptxphy0_grf>; 2232 #phy-cells = <0>; 2233 status = "disabled"; 2234 }; 2235 2236 usbdp_phy0: phy@fed80000 { 2237 compatible = "rockchip,rk3588-usbdp-phy"; 2238 reg = <0x0 0xfed80000 0x0 0x10000>; 2239 rockchip,usb-grf = <&usb_grf>; 2240 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 2241 rockchip,vo-grf = <&vo0_grf>; 2242 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 2243 <&cru CLK_USBDP_PHY0_IMMORTAL>, 2244 <&cru PCLK_USBDPPHY0>; 2245 clock-names = "refclk", "immortal", "pclk"; 2246 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 2247 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 2248 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 2249 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 2250 <&cru SRST_P_USBDPPHY0>; 2251 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2252 status = "disabled"; 2253 2254 usbdp_phy0_dp: dp-port { 2255 #phy-cells = <0>; 2256 status = "disabled"; 2257 }; 2258 2259 usbdp_phy0_u3: u3-port { 2260 #phy-cells = <0>; 2261 status = "disabled"; 2262 }; 2263 }; 2264 2265 combphy0_ps: phy@fee00000 { 2266 compatible = "rockchip,rk3588-naneng-combphy"; 2267 reg = <0x0 0xfee00000 0x0 0x100>; 2268 #phy-cells = <1>; 2269 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>; 2270 clock-names = "refclk", "apbclk"; 2271 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 2272 assigned-clock-rates = <100000000>; 2273 resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>; 2274 reset-names = "combphy-apb", "combphy"; 2275 rockchip,pipe-grf = <&php_grf>; 2276 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2277 status = "disabled"; 2278 }; 2279 2280 combphy2_psu: phy@fee20000 { 2281 compatible = "rockchip,rk3588-naneng-combphy"; 2282 reg = <0x0 0xfee20000 0x0 0x100>; 2283 #phy-cells = <1>; 2284 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>; 2285 clock-names = "refclk", "apbclk"; 2286 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 2287 assigned-clock-rates = <100000000>; 2288 resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>; 2289 reset-names = "combphy-apb", "combphy"; 2290 rockchip,pipe-grf = <&php_grf>; 2291 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 2292 rockchip,pcie1ln-sel-bits = <0x100 1 1 0>; 2293 status = "disabled"; 2294 }; 2295 2296 pinctrl: pinctrl { 2297 compatible = "rockchip,rk3588-pinctrl"; 2298 rockchip,grf = <&ioc>; 2299 #address-cells = <2>; 2300 #size-cells = <2>; 2301 ranges; 2302 2303 gpio0: gpio@fd8a0000 { 2304 compatible = "rockchip,gpio-bank"; 2305 reg = <0x0 0xfd8a0000 0x0 0x100>; 2306 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 2307 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2308 2309 gpio-controller; 2310 #gpio-cells = <2>; 2311 gpio-ranges = <&pinctrl 0 0 32>; 2312 interrupt-controller; 2313 #interrupt-cells = <2>; 2314 }; 2315 2316 gpio1: gpio@fec20000 { 2317 compatible = "rockchip,gpio-bank"; 2318 reg = <0x0 0xfec20000 0x0 0x100>; 2319 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 2320 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2321 2322 gpio-controller; 2323 #gpio-cells = <2>; 2324 gpio-ranges = <&pinctrl 0 32 32>; 2325 interrupt-controller; 2326 #interrupt-cells = <2>; 2327 }; 2328 2329 gpio2: gpio@fec30000 { 2330 compatible = "rockchip,gpio-bank"; 2331 reg = <0x0 0xfec30000 0x0 0x100>; 2332 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; 2333 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2334 2335 gpio-controller; 2336 #gpio-cells = <2>; 2337 gpio-ranges = <&pinctrl 0 64 32>; 2338 interrupt-controller; 2339 #interrupt-cells = <2>; 2340 }; 2341 2342 gpio3: gpio@fec40000 { 2343 compatible = "rockchip,gpio-bank"; 2344 reg = <0x0 0xfec40000 0x0 0x100>; 2345 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 2346 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2347 2348 gpio-controller; 2349 #gpio-cells = <2>; 2350 gpio-ranges = <&pinctrl 0 96 32>; 2351 interrupt-controller; 2352 #interrupt-cells = <2>; 2353 }; 2354 2355 gpio4: gpio@fec50000 { 2356 compatible = "rockchip,gpio-bank"; 2357 reg = <0x0 0xfec50000 0x0 0x100>; 2358 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; 2359 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2360 2361 gpio-controller; 2362 #gpio-cells = <2>; 2363 gpio-ranges = <&pinctrl 0 128 32>; 2364 interrupt-controller; 2365 #interrupt-cells = <2>; 2366 }; 2367 }; 2368}; 2369 2370#include "rk3588s-pinctrl.dtsi" 2371