1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rk3588-power.h> 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 compatible = "rockchip,rk3588"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 ethernet1 = &gmac1; 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 i2c4 = &i2c4; 27 i2c5 = &i2c5; 28 i2c6 = &i2c6; 29 i2c7 = &i2c7; 30 i2c8 = &i2c8; 31 serial0 = &uart0; 32 serial1 = &uart1; 33 serial2 = &uart2; 34 serial3 = &uart3; 35 serial4 = &uart4; 36 serial5 = &uart5; 37 serial6 = &uart6; 38 serial7 = &uart7; 39 serial8 = &uart8; 40 serial9 = &uart9; 41 spi0 = &spi0; 42 spi1 = &spi1; 43 spi2 = &spi2; 44 spi3 = &spi3; 45 spi4 = &spi4; 46 spi5 = &sfc; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu-map { 54 cluster0 { 55 core0 { 56 cpu = <&cpu_l0>; 57 }; 58 core1 { 59 cpu = <&cpu_l1>; 60 }; 61 core2 { 62 cpu = <&cpu_l2>; 63 }; 64 core3 { 65 cpu = <&cpu_l3>; 66 }; 67 }; 68 cluster1 { 69 core0 { 70 cpu = <&cpu_b0>; 71 }; 72 core1 { 73 cpu = <&cpu_b1>; 74 }; 75 }; 76 cluster2 { 77 core0 { 78 cpu = <&cpu_b2>; 79 }; 80 core1 { 81 cpu = <&cpu_b3>; 82 }; 83 }; 84 }; 85 86 cpu_l0: cpu@0 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a55"; 89 reg = <0x0>; 90 enable-method = "psci"; 91 capacity-dmips-mhz = <530>; 92 }; 93 94 cpu_l1: cpu@100 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a55"; 97 reg = <0x100>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <530>; 100 }; 101 102 cpu_l2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a55"; 105 reg = <0x200>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <530>; 108 }; 109 110 cpu_l3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 capacity-dmips-mhz = <530>; 116 }; 117 118 cpu_b0: cpu@400 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a76"; 121 reg = <0x400>; 122 enable-method = "psci"; 123 capacity-dmips-mhz = <1024>; 124 }; 125 126 cpu_b1: cpu@500 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a76"; 129 reg = <0x500>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <1024>; 132 }; 133 134 cpu_b2: cpu@600 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a76"; 137 reg = <0x600>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 }; 141 142 cpu_b3: cpu@700 { 143 device_type = "cpu"; 144 compatible = "arm,cortex-a76"; 145 reg = <0x700>; 146 enable-method = "psci"; 147 capacity-dmips-mhz = <1024>; 148 }; 149 }; 150 151 arm_pmu: arm-pmu { 152 compatible = "arm,armv8-pmuv3"; 153 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_LOW>; 154 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>, 155 <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 156 }; 157 158 firmware: firmware { 159 optee: optee { 160 compatible = "linaro,optee-tz"; 161 method = "smc"; 162 }; 163 164 scmi: scmi { 165 compatible = "arm,scmi-smc"; 166 shmem = <&scmi_shmem>; 167 arm,smc-id = <0x82000010>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 scmi_clk: protocol@14 { 172 reg = <0x14>; 173 #clock-cells = <1>; 174 175 assigned-clocks = <&scmi_clk SCMI_SPLL>; 176 assigned-clock-rates = <700000000>; 177 }; 178 179 scmi_reset: protocol@16 { 180 reg = <0x16>; 181 #reset-cells = <1>; 182 }; 183 }; 184 185 sdei: sdei { 186 compatible = "arm,sdei-1.0"; 187 method = "smc"; 188 }; 189 }; 190 191 psci: psci { 192 compatible = "arm,psci-1.0"; 193 method = "smc"; 194 }; 195 196 spll: spll { 197 compatible = "fixed-clock"; 198 #clock-cells = <0>; 199 clock-frequency = <702000000>; 200 clock-output-names = "spll"; 201 }; 202 203 timer { 204 compatible = "arm,armv8-timer"; 205 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 207 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 209 }; 210 211 xin32k: xin32k { 212 compatible = "fixed-clock"; 213 #clock-cells = <0>; 214 clock-frequency = <32768>; 215 clock-output-names = "xin32k"; 216 }; 217 218 xin24m: xin24m { 219 compatible = "fixed-clock"; 220 #clock-cells = <0>; 221 clock-frequency = <24000000>; 222 clock-output-names = "xin24m"; 223 }; 224 225 sram: sram@10f000 { 226 compatible = "mmio-sram"; 227 reg = <0x0 0x0010f000 0x0 0x100>; 228 #address-cells = <1>; 229 #size-cells = <1>; 230 ranges = <0 0x0 0x0010f000 0x100>; 231 232 scmi_shmem: scmi_shmem@0 { 233 compatible = "arm,scmi-shmem"; 234 reg = <0x0 0x100>; 235 }; 236 }; 237 238 usbdrd3_0: usbdrd3_0 { 239 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 240 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 241 <&cru ACLK_USB3OTG0>; 242 clock-names = "ref", "suspend", "bus"; 243 #address-cells = <2>; 244 #size-cells = <2>; 245 ranges; 246 status = "disabled"; 247 248 usbdrd_dwc3_0: usb@fc000000 { 249 compatible = "snps,dwc3"; 250 reg = <0x0 0xfc000000 0x0 0x400000>; 251 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 252 power-domains = <&power RK3588_PD_USB>; 253 resets = <&cru SRST_A_USB3OTG0>; 254 reset-names = "usb3-otg"; 255 dr_mode = "otg"; 256 phy_type = "utmi_wide"; 257 snps,dis_enblslpm_quirk; 258 snps,dis-u1-entry-quirk; 259 snps,dis-u2-entry-quirk; 260 snps,dis-u2-freeclk-exists-quirk; 261 snps,dis-del-phy-power-chg-quirk; 262 snps,dis-tx-ipgap-linecheck-quirk; 263 status = "disabled"; 264 }; 265 }; 266 267 usb_host0_ehci: usb@fc800000 { 268 compatible = "generic-ehci"; 269 reg = <0x0 0xfc800000 0x0 0x40000>; 270 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; 272 clock-names = "usbhost", "arbiter"; 273 power-domains = <&power RK3588_PD_USB>; 274 status = "disabled"; 275 }; 276 277 usb_host0_ohci: usb@fc840000 { 278 compatible = "generic-ohci"; 279 reg = <0x0 0xfc840000 0x0 0x40000>; 280 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; 282 clock-names = "usbhost", "arbiter"; 283 power-domains = <&power RK3588_PD_USB>; 284 status = "disabled"; 285 }; 286 287 usb_host1_ehci: usb@fc880000 { 288 compatible = "generic-ehci"; 289 reg = <0x0 0xfc880000 0x0 0x40000>; 290 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; 292 clock-names = "usbhost", "arbiter"; 293 power-domains = <&power RK3588_PD_USB>; 294 status = "disabled"; 295 }; 296 297 usb_host1_ohci: usb@fc8c0000 { 298 compatible = "generic-ohci"; 299 reg = <0x0 0xfc8c0000 0x0 0x40000>; 300 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; 302 clock-names = "usbhost", "arbiter"; 303 power-domains = <&power RK3588_PD_USB>; 304 status = "disabled"; 305 }; 306 307 mmu600_pcie: iommu@fc900000 { 308 compatible = "arm,smmu-v3"; 309 reg = <0x0 0xfc900000 0x0 0x200000>; 310 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 315 #iommu-cells = <1>; 316 status = "disabled"; 317 }; 318 319 mmu600_php: iommu@fcb00000 { 320 compatible = "arm,smmu-v3"; 321 reg = <0x0 0xfcb00000 0x0 0x200000>; 322 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 326 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 327 #iommu-cells = <1>; 328 status = "disabled"; 329 }; 330 331 usbhost3_0: usbhost3_0 { 332 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 333 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 334 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>; 335 clock-names = "ref", "suspend", "bus", "utmi"; 336 #address-cells = <2>; 337 #size-cells = <2>; 338 ranges; 339 status = "disabled"; 340 341 usbhost_dwc3_0: usb@fcd00000 { 342 compatible = "snps,dwc3"; 343 reg = <0x0 0xfcd00000 0x0 0x400000>; 344 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 345 power-domains = <&power RK3588_PD_PHP>; 346 resets = <&cru SRST_A_USB3OTG2>; 347 reset-names = "usb3-host"; 348 dr_mode = "host"; 349 phy_type = "utmi_wide"; 350 snps,dis_enblslpm_quirk; 351 snps,dis-u2-freeclk-exists-quirk; 352 snps,dis-del-phy-power-chg-quirk; 353 snps,dis-tx-ipgap-linecheck-quirk; 354 status = "disabled"; 355 }; 356 }; 357 358 sys_grf: syscon@fd58c000 { 359 compatible = "rockchip,rk3588-sys-grf", "syscon"; 360 reg = <0x0 0xfd58c000 0x0 0x1000>; 361 }; 362 363 vo0_grf: syscon@fd5a6000 { 364 compatible = "rockchip,rk3588-vo-grf", "syscon"; 365 reg = <0x0 0xfd5a6000 0x0 0x2000>; 366 }; 367 368 vo1_grf: syscon@fd5a8000 { 369 compatible = "rockchip,rk3588-vo-grf", "syscon"; 370 reg = <0x0 0xfd5a8000 0x0 0x100>; 371 }; 372 373 usb_grf: syscon@fd5ac000 { 374 compatible = "rockchip,rk3588-usb-grf", "syscon"; 375 reg = <0x0 0xfd5ac000 0x0 0x4000>; 376 }; 377 378 php_grf: syscon@fd5b0000 { 379 compatible = "rockchip,rk3588-php-grf", "syscon"; 380 reg = <0x0 0xfd5b0000 0x0 0x1000>; 381 }; 382 383 pipe_phy0_grf: syscon@fd5bc000 { 384 compatible = "rockchip,pipe-phy-grf", "syscon"; 385 reg = <0x0 0xfd5bc000 0x0 0x100>; 386 }; 387 388 pipe_phy2_grf: syscon@fd5c4000 { 389 compatible = "rockchip,pipe-phy-grf", "syscon"; 390 reg = <0x0 0xfd5c4000 0x0 0x100>; 391 }; 392 393 usbdpphy0_grf: syscon@fd5c8000 { 394 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 395 reg = <0x0 0xfd5c8000 0x0 0x4000>; 396 }; 397 398 usb2phy0_grf: syscon@fd5d0000 { 399 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 400 "simple-mfd"; 401 reg = <0x0 0xfd5d0000 0x0 0x4000>; 402 #address-cells = <1>; 403 #size-cells = <1>; 404 405 u2phy0: usb2-phy@0 { 406 compatible = "rockchip,rk3588-usb2phy"; 407 reg = <0x0 0x10>; 408 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 410 clock-names = "phyclk"; 411 #clock-cells = <0>; 412 status = "disabled"; 413 414 u2phy0_otg: otg-port { 415 #phy-cells = <0>; 416 status = "disabled"; 417 }; 418 }; 419 }; 420 421 usb2phy2_grf: syscon@fd5d8000 { 422 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 423 "simple-mfd"; 424 reg = <0x0 0xfd5d8000 0x0 0x4000>; 425 #address-cells = <1>; 426 #size-cells = <1>; 427 428 u2phy2: usb2-phy@8000 { 429 compatible = "rockchip,rk3588-usb2phy"; 430 reg = <0x8000 0x10>; 431 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 433 clock-names = "phyclk"; 434 #clock-cells = <0>; 435 status = "disabled"; 436 437 u2phy2_host: host-port { 438 #phy-cells = <0>; 439 status = "disabled"; 440 }; 441 }; 442 }; 443 444 usb2phy3_grf: syscon@fd5dc000 { 445 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 446 "simple-mfd"; 447 reg = <0x0 0xfd5dc000 0x0 0x4000>; 448 #address-cells = <1>; 449 #size-cells = <1>; 450 451 u2phy3: usb2-phy@c000 { 452 compatible = "rockchip,rk3588-usb2phy"; 453 reg = <0xc000 0x10>; 454 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 456 clock-names = "phyclk"; 457 #clock-cells = <0>; 458 status = "disabled"; 459 460 u2phy3_host: host-port { 461 #phy-cells = <0>; 462 status = "disabled"; 463 }; 464 }; 465 }; 466 467 hdptxphy0_grf: syscon@fd5e0000 { 468 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 469 reg = <0x0 0xfd5e0000 0x0 0x100>; 470 }; 471 472 ioc: syscon@fd5f0000 { 473 compatible = "rockchip,rk3588-ioc", "syscon"; 474 reg = <0x0 0xfd5f0000 0x0 0x10000>; 475 }; 476 477 syssram: sram@fd600000 { 478 compatible = "mmio-sram"; 479 reg = <0x0 0xfd600000 0x0 0x100000>; 480 481 #address-cells = <1>; 482 #size-cells = <1>; 483 ranges = <0x0 0x0 0xfd600000 0x100000>; 484 }; 485 486 cru: clock-controller@fd7c0000 { 487 compatible = "rockchip,rk3588-cru"; 488 rockchip,grf = <&php_grf>; 489 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 490 #clock-cells = <1>; 491 #reset-cells = <1>; 492 493 assigned-clocks = 494 <&cru PLL_PPLL>, <&cru PLL_CPLL>, 495 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 496 <&cru ARMCLK_L>, <&cru ARMCLK_B01>, 497 <&cru ACLK_CENTER_ROOT>, <&cru PCLK_CENTER_ROOT>, 498 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 499 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 500 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 501 <&cru HCLK_PMU_CM0_ROOT>; 502 assigned-clock-rates = 503 <100000000>, <1500000000>, 504 <850000000>, <1188000000>, 505 <816000000>, <1008000000>, 506 <600000000>, <200000000>, 507 <400000000>, <500000000>, 508 <800000000>, <100000000>, 509 <400000000>, <100000000>, 510 <200000000>; 511 }; 512 513 i2c0: i2c@fd880000 { 514 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 515 reg = <0x0 0xfd880000 0x0 0x1000>; 516 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 517 clock-names = "i2c", "pclk"; 518 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 519 pinctrl-names = "default"; 520 pinctrl-0 = <&i2c0m0_xfer>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 status = "disabled"; 524 }; 525 526 uart0: serial@fd890000 { 527 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 528 reg = <0x0 0xfd890000 0x0 0x100>; 529 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 531 clock-names = "baudclk", "apb_pclk"; 532 reg-shift = <2>; 533 reg-io-width = <4>; 534 dmas = <&dmac0 6>, <&dmac0 7>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&uart0m0_xfer>; 537 status = "disabled"; 538 }; 539 540 pwm0: pwm@fd8b0000 { 541 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 542 reg = <0x0 0xfd8b0000 0x0 0x10>; 543 #pwm-cells = <3>; 544 pinctrl-names = "active"; 545 pinctrl-0 = <&pwm0m0_pins>; 546 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 547 clock-names = "pwm", "pclk"; 548 status = "disabled"; 549 }; 550 551 pwm1: pwm@fd8b0010 { 552 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 553 reg = <0x0 0xfd8b0010 0x0 0x10>; 554 #pwm-cells = <3>; 555 pinctrl-names = "active"; 556 pinctrl-0 = <&pwm1m0_pins>; 557 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 558 clock-names = "pwm", "pclk"; 559 status = "disabled"; 560 }; 561 562 pwm2: pwm@fd8b0020 { 563 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 564 reg = <0x0 0xfd8b0020 0x0 0x10>; 565 #pwm-cells = <3>; 566 pinctrl-names = "active"; 567 pinctrl-0 = <&pwm2m0_pins>; 568 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 569 clock-names = "pwm", "pclk"; 570 status = "disabled"; 571 }; 572 573 pwm3: pwm@fd8b0030 { 574 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 575 reg = <0x0 0xfd8b0030 0x0 0x10>; 576 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 578 #pwm-cells = <3>; 579 pinctrl-names = "active"; 580 pinctrl-0 = <&pwm3m0_pins>; 581 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 582 clock-names = "pwm", "pclk"; 583 status = "disabled"; 584 }; 585 586 pmu: power-management@fd8d8000 { 587 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 588 reg = <0x0 0xfd8d8000 0x0 0x400>; 589 590 power: power-controller { 591 compatible = "rockchip,rk3588-power-controller"; 592 #power-domain-cells = <1>; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 status = "okay"; 596 597 /* These power domains are grouped by VD_NPU */ 598 power-domain@RK3588_PD_NPU { 599 reg = <RK3588_PD_NPU>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 603 power-domain@RK3588_PD_NPUTOP { 604 reg = <RK3588_PD_NPUTOP>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 608 power-domain@RK3588_PD_NPU1 { 609 reg = <RK3588_PD_NPU1>; 610 }; 611 power-domain@RK3588_PD_NPU2 { 612 reg = <RK3588_PD_NPU2>; 613 }; 614 }; 615 }; 616 /* These power domains are grouped by VD_GPU */ 617 power-domain@RK3588_PD_GPU { 618 reg = <RK3588_PD_GPU>; 619 }; 620 /* These power domains are grouped by VD_VCODEC */ 621 power-domain@RK3588_PD_VCODEC { 622 reg = <RK3588_PD_VCODEC>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 626 power-domain@RK3588_PD_RKVDEC0 { 627 reg = <RK3588_PD_RKVDEC0>; 628 }; 629 power-domain@RK3588_PD_RKVDEC1 { 630 reg = <RK3588_PD_RKVDEC1>; 631 }; 632 power-domain@RK3588_PD_VENC0 { 633 reg = <RK3588_PD_VENC0>; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 637 power-domain@RK3588_PD_VENC1 { 638 reg = <RK3588_PD_VENC1>; 639 }; 640 }; 641 }; 642 /* These power domains are grouped by VD_LOGIC */ 643 power-domain@RK3588_PD_VDPU { 644 reg = <RK3588_PD_VDPU>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 648 power-domain@RK3588_PD_RGA30 { 649 reg = <RK3588_PD_RGA30>; 650 }; 651 power-domain@RK3588_PD_av1 { 652 reg = <RK3588_PD_AV1>; 653 }; 654 }; 655 power-domain@RK3588_PD_VOP { 656 reg = <RK3588_PD_VOP>; 657 }; 658 power-domain@RK3588_PD_VO0 { 659 reg = <RK3588_PD_VO0>; 660 }; 661 power-domain@RK3588_PD_VO1 { 662 reg = <RK3588_PD_VO1>; 663 }; 664 power-domain@RK3588_PD_VI { 665 reg = <RK3588_PD_VI>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 669 power-domain@RK3588_PD_ISP1 { 670 reg = <RK3588_PD_ISP1>; 671 }; 672 power-domain@RK3588_PD_FEC { 673 reg = <RK3588_PD_FEC>; 674 }; 675 }; 676 power-domain@RK3588_PD_RGA31 { 677 reg = <RK3588_PD_RGA31>; 678 }; 679 power-domain@RK3588_PD_USB { 680 reg = <RK3588_PD_USB>; 681 }; 682 power-domain@RK3588_PD_PHP { 683 reg = <RK3588_PD_PHP>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 687 power-domain@RK3588_PD_GMAC { 688 reg = <RK3588_PD_GMAC>; 689 }; 690 power-domain@RK3588_PD_PCIE { 691 reg = <RK3588_PD_PCIE>; 692 }; 693 }; 694 power-domain@RK3588_PD_NVM { 695 reg = <RK3588_PD_NVM>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 699 power-domain@RK3588_PD_NVM0 { 700 reg = <RK3588_PD_NVM0>; 701 }; 702 }; 703 power-domain@RK3588_PD_SDIO { 704 reg = <RK3588_PD_SDIO>; 705 }; 706 power-domain@RK3588_PD_AUDIO { 707 reg = <RK3588_PD_AUDIO>; 708 }; 709 power-domain@RK3588_PD_SDMMC { 710 reg = <RK3588_PD_SDMMC>; 711 }; 712 }; 713 }; 714 715 pvtm@fda40000 { 716 compatible = "rockchip,rk3588-bigcore0-pvtm"; 717 reg = <0x0 0xfda40000 0x0 0x100>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 pvtm@0 { 721 reg = <0>; 722 clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>; 723 clock-names = "clk", "pclk"; 724 }; 725 }; 726 727 pvtm@fda50000 { 728 compatible = "rockchip,rk3588-bigcore1-pvtm"; 729 reg = <0x0 0xfda50000 0x0 0x100>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 pvtm@1 { 733 reg = <1>; 734 clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>; 735 clock-names = "clk", "pclk"; 736 }; 737 }; 738 739 pvtm@fda60000 { 740 compatible = "rockchip,rk3588-litcore-pvtm"; 741 reg = <0x0 0xfda60000 0x0 0x100>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 pvtm@2 { 745 reg = <2>; 746 clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>; 747 clock-names = "clk", "pclk"; 748 }; 749 }; 750 751 pvtm@fdaf0000 { 752 compatible = "rockchip,rk3588-npu-pvtm"; 753 reg = <0x0 0xfdaf0000 0x0 0x100>; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 pvtm@3 { 757 reg = <3>; 758 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>; 759 clock-names = "clk", "pclk"; 760 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; 761 reset-names = "rts", "rst-p"; 762 }; 763 }; 764 765 pvtm@fdb30000 { 766 compatible = "rockchip,rk3588-gpu-pvtm"; 767 reg = <0x0 0xfdb30000 0x0 0x100>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 pvtm@4 { 771 reg = <4>; 772 clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>; 773 clock-names = "clk", "pclk"; 774 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; 775 reset-names = "rts", "rst-p"; 776 }; 777 }; 778 779 npu0_mmu: iommu@fdab9000 { 780 compatible = "rockchip,iommu-v2"; 781 reg = <0x0 0xfdab9000 0x0 0x100>, <0x0 0xfdaba000 0x0 0x100>; 782 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 783 interrupt-names = "npu0_mmu"; 784 clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>; 785 clock-names = "aclk", "iface"; 786 power-domains = <&power RK3588_PD_NPUTOP>; 787 #iommu-cells = <0>; 788 status = "disabled"; 789 }; 790 791 npu1_mmu: iommu@fdaca000 { 792 compatible = "rockchip,iommu-v2"; 793 reg = <0x0 0xfdaca000 0x0 0x100>; 794 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 795 interrupt-names = "npu1_mmu"; 796 clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>; 797 clock-names = "aclk", "iface"; 798 power-domains = <&power RK3588_PD_NPU1>; 799 #iommu-cells = <0>; 800 status = "disabled"; 801 }; 802 803 npu2_mmu: iommu@fdada000 { 804 compatible = "rockchip,iommu-v2"; 805 reg = <0x0 0xfdada000 0x0 0x100>; 806 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 807 interrupt-names = "npu2_mmu"; 808 clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>; 809 clock-names = "aclk", "iface"; 810 power-domains = <&power RK3588_PD_NPU2>; 811 #iommu-cells = <0>; 812 status = "disabled"; 813 }; 814 815 vdpu_mmu: iommu@fdb50800 { 816 compatible = "rockchip,iommu-v2"; 817 reg = <0x0 0xfdb50800 0x0 0x40>; 818 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 819 interrupt-names = "irq_vdpu_mmu"; 820 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 821 clock-names = "aclk", "iface"; 822 power-domains = <&power RK3588_PD_VDPU>; 823 #iommu-cells = <0>; 824 status = "disabled"; 825 }; 826 827 rga3_0_mmu: iommu@fdb60f00 { 828 compatible = "rockchip,iommu-v2"; 829 reg = <0x0 0xfdb60f00 0x0 0x100>; 830 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 831 interrupt-names = "rga3_0_mmu"; 832 clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; 833 clock-names = "aclk", "iface"; 834 power-domains = <&power RK3588_PD_RGA30>; 835 #iommu-cells = <0>; 836 status = "disabled"; 837 }; 838 839 rga3_1_mmu: iommu@fdb70f00 { 840 compatible = "rockchip,iommu-v2"; 841 reg = <0x0 0xfdb70f00 0x0 0x100>; 842 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 843 interrupt-names = "rga3_1_mmu"; 844 clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; 845 clock-names = "aclk", "iface"; 846 power-domains = <&power RK3588_PD_RGA31>; 847 #iommu-cells = <0>; 848 status = "disabled"; 849 }; 850 851 jpegd_mmu: iommu@fdb90480 { 852 compatible = "rockchip,iommu-v2"; 853 reg = <0x0 0xfdb90480 0x0 0x40>; 854 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 855 interrupt-names = "irq_jpegd_mmu"; 856 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 857 clock-names = "aclk", "iface"; 858 power-domains = <&power RK3588_PD_VDPU>; 859 #iommu-cells = <0>; 860 status = "disabled"; 861 }; 862 863 jpege0_mmu: iommu@fdba0800 { 864 compatible = "rockchip,iommu-v2"; 865 reg = <0x0 0xfdba0800 0x0 0x40>; 866 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 867 interrupt-names = "irq_jpege0_mmu"; 868 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 869 clock-names = "aclk", "iface"; 870 power-domains = <&power RK3588_PD_VDPU>; 871 #iommu-cells = <0>; 872 status = "disabled"; 873 }; 874 875 jpege1_mmu: iommu@fdba4800 { 876 compatible = "rockchip,iommu-v2"; 877 reg = <0x0 0xfdba4800 0x0 0x40>; 878 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 879 interrupt-names = "irq_jpege1_mmu"; 880 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 881 clock-names = "aclk", "iface"; 882 power-domains = <&power RK3588_PD_VDPU>; 883 #iommu-cells = <0>; 884 status = "disabled"; 885 }; 886 887 jpege2_mmu: iommu@fdba8800 { 888 compatible = "rockchip,iommu-v2"; 889 reg = <0x0 0xfdba8800 0x0 0x40>; 890 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 891 interrupt-names = "irq_jpege2_mmu"; 892 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 893 clock-names = "aclk", "iface"; 894 power-domains = <&power RK3588_PD_VDPU>; 895 #iommu-cells = <0>; 896 status = "disabled"; 897 }; 898 899 jpege3_mmu: iommu@fdbac800 { 900 compatible = "rockchip,iommu-v2"; 901 reg = <0x0 0xfdbac800 0x0 0x40>; 902 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 903 interrupt-names = "irq_jpege3_mmu"; 904 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 905 clock-names = "aclk", "iface"; 906 power-domains = <&power RK3588_PD_VDPU>; 907 #iommu-cells = <0>; 908 status = "disabled"; 909 }; 910 911 iep_mmu: iommu@fdbb0800 { 912 compatible = "rockchip,iommu-v2"; 913 reg = <0x0 0xfdbb0800 0x0 0x100>; 914 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "irq_iep_mmu"; 916 clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>; 917 clock-names = "aclk", "iface"; 918 #iommu-cells = <0>; 919 power-domains = <&power RK3588_PD_VDPU>; 920 status = "disabled"; 921 }; 922 923 rkvenc0_mmu: iommu@fdbdf000 { 924 compatible = "rockchip,iommu-v2"; 925 reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>; 926 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 928 interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1"; 929 clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>; 930 clock-names = "aclk", "iface"; 931 rockchip,disable-mmu-reset; 932 rockchip,enable-cmd-retry; 933 #iommu-cells = <0>; 934 power-domains = <&power RK3588_PD_VENC0>; 935 status = "disabled"; 936 }; 937 938 rkvenc1_mmu: iommu@fdbef000 { 939 compatible = "rockchip,iommu-v2"; 940 reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>; 941 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 943 interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1"; 944 clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>; 945 lock-names = "aclk", "iface"; 946 rockchip,disable-mmu-reset; 947 rockchip,enable-cmd-retry; 948 #iommu-cells = <0>; 949 power-domains = <&power RK3588_PD_VENC1>; 950 status = "disabled"; 951 }; 952 953 rkvdec0_mmu: iommu@fdc38700 { 954 compatible = "rockchip,iommu-v2"; 955 reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; 956 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 957 interrupt-names = "irq_rkvdec0_mmu"; 958 locks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; 959 clock-names = "aclk", "iface"; 960 rockchip,disable-mmu-reset; 961 rockchip,enable-cmd-retry; 962 #iommu-cells = <0>; 963 power-domains = <&power RK3588_PD_RKVDEC0>; 964 status = "disabled"; 965 }; 966 967 rkvdec1_mmu: iommu@fdc48700 { 968 compatible = "rockchip,iommu-v2"; 969 reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>; 970 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 971 interrupt-names = "irq_rkvdec1_mmu"; 972 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; 973 clock-names = "aclk", "iface"; 974 rockchip,disable-mmu-reset; 975 rockchip,enable-cmd-retry; 976 #iommu-cells = <0>; 977 power-domains = <&power RK3588_PD_RKVDEC1>; 978 status = "disabled"; 979 }; 980 981 isp0_mmu: iommu@fdcb7f00 { 982 compatible = "rockchip,iommu-v2"; 983 reg = <0x0 0xfdcb7f00 0x0 0x100>; 984 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 985 interrupt-names = "isp0_mmu"; 986 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; 987 clock-names = "aclk", "iface"; 988 power-domains = <&power RK3588_PD_VI>; 989 #iommu-cells = <0>; 990 rockchip,disable-mmu-reset; 991 status = "disabled"; 992 }; 993 994 isp1_mmu: iommu@fdcc7f00 { 995 compatible = "rockchip,iommu-v2"; 996 reg = <0x0 0xfdcc7f00 0x0 0x100>; 997 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 998 interrupt-names = "isp1_mmu"; 999 clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; 1000 clock-names = "aclk", "iface"; 1001 power-domains = <&power RK3588_PD_ISP1>; 1002 #iommu-cells = <0>; 1003 rockchip,disable-mmu-reset; 1004 status = "disabled"; 1005 }; 1006 1007 fec0_mmu: iommu@fdcd0f00 { 1008 compatible = "rockchip,iommu-v2"; 1009 reg = <0x0 0xfdcd0f00 0x0 0x100>; 1010 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1011 interrupt-names = "fec0_mmu"; 1012 clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>; 1013 clock-names = "aclk", "iface"; 1014 power-domains = <&power RK3588_PD_FEC>; 1015 #iommu-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 fec1_mmu: iommu@fdcd8f00 { 1020 compatible = "rockchip,iommu-v2"; 1021 reg = <0x0 0xfdcd8f00 0x0 0x100>; 1022 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1023 interrupt-names = "fec1_mmu"; 1024 clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>; 1025 clock-names = "aclk", "iface"; 1026 power-domains = <&power RK3588_PD_FEC>; 1027 #iommu-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 vop_mmu: iommu@fdd97e00 { 1032 compatible = "rockchip,iommu-v2"; 1033 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1034 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1035 interrupt-names = "vop_mmu"; 1036 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1037 clock-names = "aclk", "iface"; 1038 #iommu-cells = <0>; 1039 rockchip,disable-device-link-resume; 1040 status = "disabled"; 1041 }; 1042 1043 spdif_tx2: spdif-tx@fddb0000 { 1044 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1045 reg = <0x0 0xfddb0000 0x0 0x1000>; 1046 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1047 dmas = <&dmac1 6>; 1048 dma-names = "tx"; 1049 clock-names = "mclk", "hclk"; 1050 clocks = <&cru MCLK_SPDIF2_DP0>, <&cru HCLK_SPDIF2_DP0>; 1051 #sound-dai-cells = <0>; 1052 status = "disabled"; 1053 }; 1054 1055 i2s4_8ch: i2s@fddc0000 { 1056 compatible = "rockchip,rk3588-i2s-tdm"; 1057 reg = <0x0 0xfddc0000 0x0 0x1000>; 1058 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1060 clock-names = "mclk_tx", "hclk"; 1061 dmas = <&dmac2 0>; 1062 dma-names = "tx"; 1063 resets = <&cru SRST_M_I2S4_8CH_TX>; 1064 reset-names = "tx-m"; 1065 #sound-dai-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 spdif_tx3: spdif-tx@fdde0000 { 1070 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1071 reg = <0x0 0xfdde0000 0x0 0x1000>; 1072 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 1073 dmas = <&dmac1 7>; 1074 dma-names = "tx"; 1075 clock-names = "mclk", "hclk"; 1076 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; 1077 #sound-dai-cells = <0>; 1078 status = "disabled"; 1079 }; 1080 1081 i2s5_8ch: i2s@fddf0000 { 1082 compatible = "rockchip,rk3588-i2s-tdm"; 1083 reg = <0x0 0xfddf0000 0x0 0x1000>; 1084 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1086 clock-names = "mclk_tx", "hclk"; 1087 dmas = <&dmac2 2>; 1088 dma-names = "tx"; 1089 resets = <&cru SRST_M_I2S5_8CH_TX>; 1090 reset-names = "tx-m"; 1091 #sound-dai-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 i2s9_8ch: i2s@fddfc000 { 1096 compatible = "rockchip,rk3588-i2s-tdm"; 1097 reg = <0x0 0xfddfc000 0x0 0x1000>; 1098 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1100 clock-names = "mclk_rx", "hclk"; 1101 dmas = <&dmac2 23>; 1102 dma-names = "rx"; 1103 resets = <&cru SRST_M_I2S9_8CH_RX>; 1104 reset-names = "rx-m"; 1105 #sound-dai-cells = <0>; 1106 status = "disabled"; 1107 }; 1108 1109 spdif_rx0: spdif-rx@fde08000 { 1110 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; 1111 reg = <0x0 0xfde08000 0x0 0x1000>; 1112 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>; 1114 clock-names = "mclk", "hclk"; 1115 dmas = <&dmac0 21>; 1116 dma-names = "rx"; 1117 resets = <&cru SRST_M_SPDIFRX0>; 1118 reset-names = "spdifrx-m"; 1119 #sound-dai-cells = <0>; 1120 status = "disabled"; 1121 }; 1122 1123 edp0: edp@fdec0000 { 1124 compatible = "rockchip,rk3588-edp"; 1125 reg = <0x0 0xfdec0000 0x0 0x1000>; 1126 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, 1128 <&cru CLK_EDP0_200M>; 1129 clock-names = "dp", "pclk", "spdif"; 1130 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; 1131 reset-names = "dp", "apb"; 1132 phys = <&hdptxphy0>; 1133 phy-names = "dp"; 1134 power-domains = <&power RK3588_PD_VO1>; 1135 rockchip,grf = <&vo1_grf>; 1136 status = "disabled"; 1137 }; 1138 1139 pcie2x1l1: pcie@fe180000 { 1140 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 1141 #address-cells = <3>; 1142 #size-cells = <2>; 1143 bus-range = <0x30 0x3f>; 1144 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1145 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1146 <&cru CLK_PCIE_AUX3>; 1147 clock-names = "aclk_mst", "aclk_slv", 1148 "aclk_dbi", "pclk", "aux"; 1149 device_type = "pci"; 1150 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1155 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1156 #interrupt-cells = <1>; 1157 interrupt-map-mask = <0 0 0 7>; 1158 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1159 <0 0 0 2 &pcie2x1l1_intc 1>, 1160 <0 0 0 3 &pcie2x1l1_intc 2>, 1161 <0 0 0 4 &pcie2x1l1_intc 3>; 1162 linux,pci-domain = <3>; 1163 num-ib-windows = <8>; 1164 num-ob-windows = <8>; 1165 max-link-speed = <2>; 1166 msi-map = <0x3000 &its 0x3000 0x1000>; 1167 num-lanes = <1>; 1168 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1169 phy-names = "pcie-phy"; 1170 power-domains = <&power RK3588_PD_PHP>; 1171 ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000 1172 0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000 1173 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000 1174 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; 1175 1176 reg = <0xa 0x40c00000 0x0 0x400000>, 1177 <0x0 0xfe180000 0x0 0x10000>; 1178 reg-names = "pcie-dbi", "pcie-apb"; 1179 resets = <&cru SRST_PCIE3_POWER_UP>; 1180 reset-names = "pipe"; 1181 status = "disabled"; 1182 1183 pcie2x1l1_intc: legacy-interrupt-controller { 1184 interrupt-controller; 1185 #address-cells = <0>; 1186 #interrupt-cells = <1>; 1187 interrupt-parent = <&gic>; 1188 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>; 1189 }; 1190 }; 1191 1192 pcie2x1l2: pcie@fe190000 { 1193 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 1194 #address-cells = <3>; 1195 #size-cells = <2>; 1196 bus-range = <0x40 0x4f>; 1197 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1198 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1199 <&cru CLK_PCIE_AUX4>; 1200 clock-names = "aclk_mst", "aclk_slv", 1201 "aclk_dbi", "pclk", "aux"; 1202 device_type = "pci"; 1203 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1208 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1209 #interrupt-cells = <1>; 1210 interrupt-map-mask = <0 0 0 7>; 1211 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1212 <0 0 0 2 &pcie2x1l2_intc 1>, 1213 <0 0 0 3 &pcie2x1l2_intc 2>, 1214 <0 0 0 4 &pcie2x1l2_intc 3>; 1215 linux,pci-domain = <4>; 1216 num-ib-windows = <8>; 1217 num-ob-windows = <8>; 1218 max-link-speed = <2>; 1219 msi-map = <0x4000 &its 0x4000 0x1000>; 1220 num-lanes = <1>; 1221 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1222 phy-names = "pcie-phy"; 1223 power-domains = <&power RK3588_PD_PHP>; 1224 ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 1225 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 1226 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000 1227 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; 1228 reg = <0xa 0x41000000 0x0 0x400000>, 1229 <0x0 0xfe190000 0x0 0x10000>; 1230 reg-names = "pcie-dbi", "pcie-apb"; 1231 resets = <&cru SRST_PCIE4_POWER_UP>; 1232 reset-names = "pipe"; 1233 status = "disabled"; 1234 1235 pcie2x1l2_intc: legacy-interrupt-controller { 1236 interrupt-controller; 1237 #address-cells = <0>; 1238 #interrupt-cells = <1>; 1239 interrupt-parent = <&gic>; 1240 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>; 1241 }; 1242 }; 1243 1244 gmac1: ethernet@fe1c0000 { 1245 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1246 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1247 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1249 interrupt-names = "macirq", "eth_wake_irq"; 1250 rockchip,grf = <&sys_grf>; 1251 rockchip,php_grf = <&php_grf>; 1252 clocks = <&cru CLK_GMAC1>, <&cru ACLK_GMAC1>, 1253 <&cru PCLK_GMAC1>, <&cru CLK_GMAC1_PTP_REF>; 1254 clock-names = "stmmaceth", "aclk_mac", 1255 "pclk_mac", "ptp_ref"; 1256 resets = <&cru SRST_A_GMAC1>; 1257 reset-names = "stmmaceth"; 1258 1259 snps,mixed-burst; 1260 snps,tso; 1261 1262 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1263 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1264 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1265 status = "disabled"; 1266 1267 mdio1: mdio { 1268 compatible = "snps,dwmac-mdio"; 1269 #address-cells = <0x1>; 1270 #size-cells = <0x0>; 1271 }; 1272 1273 gmac1_stmmac_axi_setup: stmmac-axi-config { 1274 snps,wr_osr_lmt = <4>; 1275 snps,rd_osr_lmt = <8>; 1276 snps,blen = <0 0 0 0 16 8 4>; 1277 }; 1278 1279 gmac1_mtl_rx_setup: rx-queues-config { 1280 snps,rx-queues-to-use = <2>; 1281 queue0 {}; 1282 queue1 {}; 1283 }; 1284 1285 gmac1_mtl_tx_setup: tx-queues-config { 1286 snps,tx-queues-to-use = <2>; 1287 queue0 {}; 1288 queue1 {}; 1289 }; 1290 }; 1291 1292 sata0: sata@fe210000 { 1293 compatible = "snps,dwc-ahci"; 1294 reg = <0 0xfe210000 0 0x1000>; 1295 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1296 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>; 1297 clock-names = "sata", "pmalive", "rxoob", "ref"; 1298 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; 1299 interrupt-names = "hostc"; 1300 phys = <&combphy0_ps PHY_TYPE_SATA>; 1301 phy-names = "sata-phy"; 1302 ports-implemented = <0x1>; 1303 power-domains = <&power RK3588_PD_PHP>; 1304 status = "disabled"; 1305 }; 1306 1307 sata2: sata@fe230000 { 1308 compatible = "snps,dwc-ahci"; 1309 reg = <0 0xfe230000 0 0x1000>; 1310 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1311 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>; 1312 clock-names = "sata", "pmalive", "rxoob", "ref"; 1313 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; 1314 interrupt-names = "hostc"; 1315 phys = <&combphy2_psu PHY_TYPE_SATA>; 1316 phy-names = "sata-phy"; 1317 ports-implemented = <0x1>; 1318 power-domains = <&power RK3588_PD_PHP>; 1319 status = "disabled"; 1320 }; 1321 1322 sfc: spi@fe2b0000 { 1323 compatible = "rockchip,sfc"; 1324 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1325 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1327 clock-names = "clk_sfc", "hclk_sfc"; 1328 assigned-clocks = <&cru SCLK_SFC>; 1329 assigned-clock-rates = <100000000>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 sdmmc: mmc@fe2c0000 { 1336 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1337 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1338 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1339 clocks = <&scmi_clk SCMI_CCLK_SD>, <&scmi_clk SCMI_HCLK_SD>, 1340 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1341 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; 1342 fifo-depth = <0x100>; 1343 max-frequency = <200000000>; 1344 pinctrl-names = "default"; 1345 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1346 status = "disabled"; 1347 }; 1348 1349 sdio: mmc@fe2d0000 { 1350 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1351 reg = <0x0 0xfe2d0000 0x0 0x4000>; 1352 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1353 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1354 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1355 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1356 fifo-depth = <0x100>; 1357 max-frequency = <200000000>; 1358 status = "disabled"; 1359 }; 1360 1361 sdhci: mmc@fe2e0000 { 1362 compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci"; 1363 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1364 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1365 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>; 1366 assigned-clock-rates = <200000000>, <24000000>; 1367 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1368 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1369 <&cru TMCLK_EMMC>; 1370 clock-names = "core", "bus", "axi", "block", "timer"; 1371 max-frequency = <200000000>; 1372 status = "disabled"; 1373 }; 1374 1375 i2s0_8ch: i2s@fe470000 { 1376 compatible = "rockchip,rk3588-i2s-tdm"; 1377 reg = <0x0 0xfe470000 0x0 0x1000>; 1378 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 1379 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1380 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1381 dmas = <&dmac0 0>, <&dmac0 1>; 1382 dma-names = "tx", "rx"; 1383 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1384 reset-names = "tx-m", "rx-m"; 1385 pinctrl-names = "default"; 1386 pinctrl-0 = <&i2s0_lrck 1387 &i2s0_sclk 1388 &i2s0_sdi0 1389 &i2s0_sdi1 1390 &i2s0_sdi2 1391 &i2s0_sdi3 1392 &i2s0_sdo0 1393 &i2s0_sdo1 1394 &i2s0_sdo2 1395 &i2s0_sdo3>; 1396 #sound-dai-cells = <0>; 1397 status = "disabled"; 1398 }; 1399 1400 i2s1_8ch: i2s@fe480000 { 1401 compatible = "rockchip,rk3588-i2s-tdm"; 1402 reg = <0x0 0xfe480000 0x0 0x1000>; 1403 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 1404 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1405 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1406 dmas = <&dmac0 2>, <&dmac0 3>; 1407 dma-names = "tx", "rx"; 1408 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1409 reset-names = "tx-m", "rx-m"; 1410 pinctrl-names = "default"; 1411 pinctrl-0 = <&i2s1m0_lrck 1412 &i2s1m0_sclk 1413 &i2s1m0_sdi0 1414 &i2s1m0_sdi1 1415 &i2s1m0_sdi2 1416 &i2s1m0_sdi3 1417 &i2s1m0_sdo0 1418 &i2s1m0_sdo1 1419 &i2s1m0_sdo2 1420 &i2s1m0_sdo3>; 1421 #sound-dai-cells = <0>; 1422 status = "disabled"; 1423 }; 1424 1425 i2s2_2ch: i2s@fe490000 { 1426 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1427 reg = <0x0 0xfe490000 0x0 0x1000>; 1428 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 1429 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1430 clock-names = "i2s_clk", "i2s_hclk"; 1431 dmas = <&dmac1 0>, <&dmac1 1>; 1432 dma-names = "tx", "rx"; 1433 pinctrl-names = "default"; 1434 pinctrl-0 = <&i2s2m1_lrck 1435 &i2s2m1_sclk 1436 &i2s2m1_sdi 1437 &i2s2m1_sdo>; 1438 #sound-dai-cells = <0>; 1439 status = "disabled"; 1440 }; 1441 1442 i2s3_2ch: i2s@fe4a0000 { 1443 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1444 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1445 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1447 clock-names = "i2s_clk", "i2s_hclk"; 1448 dmas = <&dmac1 2>, <&dmac1 3>; 1449 dma-names = "tx", "rx"; 1450 pinctrl-names = "default"; 1451 pinctrl-0 = <&i2s3_lrck 1452 &i2s3_sclk 1453 &i2s3_sdi 1454 &i2s3_sdo>; 1455 #sound-dai-cells = <0>; 1456 status = "disabled"; 1457 }; 1458 1459 pdm0: pdm@fe4b0000 { 1460 compatible = "rockchip,rk3588-pdm"; 1461 reg = <0x0 0xfe4b0000 0x0 0x1000>; 1462 clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>; 1463 clock-names = "pdm_clk", "pdm_hclk"; 1464 dmas = <&dmac0 4>; 1465 dma-names = "rx"; 1466 pinctrl-names = "default"; 1467 pinctrl-0 = <&pdm0m0_clk 1468 &pdm0m0_clk1 1469 &pdm0m0_sdi0 1470 &pdm0m0_sdi1 1471 &pdm0m0_sdi2 1472 &pdm0m0_sdi3>; 1473 #sound-dai-cells = <0>; 1474 status = "disabled"; 1475 }; 1476 1477 pdm1: pdm@fe4c0000 { 1478 compatible = "rockchip,rk3588-pdm"; 1479 reg = <0x0 0xfe4c0000 0x0 0x1000>; 1480 clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>; 1481 clock-names = "pdm_clk", "pdm_hclk"; 1482 dmas = <&dmac1 4>; 1483 dma-names = "rx"; 1484 pinctrl-names = "default"; 1485 pinctrl-0 = <&pdm1m0_clk 1486 &pdm1m0_clk1 1487 &pdm1m0_sdi0 1488 &pdm1m0_sdi1 1489 &pdm1m0_sdi2 1490 &pdm1m0_sdi3>; 1491 #sound-dai-cells = <0>; 1492 status = "disabled"; 1493 }; 1494 1495 vad: vad@fe4d0000 { 1496 compatible = "rockchip,rk3588-vad"; 1497 reg = <0x0 0xfe4d0000 0x0 0x1000>; 1498 reg-names = "vad"; 1499 clocks = <&cru HCLK_VAD>; 1500 clock-names = "hclk"; 1501 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1502 rockchip,audio-src = <0>; 1503 rockchip,det-channel = <0>; 1504 rockchip,mode = <0>; 1505 #sound-dai-cells = <0>; 1506 status = "disabled"; 1507 }; 1508 1509 spdif_tx0: spdif-tx@fe4e0000 { 1510 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1511 reg = <0x0 0xfe4e0000 0x0 0x1000>; 1512 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1513 dmas = <&dmac0 5>; 1514 dma-names = "tx"; 1515 clock-names = "mclk", "hclk"; 1516 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&spdif0m0_tx>; 1519 #sound-dai-cells = <0>; 1520 status = "disabled"; 1521 }; 1522 1523 spdif_tx1: spdif-tx@fe4f0000 { 1524 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1525 reg = <0x0 0xfe4f0000 0x0 0x1000>; 1526 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1527 dmas = <&dmac1 5>; 1528 dma-names = "tx"; 1529 clock-names = "mclk", "hclk"; 1530 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; 1531 pinctrl-names = "default"; 1532 pinctrl-0 = <&spdif1m0_tx>; 1533 #sound-dai-cells = <0>; 1534 status = "disabled"; 1535 }; 1536 1537 acdcdig_dsm: codec-digital@fe500000 { 1538 compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1"; 1539 reg = <0x0 0xfe500000 0x0 0x1000>; 1540 clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>; 1541 clock-names = "dac", "pclk"; 1542 resets = <&cru SRST_DAC_ACDCDIG>; 1543 reset-names = "reset" ; 1544 rockchip,grf = <&sys_grf>; 1545 rockchip,pwm-output-mode; 1546 pinctrl-names = "default"; 1547 pinctrl-0 = <&auddsm_pins>; 1548 #sound-dai-cells = <0>; 1549 status = "disabled"; 1550 }; 1551 1552 hwlock: hwspinlock@fe5a0000 { 1553 compatible = "rockchip,hwspinlock"; 1554 reg = <0 0xfe5a0000 0 0x100>; 1555 #hwlock-cells = <1>; 1556 }; 1557 1558 gic: interrupt-controller@fe600000 { 1559 compatible = "arm,gic-v3"; 1560 #interrupt-cells = <3>; 1561 #address-cells = <2>; 1562 #size-cells = <2>; 1563 ranges; 1564 interrupt-controller; 1565 1566 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1567 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1568 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1569 its: interrupt-controller@fe640000 { 1570 compatible = "arm,gic-v3-its"; 1571 msi-controller; 1572 #msi-cells = <1>; 1573 reg = <0x0 0xfe640000 0x0 0x20000>; 1574 }; 1575 }; 1576 1577 dmac0: dma-controller@fea10000 { 1578 compatible = "arm,pl330", "arm,primecell"; 1579 reg = <0x0 0xfea10000 0x0 0x4000>; 1580 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1582 clocks = <&cru ACLK_DMAC0>; 1583 clock-names = "apb_pclk"; 1584 #dma-cells = <1>; 1585 arm,pl330-periph-burst; 1586 }; 1587 1588 dmac1: dma-controller@fea30000 { 1589 compatible = "arm,pl330", "arm,primecell"; 1590 reg = <0x0 0xfea30000 0x0 0x4000>; 1591 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1593 clocks = <&cru ACLK_DMAC1>; 1594 clock-names = "apb_pclk"; 1595 #dma-cells = <1>; 1596 arm,pl330-periph-burst; 1597 }; 1598 1599 can0: can@fea50000 { 1600 compatible = "rockchip,canfd-1.0"; 1601 reg = <0x0 0xfea50000 0x0 0x1000>; 1602 iinterrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 1603 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 1604 clock-names = "baudclk", "apb_pclk"; 1605 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 1606 reset-names = "can", "can-apb"; 1607 pinctrl-names = "default"; 1608 pinctrl-0 = <&can0m0_pins>; 1609 tx-fifo-depth = <1>; 1610 rx-fifo-depth = <6>; 1611 status = "disabled"; 1612 }; 1613 1614 can1: can@fea60000 { 1615 compatible = "rockchip,canfd-1.0"; 1616 reg = <0x0 0xfea60000 0x0 0x1000>; 1617 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 1618 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 1619 clock-names = "baudclk", "apb_pclk"; 1620 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 1621 reset-names = "can", "can-apb"; 1622 pinctrl-names = "default"; 1623 pinctrl-0 = <&can1m0_pins>; 1624 tx-fifo-depth = <1>; 1625 rx-fifo-depth = <6>; 1626 status = "disabled"; 1627 }; 1628 1629 can2: can@fea70000 { 1630 compatible = "rockchip,canfd-1.0"; 1631 reg = <0x0 0xfea70000 0x0 0x1000>; 1632 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1633 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 1634 clock-names = "baudclk", "apb_pclk"; 1635 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; 1636 reset-names = "can", "can-apb"; 1637 pinctrl-names = "default"; 1638 pinctrl-0 = <&can2m0_pins>; 1639 tx-fifo-depth = <1>; 1640 rx-fifo-depth = <6>; 1641 status = "disabled"; 1642 }; 1643 1644 hw_decompress: decompress@fea80000 { 1645 compatible = "rockchip,hw-decompress"; 1646 reg = <0x0 0xfea80000 0x0 0x1000>; 1647 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1648 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 1649 clock-names = "aclk", "dclk", "pclk"; 1650 resets = <&cru SRST_D_DECOM>; 1651 reset-names = "dresetn"; 1652 status = "disabled"; 1653 }; 1654 1655 i2c1: i2c@fea90000 { 1656 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1657 reg = <0x0 0xfea90000 0x0 0x1000>; 1658 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1659 clock-names = "i2c", "pclk"; 1660 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 1661 pinctrl-names = "default"; 1662 pinctrl-0 = <&i2c1m0_xfer>; 1663 #address-cells = <1>; 1664 #size-cells = <0>; 1665 status = "disabled"; 1666 }; 1667 1668 i2c2: i2c@feaa0000 { 1669 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1670 reg = <0x0 0xfeaa0000 0x0 0x1000>; 1671 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1672 clock-names = "i2c", "pclk"; 1673 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 1674 pinctrl-names = "default"; 1675 pinctrl-0 = <&i2c2m0_xfer>; 1676 #address-cells = <1>; 1677 #size-cells = <0>; 1678 status = "disabled"; 1679 }; 1680 1681 i2c3: i2c@feab0000 { 1682 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1683 reg = <0x0 0xfeab0000 0x0 0x1000>; 1684 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1685 clock-names = "i2c", "pclk"; 1686 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&i2c3m0_xfer>; 1689 #address-cells = <1>; 1690 #size-cells = <0>; 1691 status = "disabled"; 1692 }; 1693 1694 i2c4: i2c@feac0000 { 1695 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1696 reg = <0x0 0xfeac0000 0x0 0x1000>; 1697 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1698 clock-names = "i2c", "pclk"; 1699 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1700 pinctrl-names = "default"; 1701 pinctrl-0 = <&i2c4m0_xfer>; 1702 #address-cells = <1>; 1703 #size-cells = <0>; 1704 status = "disabled"; 1705 }; 1706 1707 i2c5: i2c@fead0000 { 1708 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1709 reg = <0x0 0xfead0000 0x0 0x1000>; 1710 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1711 clock-names = "i2c", "pclk"; 1712 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; 1713 pinctrl-names = "default"; 1714 pinctrl-0 = <&i2c5m0_xfer>; 1715 #address-cells = <1>; 1716 #size-cells = <0>; 1717 status = "disabled"; 1718 }; 1719 1720 rktimer: timer@feae0000 { 1721 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 1722 reg = <0x0 0xfeae0000 0x0 0x20>; 1723 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 1724 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 1725 clock-names = "pclk", "timer"; 1726 }; 1727 1728 wdt: watchdog@feaf0000 { 1729 compatible = "snps,dw-wdt"; 1730 reg = <0x0 0xfeaf0000 0x0 0x100>; 1731 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1732 clock-names = "tclk", "pclk"; 1733 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1734 status = "disabled"; 1735 }; 1736 1737 spi0: spi@feb00000 { 1738 compatible = "rockchip,rk3066-spi"; 1739 reg = <0x0 0xfeb00000 0x0 0x1000>; 1740 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1744 clock-names = "spiclk", "apb_pclk"; 1745 dmas = <&dmac0 14>, <&dmac0 15>; 1746 dma-names = "tx", "rx"; 1747 pinctrl-names = "default", "high_speed"; 1748 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1749 pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>; 1750 num-cs = <2>; 1751 status = "disabled"; 1752 }; 1753 1754 spi1: spi@feb10000 { 1755 compatible = "rockchip,rk3066-spi"; 1756 reg = <0x0 0xfeb10000 0x0 0x1000>; 1757 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1758 #address-cells = <1>; 1759 #size-cells = <0>; 1760 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1761 clock-names = "spiclk", "apb_pclk"; 1762 dmas = <&dmac0 16>, <&dmac0 17>; 1763 dma-names = "tx", "rx"; 1764 pinctrl-names = "default", "high_speed"; 1765 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 1766 pinctrl-1 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins_hs>; 1767 num-cs = <2>; 1768 status = "disabled"; 1769 }; 1770 1771 spi2: spi@feb20000 { 1772 compatible = "rockchip,rk3066-spi"; 1773 reg = <0x0 0xfeb20000 0x0 0x1000>; 1774 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1775 #address-cells = <1>; 1776 #size-cells = <0>; 1777 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1778 clock-names = "spiclk", "apb_pclk"; 1779 dmas = <&dmac1 15>, <&dmac1 16>; 1780 dma-names = "tx", "rx"; 1781 pinctrl-names = "default", "high_speed"; 1782 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1783 pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>; 1784 num-cs = <2>; 1785 status = "disabled"; 1786 }; 1787 1788 spi3: spi@feb30000 { 1789 compatible = "rockchip,rk3066-spi"; 1790 reg = <0x0 0xfeb30000 0x0 0x1000>; 1791 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1792 #address-cells = <1>; 1793 #size-cells = <0>; 1794 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1795 clock-names = "spiclk", "apb_pclk"; 1796 dmas = <&dmac1 17>, <&dmac1 18>; 1797 dma-names = "tx", "rx"; 1798 pinctrl-names = "default", "high_speed"; 1799 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 1800 pinctrl-1 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins_hs>; 1801 num-cs = <2>; 1802 status = "disabled"; 1803 }; 1804 1805 uart1: serial@feb40000 { 1806 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1807 reg = <0x0 0xfeb40000 0x0 0x100>; 1808 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1809 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1810 clock-names = "baudclk", "apb_pclk"; 1811 reg-shift = <2>; 1812 reg-io-width = <4>; 1813 dmas = <&dmac0 8>, <&dmac0 9>; 1814 pinctrl-names = "default"; 1815 pinctrl-0 = <&uart1m0_xfer>; 1816 status = "disabled"; 1817 }; 1818 1819 uart2: serial@feb50000 { 1820 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1821 reg = <0x0 0xfeb50000 0x0 0x100>; 1822 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 1823 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1824 clock-names = "baudclk", "apb_pclk"; 1825 reg-shift = <2>; 1826 reg-io-width = <4>; 1827 dmas = <&dmac0 10>, <&dmac0 11>; 1828 pinctrl-names = "default"; 1829 pinctrl-0 = <&uart2m0_xfer>; 1830 status = "disabled"; 1831 }; 1832 1833 uart3: serial@feb60000 { 1834 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1835 reg = <0x0 0xfeb60000 0x0 0x100>; 1836 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 1837 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1838 clock-names = "baudclk", "apb_pclk"; 1839 reg-shift = <2>; 1840 reg-io-width = <4>; 1841 dmas = <&dmac0 12>, <&dmac0 13>; 1842 pinctrl-names = "default"; 1843 pinctrl-0 = <&uart3m0_xfer>; 1844 status = "disabled"; 1845 }; 1846 1847 uart4: serial@feb70000 { 1848 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1849 reg = <0x0 0xfeb70000 0x0 0x100>; 1850 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1851 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1852 clock-names = "baudclk", "apb_pclk"; 1853 reg-shift = <2>; 1854 reg-io-width = <4>; 1855 dmas = <&dmac1 9>, <&dmac1 10>; 1856 pinctrl-names = "default"; 1857 pinctrl-0 = <&uart4m0_xfer>; 1858 status = "disabled"; 1859 }; 1860 1861 uart5: serial@feb80000 { 1862 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1863 reg = <0x0 0xfeb80000 0x0 0x100>; 1864 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 1865 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1866 clock-names = "baudclk", "apb_pclk"; 1867 reg-shift = <2>; 1868 reg-io-width = <4>; 1869 dmas = <&dmac1 11>, <&dmac1 12>; 1870 pinctrl-names = "default"; 1871 pinctrl-0 = <&uart5m0_xfer>; 1872 status = "disabled"; 1873 }; 1874 1875 uart6: serial@feb90000 { 1876 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1877 reg = <0x0 0xfeb90000 0x0 0x100>; 1878 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 1879 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1880 clock-names = "baudclk", "apb_pclk"; 1881 reg-shift = <2>; 1882 reg-io-width = <4>; 1883 dmas = <&dmac1 13>, <&dmac1 14>; 1884 pinctrl-names = "default"; 1885 pinctrl-0 = <&uart6m0_xfer>; 1886 status = "disabled"; 1887 }; 1888 1889 uart7: serial@feba0000 { 1890 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1891 reg = <0x0 0xfeba0000 0x0 0x100>; 1892 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 1893 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1894 clock-names = "baudclk", "apb_pclk"; 1895 reg-shift = <2>; 1896 reg-io-width = <4>; 1897 dmas = <&dmac2 7>, <&dmac2 8>; 1898 pinctrl-names = "default"; 1899 pinctrl-0 = <&uart7m0_xfer>; 1900 status = "disabled"; 1901 }; 1902 1903 uart8: serial@febb0000 { 1904 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1905 reg = <0x0 0xfebb0000 0x0 0x100>; 1906 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 1907 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1908 clock-names = "baudclk", "apb_pclk"; 1909 reg-shift = <2>; 1910 reg-io-width = <4>; 1911 dmas = <&dmac2 9>, <&dmac2 10>; 1912 pinctrl-names = "default"; 1913 pinctrl-0 = <&uart8m0_xfer>; 1914 status = "disabled"; 1915 }; 1916 1917 uart9: serial@febc0000 { 1918 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1919 reg = <0x0 0xfebc0000 0x0 0x100>; 1920 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 1921 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1922 clock-names = "baudclk", "apb_pclk"; 1923 reg-shift = <2>; 1924 reg-io-width = <4>; 1925 dmas = <&dmac2 11>, <&dmac2 12>; 1926 pinctrl-names = "default"; 1927 pinctrl-0 = <&uart9m0_xfer>; 1928 status = "disabled"; 1929 }; 1930 1931 pwm4: pwm@febd0000 { 1932 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1933 reg = <0x0 0xfebd0000 0x0 0x10>; 1934 #pwm-cells = <3>; 1935 pinctrl-names = "active"; 1936 pinctrl-0 = <&pwm4m0_pins>; 1937 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1938 clock-names = "pwm", "pclk"; 1939 status = "disabled"; 1940 }; 1941 1942 pwm5: pwm@febd0010 { 1943 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1944 reg = <0x0 0xfebd0010 0x0 0x10>; 1945 #pwm-cells = <3>; 1946 pinctrl-names = "active"; 1947 pinctrl-0 = <&pwm5m0_pins>; 1948 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1949 clock-names = "pwm", "pclk"; 1950 status = "disabled"; 1951 }; 1952 1953 pwm6: pwm@febd0020 { 1954 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1955 reg = <0x0 0xfebd0020 0x0 0x10>; 1956 #pwm-cells = <3>; 1957 pinctrl-names = "active"; 1958 pinctrl-0 = <&pwm6m0_pins>; 1959 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1960 clock-names = "pwm", "pclk"; 1961 status = "disabled"; 1962 }; 1963 1964 pwm7: pwm@febd0030 { 1965 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1966 reg = <0x0 0xfebd0030 0x0 0x10>; 1967 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 1969 #pwm-cells = <3>; 1970 pinctrl-names = "active"; 1971 pinctrl-0 = <&pwm7m0_pins>; 1972 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1973 clock-names = "pwm", "pclk"; 1974 status = "disabled"; 1975 }; 1976 1977 pwm8: pwm@febe0000 { 1978 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1979 reg = <0x0 0xfebe0000 0x0 0x10>; 1980 #pwm-cells = <3>; 1981 pinctrl-names = "active"; 1982 pinctrl-0 = <&pwm8m0_pins>; 1983 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1984 clock-names = "pwm", "pclk"; 1985 status = "disabled"; 1986 }; 1987 1988 pwm9: pwm@febe0010 { 1989 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1990 reg = <0x0 0xfebe0010 0x0 0x10>; 1991 #pwm-cells = <3>; 1992 pinctrl-names = "active"; 1993 pinctrl-0 = <&pwm9m0_pins>; 1994 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1995 clock-names = "pwm", "pclk"; 1996 status = "disabled"; 1997 }; 1998 1999 pwm10: pwm@febe0020 { 2000 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2001 reg = <0x0 0xfebe0020 0x0 0x10>; 2002 #pwm-cells = <3>; 2003 pinctrl-names = "active"; 2004 pinctrl-0 = <&pwm10m0_pins>; 2005 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2006 clock-names = "pwm", "pclk"; 2007 status = "disabled"; 2008 }; 2009 2010 pwm11: pwm@febe0030 { 2011 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2012 reg = <0x0 0xfebe0030 0x0 0x10>; 2013 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 2015 #pwm-cells = <3>; 2016 pinctrl-names = "active"; 2017 pinctrl-0 = <&pwm11m0_pins>; 2018 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2019 clock-names = "pwm", "pclk"; 2020 status = "disabled"; 2021 }; 2022 2023 pwm12: pwm@febf0000 { 2024 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2025 reg = <0x0 0xfebf0000 0x0 0x10>; 2026 #pwm-cells = <3>; 2027 pinctrl-names = "active"; 2028 pinctrl-0 = <&pwm12m0_pins>; 2029 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2030 clock-names = "pwm", "pclk"; 2031 status = "disabled"; 2032 }; 2033 2034 pwm13: pwm@febf0010 { 2035 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2036 reg = <0x0 0xfebf0010 0x0 0x10>; 2037 #pwm-cells = <3>; 2038 pinctrl-names = "active"; 2039 pinctrl-0 = <&pwm13m0_pins>; 2040 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2041 clock-names = "pwm", "pclk"; 2042 status = "disabled"; 2043 }; 2044 2045 pwm14: pwm@febf0020 { 2046 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2047 reg = <0x0 0xfebf0020 0x0 0x10>; 2048 #pwm-cells = <3>; 2049 pinctrl-names = "active"; 2050 pinctrl-0 = <&pwm14m0_pins>; 2051 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2052 clock-names = "pwm", "pclk"; 2053 status = "disabled"; 2054 }; 2055 2056 pwm15: pwm@febf0030 { 2057 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2058 reg = <0x0 0xfebf0030 0x0 0x10>; 2059 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 2061 #pwm-cells = <3>; 2062 pinctrl-names = "active"; 2063 pinctrl-0 = <&pwm15m0_pins>; 2064 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2065 clock-names = "pwm", "pclk"; 2066 status = "disabled"; 2067 }; 2068 2069 tsadc: tsadc@fec00000 { 2070 compatible = "rockchip,rk3588-tsadc"; 2071 reg = <0x0 0xfec00000 0x0 0x400>; 2072 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 2073 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2074 clock-names = "tsadc", "apb_pclk"; 2075 assigned-clocks = <&cru CLK_TSADC>; 2076 assigned-clock-rates = <2000000>; 2077 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; 2078 reset-names = "tsadc", "tsadc-apb"; 2079 #thermal-sensor-cells = <1>; 2080 rockchip,hw-tshut-temp = <120000>; 2081 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 2082 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2083 pinctrl-names = "gpio", "otpout"; 2084 pinctrl-0 = <&tsadc_gpio_func>; 2085 pinctrl-1 = <&tsadc_shut_org>; 2086 status = "disabled"; 2087 }; 2088 2089 saradc: saradc@fec10000 { 2090 compatible = "rockchip,rk3588-saradc"; 2091 reg = <0x0 0xfec10000 0x0 0x10000>; 2092 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; 2093 #io-channel-cells = <1>; 2094 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2095 clock-names = "saradc", "apb_pclk"; 2096 resets = <&cru SRST_P_SARADC>; 2097 reset-names = "saradc-apb"; 2098 status = "disabled"; 2099 }; 2100 2101 mailbox0: mailbox@fec60000 { 2102 compatible = "rockchip,rk3588-mailbox", 2103 "rockchip,rk3368-mailbox"; 2104 reg = <0x0 0xfec60000 0x0 0x200>; 2105 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 2109 clocks = <&cru PCLK_MAILBOX0>; 2110 clock-names = "pclk_mailbox"; 2111 #mbox-cells = <1>; 2112 status = "disabled"; 2113 }; 2114 2115 mailbox1: mailbox@fec70000 { 2116 compatible = "rockchip,rk3588-mailbox", 2117 "rockchip,rk3368-mailbox"; 2118 reg = <0x0 0xfec70000 0x0 0x200>; 2119 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2123 clocks = <&cru PCLK_MAILBOX1>; 2124 clock-names = "pclk_mailbox"; 2125 #mbox-cells = <1>; 2126 status = "disabled"; 2127 }; 2128 2129 i2c6: i2c@fec80000 { 2130 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2131 reg = <0x0 0xfec80000 0x0 0x1000>; 2132 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2133 clock-names = "i2c", "pclk"; 2134 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 2135 pinctrl-names = "default"; 2136 pinctrl-0 = <&i2c6m0_xfer>; 2137 #address-cells = <1>; 2138 #size-cells = <0>; 2139 status = "disabled"; 2140 }; 2141 2142 i2c7: i2c@fec90000 { 2143 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2144 reg = <0x0 0xfec90000 0x0 0x1000>; 2145 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2146 clock-names = "i2c", "pclk"; 2147 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 2148 pinctrl-names = "default"; 2149 pinctrl-0 = <&i2c7m0_xfer>; 2150 #address-cells = <1>; 2151 #size-cells = <0>; 2152 status = "disabled"; 2153 }; 2154 2155 i2c8: i2c@feca0000 { 2156 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2157 reg = <0x0 0xfeca0000 0x0 0x1000>; 2158 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2159 clock-names = "i2c", "pclk"; 2160 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 2161 pinctrl-names = "default"; 2162 pinctrl-0 = <&i2c8m0_xfer>; 2163 #address-cells = <1>; 2164 #size-cells = <0>; 2165 status = "disabled"; 2166 }; 2167 2168 spi4: spi@fecb0000 { 2169 compatible = "rockchip,rk3066-spi"; 2170 reg = <0x0 0xfecb0000 0x0 0x1000>; 2171 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2172 #address-cells = <1>; 2173 #size-cells = <0>; 2174 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2175 clock-names = "spiclk", "apb_pclk"; 2176 dmas = <&dmac2 13>, <&dmac2 14>; 2177 dma-names = "tx", "rx"; 2178 pinctrl-names = "default", "high_speed"; 2179 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2180 pinctrl-1 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins_hs>; 2181 num-cs = <2>; 2182 status = "disabled"; 2183 }; 2184 2185 otp: otp@fecc0000 { 2186 compatible = "rockchip,rk3588-otp"; 2187 reg = <0x0 0xfecc0000 0x0 0x400>; 2188 #address-cells = <1>; 2189 #size-cells = <1>; 2190 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2191 <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>; 2192 clock-names = "otpc", "apb", "arb", "phy"; 2193 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2194 <&cru SRST_OTPC_ARB>; 2195 reset-names = "otpc", "apb", "arb"; 2196 }; 2197 2198 mailbox2: mailbox@fece0000 { 2199 compatible = "rockchip,rk3588-mailbox", 2200 "rockchip,rk3368-mailbox"; 2201 reg = <0x0 0xfece0000 0x0 0x200>; 2202 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2206 clocks = <&cru PCLK_MAILBOX2>; 2207 clock-names = "pclk_mailbox"; 2208 #mbox-cells = <1>; 2209 status = "disabled"; 2210 }; 2211 2212 dmac2: dma-controller@fed10000 { 2213 compatible = "arm,pl330", "arm,primecell"; 2214 reg = <0x0 0xfed10000 0x0 0x4000>; 2215 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2217 clocks = <&cru ACLK_DMAC2>; 2218 clock-names = "apb_pclk"; 2219 #dma-cells = <1>; 2220 arm,pl330-periph-burst; 2221 }; 2222 2223 hdptxphy0: phy@fed60000 { 2224 compatible = "rockchip,rk3588-hdptx-phy"; 2225 reg = <0x0 0xfed60000 0x0 0x2000>; 2226 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 2227 clock-names = "ref", "apb"; 2228 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 2229 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 2230 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 2231 <&cru SRST_HDPTX0_LCPLL>; 2232 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 2233 "lcpll"; 2234 rockchip,grf = <&hdptxphy0_grf>; 2235 #phy-cells = <0>; 2236 status = "disabled"; 2237 }; 2238 2239 usbdp_phy0: phy@fed80000 { 2240 compatible = "rockchip,rk3588-usbdp-phy"; 2241 reg = <0x0 0xfed80000 0x0 0x10000>; 2242 rockchip,usb-grf = <&usb_grf>; 2243 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 2244 rockchip,vo-grf = <&vo0_grf>; 2245 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 2246 <&cru CLK_USBDP_PHY0_IMMORTAL>, 2247 <&cru PCLK_USBDPPHY0>; 2248 clock-names = "refclk", "immortal", "pclk"; 2249 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 2250 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 2251 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 2252 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 2253 <&cru SRST_P_USBDPPHY0>; 2254 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2255 status = "disabled"; 2256 2257 usbdp_phy0_dp: dp-port { 2258 #phy-cells = <0>; 2259 status = "disabled"; 2260 }; 2261 2262 usbdp_phy0_u3: u3-port { 2263 #phy-cells = <0>; 2264 status = "disabled"; 2265 }; 2266 }; 2267 2268 combphy0_ps: phy@fee00000 { 2269 compatible = "rockchip,rk3588-naneng-combphy"; 2270 reg = <0x0 0xfee00000 0x0 0x100>; 2271 #phy-cells = <1>; 2272 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>; 2273 clock-names = "refclk", "apbclk"; 2274 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 2275 assigned-clock-rates = <100000000>; 2276 resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>; 2277 reset-names = "combphy-apb", "combphy"; 2278 rockchip,pipe-grf = <&php_grf>; 2279 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2280 status = "disabled"; 2281 }; 2282 2283 combphy2_psu: phy@fee20000 { 2284 compatible = "rockchip,rk3588-naneng-combphy"; 2285 reg = <0x0 0xfee20000 0x0 0x100>; 2286 #phy-cells = <1>; 2287 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>; 2288 clock-names = "refclk", "apbclk"; 2289 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 2290 assigned-clock-rates = <100000000>; 2291 resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>; 2292 reset-names = "combphy-apb", "combphy"; 2293 rockchip,pipe-grf = <&php_grf>; 2294 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 2295 rockchip,pcie1ln-sel-bits = <0x100 1 1 0>; 2296 status = "disabled"; 2297 }; 2298 2299 pinctrl: pinctrl { 2300 compatible = "rockchip,rk3588-pinctrl"; 2301 rockchip,grf = <&ioc>; 2302 #address-cells = <2>; 2303 #size-cells = <2>; 2304 ranges; 2305 2306 gpio0: gpio@fd8a0000 { 2307 compatible = "rockchip,gpio-bank"; 2308 reg = <0x0 0xfd8a0000 0x0 0x100>; 2309 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 2310 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2311 2312 gpio-controller; 2313 #gpio-cells = <2>; 2314 gpio-ranges = <&pinctrl 0 0 32>; 2315 interrupt-controller; 2316 #interrupt-cells = <2>; 2317 }; 2318 2319 gpio1: gpio@fec20000 { 2320 compatible = "rockchip,gpio-bank"; 2321 reg = <0x0 0xfec20000 0x0 0x100>; 2322 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 2323 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2324 2325 gpio-controller; 2326 #gpio-cells = <2>; 2327 gpio-ranges = <&pinctrl 0 32 32>; 2328 interrupt-controller; 2329 #interrupt-cells = <2>; 2330 }; 2331 2332 gpio2: gpio@fec30000 { 2333 compatible = "rockchip,gpio-bank"; 2334 reg = <0x0 0xfec30000 0x0 0x100>; 2335 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; 2336 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2337 2338 gpio-controller; 2339 #gpio-cells = <2>; 2340 gpio-ranges = <&pinctrl 0 64 32>; 2341 interrupt-controller; 2342 #interrupt-cells = <2>; 2343 }; 2344 2345 gpio3: gpio@fec40000 { 2346 compatible = "rockchip,gpio-bank"; 2347 reg = <0x0 0xfec40000 0x0 0x100>; 2348 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 2349 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2350 2351 gpio-controller; 2352 #gpio-cells = <2>; 2353 gpio-ranges = <&pinctrl 0 96 32>; 2354 interrupt-controller; 2355 #interrupt-cells = <2>; 2356 }; 2357 2358 gpio4: gpio@fec50000 { 2359 compatible = "rockchip,gpio-bank"; 2360 reg = <0x0 0xfec50000 0x0 0x100>; 2361 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; 2362 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2363 2364 gpio-controller; 2365 #gpio-cells = <2>; 2366 gpio-ranges = <&pinctrl 0 128 32>; 2367 interrupt-controller; 2368 #interrupt-cells = <2>; 2369 }; 2370 }; 2371}; 2372 2373#include "rk3588s-pinctrl.dtsi" 2374