1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rk3588-power.h> 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 compatible = "rockchip,rk3588"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 ethernet1 = &gmac1; 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 i2c4 = &i2c4; 27 i2c5 = &i2c5; 28 i2c6 = &i2c6; 29 i2c7 = &i2c7; 30 i2c8 = &i2c8; 31 serial0 = &uart0; 32 serial1 = &uart1; 33 serial2 = &uart2; 34 serial3 = &uart3; 35 serial4 = &uart4; 36 serial5 = &uart5; 37 serial6 = &uart6; 38 serial7 = &uart7; 39 serial8 = &uart8; 40 serial9 = &uart9; 41 spi0 = &spi0; 42 spi1 = &spi1; 43 spi2 = &spi2; 44 spi3 = &spi3; 45 spi4 = &spi4; 46 spi5 = &sfc; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu-map { 54 cluster0 { 55 core0 { 56 cpu = <&cpu_l0>; 57 }; 58 core1 { 59 cpu = <&cpu_l1>; 60 }; 61 core2 { 62 cpu = <&cpu_l2>; 63 }; 64 core3 { 65 cpu = <&cpu_l3>; 66 }; 67 }; 68 cluster1 { 69 core0 { 70 cpu = <&cpu_b0>; 71 }; 72 core1 { 73 cpu = <&cpu_b1>; 74 }; 75 }; 76 cluster2 { 77 core0 { 78 cpu = <&cpu_b2>; 79 }; 80 core1 { 81 cpu = <&cpu_b3>; 82 }; 83 }; 84 }; 85 86 cpu_l0: cpu@0 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a55"; 89 reg = <0x0>; 90 enable-method = "psci"; 91 capacity-dmips-mhz = <530>; 92 }; 93 94 cpu_l1: cpu@100 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a55"; 97 reg = <0x100>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <530>; 100 }; 101 102 cpu_l2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a55"; 105 reg = <0x200>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <530>; 108 }; 109 110 cpu_l3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 capacity-dmips-mhz = <530>; 116 }; 117 118 cpu_b0: cpu@400 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a76"; 121 reg = <0x400>; 122 enable-method = "psci"; 123 capacity-dmips-mhz = <1024>; 124 }; 125 126 cpu_b1: cpu@500 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a76"; 129 reg = <0x500>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <1024>; 132 }; 133 134 cpu_b2: cpu@600 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a76"; 137 reg = <0x600>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 }; 141 142 cpu_b3: cpu@700 { 143 device_type = "cpu"; 144 compatible = "arm,cortex-a76"; 145 reg = <0x700>; 146 enable-method = "psci"; 147 capacity-dmips-mhz = <1024>; 148 }; 149 }; 150 151 arm_pmu: arm-pmu { 152 compatible = "arm,armv8-pmuv3"; 153 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_LOW>; 154 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>, 155 <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 156 }; 157 158 firmware: firmware { 159 optee: optee { 160 compatible = "linaro,optee-tz"; 161 method = "smc"; 162 }; 163 164 scmi: scmi { 165 compatible = "arm,scmi-smc"; 166 shmem = <&scmi_shmem>; 167 arm,smc-id = <0x82000010>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 scmi_clk: protocol@14 { 172 reg = <0x14>; 173 #clock-cells = <1>; 174 175 assigned-clocks = <&scmi_clk SCMI_SPLL>; 176 assigned-clock-rates = <700000000>; 177 }; 178 179 scmi_reset: protocol@16 { 180 reg = <0x16>; 181 #reset-cells = <1>; 182 }; 183 }; 184 185 sdei: sdei { 186 compatible = "arm,sdei-1.0"; 187 method = "smc"; 188 }; 189 }; 190 191 psci: psci { 192 compatible = "arm,psci-1.0"; 193 method = "smc"; 194 }; 195 196 spll: spll { 197 compatible = "fixed-clock"; 198 #clock-cells = <0>; 199 clock-frequency = <702000000>; 200 clock-output-names = "spll"; 201 }; 202 203 timer { 204 compatible = "arm,armv8-timer"; 205 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 207 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 209 }; 210 211 xin32k: xin32k { 212 compatible = "fixed-clock"; 213 #clock-cells = <0>; 214 clock-frequency = <32768>; 215 clock-output-names = "xin32k"; 216 }; 217 218 xin24m: xin24m { 219 compatible = "fixed-clock"; 220 #clock-cells = <0>; 221 clock-frequency = <24000000>; 222 clock-output-names = "xin24m"; 223 }; 224 225 sram: sram@10f000 { 226 compatible = "mmio-sram"; 227 reg = <0x0 0x0010f000 0x0 0x100>; 228 #address-cells = <1>; 229 #size-cells = <1>; 230 ranges = <0 0x0 0x0010f000 0x100>; 231 232 scmi_shmem: scmi_shmem@0 { 233 compatible = "arm,scmi-shmem"; 234 reg = <0x0 0x100>; 235 }; 236 }; 237 238 usbdrd3_0: usbdrd3_0 { 239 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 240 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 241 <&cru ACLK_USB3OTG0>; 242 clock-names = "ref", "suspend", "bus"; 243 #address-cells = <2>; 244 #size-cells = <2>; 245 ranges; 246 status = "disabled"; 247 248 usbdrd_dwc3_0: usb@fc000000 { 249 compatible = "snps,dwc3"; 250 reg = <0x0 0xfc000000 0x0 0x400000>; 251 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 252 power-domains = <&power RK3588_PD_USB>; 253 resets = <&cru SRST_A_USB3OTG0>; 254 reset-names = "usb3-otg"; 255 dr_mode = "otg"; 256 phys = <&u2phy0_otg>; 257 phy-names = "usb2-phy"; 258 phy_type = "utmi_wide"; 259 snps,dis_enblslpm_quirk; 260 snps,dis-u1-entry-quirk; 261 snps,dis-u2-entry-quirk; 262 snps,dis-u2-freeclk-exists-quirk; 263 snps,dis-del-phy-power-chg-quirk; 264 snps,dis-tx-ipgap-linecheck-quirk; 265 status = "disabled"; 266 }; 267 }; 268 269 usb_host0_ehci: usb@fc800000 { 270 compatible = "generic-ehci"; 271 reg = <0x0 0xfc800000 0x0 0x40000>; 272 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; 274 clock-names = "usbhost", "arbiter"; 275 phys = <&u2phy2_host>; 276 phy-names = "usb2-phy"; 277 power-domains = <&power RK3588_PD_USB>; 278 status = "disabled"; 279 }; 280 281 usb_host0_ohci: usb@fc840000 { 282 compatible = "generic-ohci"; 283 reg = <0x0 0xfc840000 0x0 0x40000>; 284 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; 286 clock-names = "usbhost", "arbiter"; 287 phys = <&u2phy2_host>; 288 phy-names = "usb2-phy"; 289 power-domains = <&power RK3588_PD_USB>; 290 status = "disabled"; 291 }; 292 293 usb_host1_ehci: usb@fc880000 { 294 compatible = "generic-ehci"; 295 reg = <0x0 0xfc880000 0x0 0x40000>; 296 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; 298 clock-names = "usbhost", "arbiter"; 299 phys = <&u2phy3_host>; 300 phy-names = "usb2-phy"; 301 power-domains = <&power RK3588_PD_USB>; 302 status = "disabled"; 303 }; 304 305 usb_host1_ohci: usb@fc8c0000 { 306 compatible = "generic-ohci"; 307 reg = <0x0 0xfc8c0000 0x0 0x40000>; 308 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; 310 clock-names = "usbhost", "arbiter"; 311 phys = <&u2phy3_host>; 312 phy-names = "usb2-phy"; 313 power-domains = <&power RK3588_PD_USB>; 314 status = "disabled"; 315 }; 316 317 mmu600_pcie: iommu@fc900000 { 318 compatible = "arm,smmu-v3"; 319 reg = <0x0 0xfc900000 0x0 0x200000>; 320 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 324 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 325 #iommu-cells = <1>; 326 status = "disabled"; 327 }; 328 329 mmu600_php: iommu@fcb00000 { 330 compatible = "arm,smmu-v3"; 331 reg = <0x0 0xfcb00000 0x0 0x200000>; 332 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 336 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 337 #iommu-cells = <1>; 338 status = "disabled"; 339 }; 340 341 usbhost3_0: usbhost3_0 { 342 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 343 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 344 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>; 345 clock-names = "ref", "suspend", "bus", "utmi"; 346 #address-cells = <2>; 347 #size-cells = <2>; 348 ranges; 349 status = "disabled"; 350 351 usbhost_dwc3_0: usb@fcd00000 { 352 compatible = "snps,dwc3"; 353 reg = <0x0 0xfcd00000 0x0 0x400000>; 354 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 355 power-domains = <&power RK3588_PD_PHP>; 356 resets = <&cru SRST_A_USB3OTG2>; 357 reset-names = "usb3-host"; 358 dr_mode = "host"; 359 phy_type = "utmi_wide"; 360 snps,dis_enblslpm_quirk; 361 snps,dis-u2-freeclk-exists-quirk; 362 snps,dis-del-phy-power-chg-quirk; 363 snps,dis-tx-ipgap-linecheck-quirk; 364 status = "disabled"; 365 }; 366 }; 367 368 sys_grf: syscon@fd58c000 { 369 compatible = "rockchip,rk3588-sys-grf", "syscon"; 370 reg = <0x0 0xfd58c000 0x0 0x1000>; 371 }; 372 373 vo0_grf: syscon@fd5a6000 { 374 compatible = "rockchip,rk3588-vo-grf", "syscon"; 375 reg = <0x0 0xfd5a6000 0x0 0x2000>; 376 }; 377 378 vo1_grf: syscon@fd5a8000 { 379 compatible = "rockchip,rk3588-vo-grf", "syscon"; 380 reg = <0x0 0xfd5a8000 0x0 0x100>; 381 }; 382 383 usb_grf: syscon@fd5ac000 { 384 compatible = "rockchip,rk3588-usb-grf", "syscon"; 385 reg = <0x0 0xfd5ac000 0x0 0x4000>; 386 }; 387 388 php_grf: syscon@fd5b0000 { 389 compatible = "rockchip,rk3588-php-grf", "syscon"; 390 reg = <0x0 0xfd5b0000 0x0 0x1000>; 391 }; 392 393 pipe_phy0_grf: syscon@fd5bc000 { 394 compatible = "rockchip,pipe-phy-grf", "syscon"; 395 reg = <0x0 0xfd5bc000 0x0 0x100>; 396 }; 397 398 pipe_phy2_grf: syscon@fd5c4000 { 399 compatible = "rockchip,pipe-phy-grf", "syscon"; 400 reg = <0x0 0xfd5c4000 0x0 0x100>; 401 }; 402 403 usbdpphy0_grf: syscon@fd5c8000 { 404 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 405 reg = <0x0 0xfd5c8000 0x0 0x4000>; 406 }; 407 408 usb2phy0_grf: syscon@fd5d0000 { 409 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 410 "simple-mfd"; 411 reg = <0x0 0xfd5d0000 0x0 0x4000>; 412 #address-cells = <1>; 413 #size-cells = <1>; 414 415 u2phy0: usb2-phy@0 { 416 compatible = "rockchip,rk3588-usb2phy"; 417 reg = <0x0 0x10>; 418 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; 419 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 420 reset-names = "phy", "apb"; 421 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 422 clock-names = "phyclk"; 423 #clock-cells = <0>; 424 status = "disabled"; 425 426 u2phy0_otg: otg-port { 427 #phy-cells = <0>; 428 status = "disabled"; 429 }; 430 }; 431 }; 432 433 usb2phy2_grf: syscon@fd5d8000 { 434 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 435 "simple-mfd"; 436 reg = <0x0 0xfd5d8000 0x0 0x4000>; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 440 u2phy2: usb2-phy@8000 { 441 compatible = "rockchip,rk3588-usb2phy"; 442 reg = <0x8000 0x10>; 443 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 444 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 445 reset-names = "phy", "apb"; 446 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 447 clock-names = "phyclk"; 448 #clock-cells = <0>; 449 status = "disabled"; 450 451 u2phy2_host: host-port { 452 #phy-cells = <0>; 453 status = "disabled"; 454 }; 455 }; 456 }; 457 458 usb2phy3_grf: syscon@fd5dc000 { 459 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 460 "simple-mfd"; 461 reg = <0x0 0xfd5dc000 0x0 0x4000>; 462 #address-cells = <1>; 463 #size-cells = <1>; 464 465 u2phy3: usb2-phy@c000 { 466 compatible = "rockchip,rk3588-usb2phy"; 467 reg = <0xc000 0x10>; 468 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 469 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 470 reset-names = "phy", "apb"; 471 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 472 clock-names = "phyclk"; 473 #clock-cells = <0>; 474 status = "disabled"; 475 476 u2phy3_host: host-port { 477 #phy-cells = <0>; 478 status = "disabled"; 479 }; 480 }; 481 }; 482 483 hdptxphy0_grf: syscon@fd5e0000 { 484 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 485 reg = <0x0 0xfd5e0000 0x0 0x100>; 486 }; 487 488 ioc: syscon@fd5f0000 { 489 compatible = "rockchip,rk3588-ioc", "syscon"; 490 reg = <0x0 0xfd5f0000 0x0 0x10000>; 491 }; 492 493 syssram: sram@fd600000 { 494 compatible = "mmio-sram"; 495 reg = <0x0 0xfd600000 0x0 0x100000>; 496 497 #address-cells = <1>; 498 #size-cells = <1>; 499 ranges = <0x0 0x0 0xfd600000 0x100000>; 500 }; 501 502 cru: clock-controller@fd7c0000 { 503 compatible = "rockchip,rk3588-cru"; 504 rockchip,grf = <&php_grf>; 505 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 506 #clock-cells = <1>; 507 #reset-cells = <1>; 508 509 assigned-clocks = 510 <&cru PLL_PPLL>, <&cru PLL_CPLL>, 511 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 512 <&cru ARMCLK_L>, <&cru ARMCLK_B01>, 513 <&cru ACLK_CENTER_ROOT>, <&cru PCLK_CENTER_ROOT>, 514 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 515 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 516 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 517 <&cru HCLK_PMU_CM0_ROOT>; 518 assigned-clock-rates = 519 <100000000>, <1500000000>, 520 <850000000>, <1188000000>, 521 <816000000>, <1008000000>, 522 <600000000>, <200000000>, 523 <400000000>, <500000000>, 524 <800000000>, <100000000>, 525 <400000000>, <100000000>, 526 <200000000>; 527 }; 528 529 i2c0: i2c@fd880000 { 530 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 531 reg = <0x0 0xfd880000 0x0 0x1000>; 532 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 533 clock-names = "i2c", "pclk"; 534 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&i2c0m0_xfer>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 status = "disabled"; 540 }; 541 542 uart0: serial@fd890000 { 543 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 544 reg = <0x0 0xfd890000 0x0 0x100>; 545 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 547 clock-names = "baudclk", "apb_pclk"; 548 reg-shift = <2>; 549 reg-io-width = <4>; 550 dmas = <&dmac0 6>, <&dmac0 7>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&uart0m0_xfer>; 553 status = "disabled"; 554 }; 555 556 pwm0: pwm@fd8b0000 { 557 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 558 reg = <0x0 0xfd8b0000 0x0 0x10>; 559 #pwm-cells = <3>; 560 pinctrl-names = "active"; 561 pinctrl-0 = <&pwm0m0_pins>; 562 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 563 clock-names = "pwm", "pclk"; 564 status = "disabled"; 565 }; 566 567 pwm1: pwm@fd8b0010 { 568 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 569 reg = <0x0 0xfd8b0010 0x0 0x10>; 570 #pwm-cells = <3>; 571 pinctrl-names = "active"; 572 pinctrl-0 = <&pwm1m0_pins>; 573 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 574 clock-names = "pwm", "pclk"; 575 status = "disabled"; 576 }; 577 578 pwm2: pwm@fd8b0020 { 579 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 580 reg = <0x0 0xfd8b0020 0x0 0x10>; 581 #pwm-cells = <3>; 582 pinctrl-names = "active"; 583 pinctrl-0 = <&pwm2m0_pins>; 584 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 585 clock-names = "pwm", "pclk"; 586 status = "disabled"; 587 }; 588 589 pwm3: pwm@fd8b0030 { 590 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 591 reg = <0x0 0xfd8b0030 0x0 0x10>; 592 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 594 #pwm-cells = <3>; 595 pinctrl-names = "active"; 596 pinctrl-0 = <&pwm3m0_pins>; 597 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 598 clock-names = "pwm", "pclk"; 599 status = "disabled"; 600 }; 601 602 pmu: power-management@fd8d8000 { 603 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 604 reg = <0x0 0xfd8d8000 0x0 0x400>; 605 606 power: power-controller { 607 compatible = "rockchip,rk3588-power-controller"; 608 #power-domain-cells = <1>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 status = "okay"; 612 613 /* These power domains are grouped by VD_NPU */ 614 power-domain@RK3588_PD_NPU { 615 reg = <RK3588_PD_NPU>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 619 power-domain@RK3588_PD_NPUTOP { 620 reg = <RK3588_PD_NPUTOP>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 624 power-domain@RK3588_PD_NPU1 { 625 reg = <RK3588_PD_NPU1>; 626 }; 627 power-domain@RK3588_PD_NPU2 { 628 reg = <RK3588_PD_NPU2>; 629 }; 630 }; 631 }; 632 /* These power domains are grouped by VD_GPU */ 633 power-domain@RK3588_PD_GPU { 634 reg = <RK3588_PD_GPU>; 635 }; 636 /* These power domains are grouped by VD_VCODEC */ 637 power-domain@RK3588_PD_VCODEC { 638 reg = <RK3588_PD_VCODEC>; 639 #address-cells = <1>; 640 #size-cells = <0>; 641 642 power-domain@RK3588_PD_RKVDEC0 { 643 reg = <RK3588_PD_RKVDEC0>; 644 }; 645 power-domain@RK3588_PD_RKVDEC1 { 646 reg = <RK3588_PD_RKVDEC1>; 647 }; 648 power-domain@RK3588_PD_VENC0 { 649 reg = <RK3588_PD_VENC0>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 653 power-domain@RK3588_PD_VENC1 { 654 reg = <RK3588_PD_VENC1>; 655 }; 656 }; 657 }; 658 /* These power domains are grouped by VD_LOGIC */ 659 power-domain@RK3588_PD_VDPU { 660 reg = <RK3588_PD_VDPU>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 664 power-domain@RK3588_PD_RGA30 { 665 reg = <RK3588_PD_RGA30>; 666 }; 667 power-domain@RK3588_PD_av1 { 668 reg = <RK3588_PD_AV1>; 669 }; 670 }; 671 power-domain@RK3588_PD_VOP { 672 reg = <RK3588_PD_VOP>; 673 }; 674 power-domain@RK3588_PD_VO0 { 675 reg = <RK3588_PD_VO0>; 676 }; 677 power-domain@RK3588_PD_VO1 { 678 reg = <RK3588_PD_VO1>; 679 }; 680 power-domain@RK3588_PD_VI { 681 reg = <RK3588_PD_VI>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 685 power-domain@RK3588_PD_ISP1 { 686 reg = <RK3588_PD_ISP1>; 687 }; 688 power-domain@RK3588_PD_FEC { 689 reg = <RK3588_PD_FEC>; 690 }; 691 }; 692 power-domain@RK3588_PD_RGA31 { 693 reg = <RK3588_PD_RGA31>; 694 }; 695 power-domain@RK3588_PD_USB { 696 reg = <RK3588_PD_USB>; 697 }; 698 power-domain@RK3588_PD_PHP { 699 reg = <RK3588_PD_PHP>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 703 power-domain@RK3588_PD_GMAC { 704 reg = <RK3588_PD_GMAC>; 705 }; 706 power-domain@RK3588_PD_PCIE { 707 reg = <RK3588_PD_PCIE>; 708 }; 709 }; 710 power-domain@RK3588_PD_NVM { 711 reg = <RK3588_PD_NVM>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 715 power-domain@RK3588_PD_NVM0 { 716 reg = <RK3588_PD_NVM0>; 717 }; 718 }; 719 power-domain@RK3588_PD_SDIO { 720 reg = <RK3588_PD_SDIO>; 721 }; 722 power-domain@RK3588_PD_AUDIO { 723 reg = <RK3588_PD_AUDIO>; 724 }; 725 power-domain@RK3588_PD_SDMMC { 726 reg = <RK3588_PD_SDMMC>; 727 }; 728 }; 729 }; 730 731 pvtm@fda40000 { 732 compatible = "rockchip,rk3588-bigcore0-pvtm"; 733 reg = <0x0 0xfda40000 0x0 0x100>; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 pvtm@0 { 737 reg = <0>; 738 clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>; 739 clock-names = "clk", "pclk"; 740 }; 741 }; 742 743 pvtm@fda50000 { 744 compatible = "rockchip,rk3588-bigcore1-pvtm"; 745 reg = <0x0 0xfda50000 0x0 0x100>; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 pvtm@1 { 749 reg = <1>; 750 clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>; 751 clock-names = "clk", "pclk"; 752 }; 753 }; 754 755 pvtm@fda60000 { 756 compatible = "rockchip,rk3588-litcore-pvtm"; 757 reg = <0x0 0xfda60000 0x0 0x100>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 pvtm@2 { 761 reg = <2>; 762 clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>; 763 clock-names = "clk", "pclk"; 764 }; 765 }; 766 767 pvtm@fdaf0000 { 768 compatible = "rockchip,rk3588-npu-pvtm"; 769 reg = <0x0 0xfdaf0000 0x0 0x100>; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 pvtm@3 { 773 reg = <3>; 774 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>; 775 clock-names = "clk", "pclk"; 776 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; 777 reset-names = "rts", "rst-p"; 778 }; 779 }; 780 781 pvtm@fdb30000 { 782 compatible = "rockchip,rk3588-gpu-pvtm"; 783 reg = <0x0 0xfdb30000 0x0 0x100>; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 pvtm@4 { 787 reg = <4>; 788 clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>; 789 clock-names = "clk", "pclk"; 790 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; 791 reset-names = "rts", "rst-p"; 792 }; 793 }; 794 795 npu0_mmu: iommu@fdab9000 { 796 compatible = "rockchip,iommu-v2"; 797 reg = <0x0 0xfdab9000 0x0 0x100>, <0x0 0xfdaba000 0x0 0x100>; 798 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 799 interrupt-names = "npu0_mmu"; 800 clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>; 801 clock-names = "aclk", "iface"; 802 power-domains = <&power RK3588_PD_NPUTOP>; 803 #iommu-cells = <0>; 804 status = "disabled"; 805 }; 806 807 npu1_mmu: iommu@fdaca000 { 808 compatible = "rockchip,iommu-v2"; 809 reg = <0x0 0xfdaca000 0x0 0x100>; 810 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 811 interrupt-names = "npu1_mmu"; 812 clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>; 813 clock-names = "aclk", "iface"; 814 power-domains = <&power RK3588_PD_NPU1>; 815 #iommu-cells = <0>; 816 status = "disabled"; 817 }; 818 819 npu2_mmu: iommu@fdada000 { 820 compatible = "rockchip,iommu-v2"; 821 reg = <0x0 0xfdada000 0x0 0x100>; 822 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 823 interrupt-names = "npu2_mmu"; 824 clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>; 825 clock-names = "aclk", "iface"; 826 power-domains = <&power RK3588_PD_NPU2>; 827 #iommu-cells = <0>; 828 status = "disabled"; 829 }; 830 831 vdpu_mmu: iommu@fdb50800 { 832 compatible = "rockchip,iommu-v2"; 833 reg = <0x0 0xfdb50800 0x0 0x40>; 834 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 835 interrupt-names = "irq_vdpu_mmu"; 836 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 837 clock-names = "aclk", "iface"; 838 power-domains = <&power RK3588_PD_VDPU>; 839 #iommu-cells = <0>; 840 status = "disabled"; 841 }; 842 843 rga3_0_mmu: iommu@fdb60f00 { 844 compatible = "rockchip,iommu-v2"; 845 reg = <0x0 0xfdb60f00 0x0 0x100>; 846 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 847 interrupt-names = "rga3_0_mmu"; 848 clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; 849 clock-names = "aclk", "iface"; 850 power-domains = <&power RK3588_PD_RGA30>; 851 #iommu-cells = <0>; 852 status = "disabled"; 853 }; 854 855 rga3_1_mmu: iommu@fdb70f00 { 856 compatible = "rockchip,iommu-v2"; 857 reg = <0x0 0xfdb70f00 0x0 0x100>; 858 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 859 interrupt-names = "rga3_1_mmu"; 860 clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; 861 clock-names = "aclk", "iface"; 862 power-domains = <&power RK3588_PD_RGA31>; 863 #iommu-cells = <0>; 864 status = "disabled"; 865 }; 866 867 jpegd_mmu: iommu@fdb90480 { 868 compatible = "rockchip,iommu-v2"; 869 reg = <0x0 0xfdb90480 0x0 0x40>; 870 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 871 interrupt-names = "irq_jpegd_mmu"; 872 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 873 clock-names = "aclk", "iface"; 874 power-domains = <&power RK3588_PD_VDPU>; 875 #iommu-cells = <0>; 876 status = "disabled"; 877 }; 878 879 jpege0_mmu: iommu@fdba0800 { 880 compatible = "rockchip,iommu-v2"; 881 reg = <0x0 0xfdba0800 0x0 0x40>; 882 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 883 interrupt-names = "irq_jpege0_mmu"; 884 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 885 clock-names = "aclk", "iface"; 886 power-domains = <&power RK3588_PD_VDPU>; 887 #iommu-cells = <0>; 888 status = "disabled"; 889 }; 890 891 jpege1_mmu: iommu@fdba4800 { 892 compatible = "rockchip,iommu-v2"; 893 reg = <0x0 0xfdba4800 0x0 0x40>; 894 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 895 interrupt-names = "irq_jpege1_mmu"; 896 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 897 clock-names = "aclk", "iface"; 898 power-domains = <&power RK3588_PD_VDPU>; 899 #iommu-cells = <0>; 900 status = "disabled"; 901 }; 902 903 jpege2_mmu: iommu@fdba8800 { 904 compatible = "rockchip,iommu-v2"; 905 reg = <0x0 0xfdba8800 0x0 0x40>; 906 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 907 interrupt-names = "irq_jpege2_mmu"; 908 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 909 clock-names = "aclk", "iface"; 910 power-domains = <&power RK3588_PD_VDPU>; 911 #iommu-cells = <0>; 912 status = "disabled"; 913 }; 914 915 jpege3_mmu: iommu@fdbac800 { 916 compatible = "rockchip,iommu-v2"; 917 reg = <0x0 0xfdbac800 0x0 0x40>; 918 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 919 interrupt-names = "irq_jpege3_mmu"; 920 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 921 clock-names = "aclk", "iface"; 922 power-domains = <&power RK3588_PD_VDPU>; 923 #iommu-cells = <0>; 924 status = "disabled"; 925 }; 926 927 iep_mmu: iommu@fdbb0800 { 928 compatible = "rockchip,iommu-v2"; 929 reg = <0x0 0xfdbb0800 0x0 0x100>; 930 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 931 interrupt-names = "irq_iep_mmu"; 932 clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>; 933 clock-names = "aclk", "iface"; 934 #iommu-cells = <0>; 935 power-domains = <&power RK3588_PD_VDPU>; 936 status = "disabled"; 937 }; 938 939 rkvenc0_mmu: iommu@fdbdf000 { 940 compatible = "rockchip,iommu-v2"; 941 reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>; 942 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 944 interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1"; 945 clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>; 946 clock-names = "aclk", "iface"; 947 rockchip,disable-mmu-reset; 948 rockchip,enable-cmd-retry; 949 #iommu-cells = <0>; 950 power-domains = <&power RK3588_PD_VENC0>; 951 status = "disabled"; 952 }; 953 954 rkvenc1_mmu: iommu@fdbef000 { 955 compatible = "rockchip,iommu-v2"; 956 reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>; 957 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 959 interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1"; 960 clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>; 961 lock-names = "aclk", "iface"; 962 rockchip,disable-mmu-reset; 963 rockchip,enable-cmd-retry; 964 #iommu-cells = <0>; 965 power-domains = <&power RK3588_PD_VENC1>; 966 status = "disabled"; 967 }; 968 969 rkvdec0_mmu: iommu@fdc38700 { 970 compatible = "rockchip,iommu-v2"; 971 reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; 972 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 973 interrupt-names = "irq_rkvdec0_mmu"; 974 locks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; 975 clock-names = "aclk", "iface"; 976 rockchip,disable-mmu-reset; 977 rockchip,enable-cmd-retry; 978 #iommu-cells = <0>; 979 power-domains = <&power RK3588_PD_RKVDEC0>; 980 status = "disabled"; 981 }; 982 983 rkvdec1_mmu: iommu@fdc48700 { 984 compatible = "rockchip,iommu-v2"; 985 reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>; 986 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 987 interrupt-names = "irq_rkvdec1_mmu"; 988 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; 989 clock-names = "aclk", "iface"; 990 rockchip,disable-mmu-reset; 991 rockchip,enable-cmd-retry; 992 #iommu-cells = <0>; 993 power-domains = <&power RK3588_PD_RKVDEC1>; 994 status = "disabled"; 995 }; 996 997 isp0_mmu: iommu@fdcb7f00 { 998 compatible = "rockchip,iommu-v2"; 999 reg = <0x0 0xfdcb7f00 0x0 0x100>; 1000 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1001 interrupt-names = "isp0_mmu"; 1002 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; 1003 clock-names = "aclk", "iface"; 1004 power-domains = <&power RK3588_PD_VI>; 1005 #iommu-cells = <0>; 1006 rockchip,disable-mmu-reset; 1007 status = "disabled"; 1008 }; 1009 1010 isp1_mmu: iommu@fdcc7f00 { 1011 compatible = "rockchip,iommu-v2"; 1012 reg = <0x0 0xfdcc7f00 0x0 0x100>; 1013 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1014 interrupt-names = "isp1_mmu"; 1015 clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; 1016 clock-names = "aclk", "iface"; 1017 power-domains = <&power RK3588_PD_ISP1>; 1018 #iommu-cells = <0>; 1019 rockchip,disable-mmu-reset; 1020 status = "disabled"; 1021 }; 1022 1023 fec0_mmu: iommu@fdcd0f00 { 1024 compatible = "rockchip,iommu-v2"; 1025 reg = <0x0 0xfdcd0f00 0x0 0x100>; 1026 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1027 interrupt-names = "fec0_mmu"; 1028 clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>; 1029 clock-names = "aclk", "iface"; 1030 power-domains = <&power RK3588_PD_FEC>; 1031 #iommu-cells = <0>; 1032 status = "disabled"; 1033 }; 1034 1035 fec1_mmu: iommu@fdcd8f00 { 1036 compatible = "rockchip,iommu-v2"; 1037 reg = <0x0 0xfdcd8f00 0x0 0x100>; 1038 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1039 interrupt-names = "fec1_mmu"; 1040 clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>; 1041 clock-names = "aclk", "iface"; 1042 power-domains = <&power RK3588_PD_FEC>; 1043 #iommu-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 vop_mmu: iommu@fdd97e00 { 1048 compatible = "rockchip,iommu-v2"; 1049 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1050 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1051 interrupt-names = "vop_mmu"; 1052 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1053 clock-names = "aclk", "iface"; 1054 #iommu-cells = <0>; 1055 rockchip,disable-device-link-resume; 1056 status = "disabled"; 1057 }; 1058 1059 spdif_tx2: spdif-tx@fddb0000 { 1060 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1061 reg = <0x0 0xfddb0000 0x0 0x1000>; 1062 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1063 dmas = <&dmac1 6>; 1064 dma-names = "tx"; 1065 clock-names = "mclk", "hclk"; 1066 clocks = <&cru MCLK_SPDIF2_DP0>, <&cru HCLK_SPDIF2_DP0>; 1067 #sound-dai-cells = <0>; 1068 status = "disabled"; 1069 }; 1070 1071 i2s4_8ch: i2s@fddc0000 { 1072 compatible = "rockchip,rk3588-i2s-tdm"; 1073 reg = <0x0 0xfddc0000 0x0 0x1000>; 1074 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1076 clock-names = "mclk_tx", "hclk"; 1077 dmas = <&dmac2 0>; 1078 dma-names = "tx"; 1079 resets = <&cru SRST_M_I2S4_8CH_TX>; 1080 reset-names = "tx-m"; 1081 #sound-dai-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 1085 spdif_tx3: spdif-tx@fdde0000 { 1086 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1087 reg = <0x0 0xfdde0000 0x0 0x1000>; 1088 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 1089 dmas = <&dmac1 7>; 1090 dma-names = "tx"; 1091 clock-names = "mclk", "hclk"; 1092 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; 1093 #sound-dai-cells = <0>; 1094 status = "disabled"; 1095 }; 1096 1097 i2s5_8ch: i2s@fddf0000 { 1098 compatible = "rockchip,rk3588-i2s-tdm"; 1099 reg = <0x0 0xfddf0000 0x0 0x1000>; 1100 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1101 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1102 clock-names = "mclk_tx", "hclk"; 1103 dmas = <&dmac2 2>; 1104 dma-names = "tx"; 1105 resets = <&cru SRST_M_I2S5_8CH_TX>; 1106 reset-names = "tx-m"; 1107 #sound-dai-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 i2s9_8ch: i2s@fddfc000 { 1112 compatible = "rockchip,rk3588-i2s-tdm"; 1113 reg = <0x0 0xfddfc000 0x0 0x1000>; 1114 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1116 clock-names = "mclk_rx", "hclk"; 1117 dmas = <&dmac2 23>; 1118 dma-names = "rx"; 1119 resets = <&cru SRST_M_I2S9_8CH_RX>; 1120 reset-names = "rx-m"; 1121 #sound-dai-cells = <0>; 1122 status = "disabled"; 1123 }; 1124 1125 spdif_rx0: spdif-rx@fde08000 { 1126 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; 1127 reg = <0x0 0xfde08000 0x0 0x1000>; 1128 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>; 1130 clock-names = "mclk", "hclk"; 1131 dmas = <&dmac0 21>; 1132 dma-names = "rx"; 1133 resets = <&cru SRST_M_SPDIFRX0>; 1134 reset-names = "spdifrx-m"; 1135 #sound-dai-cells = <0>; 1136 status = "disabled"; 1137 }; 1138 1139 edp0: edp@fdec0000 { 1140 compatible = "rockchip,rk3588-edp"; 1141 reg = <0x0 0xfdec0000 0x0 0x1000>; 1142 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, 1144 <&cru CLK_EDP0_200M>; 1145 clock-names = "dp", "pclk", "spdif"; 1146 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; 1147 reset-names = "dp", "apb"; 1148 phys = <&hdptxphy0>; 1149 phy-names = "dp"; 1150 power-domains = <&power RK3588_PD_VO1>; 1151 rockchip,grf = <&vo1_grf>; 1152 status = "disabled"; 1153 }; 1154 1155 pcie2x1l1: pcie@fe180000 { 1156 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 1157 #address-cells = <3>; 1158 #size-cells = <2>; 1159 bus-range = <0x30 0x3f>; 1160 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1161 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1162 <&cru CLK_PCIE_AUX3>; 1163 clock-names = "aclk_mst", "aclk_slv", 1164 "aclk_dbi", "pclk", "aux"; 1165 device_type = "pci"; 1166 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1171 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1172 #interrupt-cells = <1>; 1173 interrupt-map-mask = <0 0 0 7>; 1174 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1175 <0 0 0 2 &pcie2x1l1_intc 1>, 1176 <0 0 0 3 &pcie2x1l1_intc 2>, 1177 <0 0 0 4 &pcie2x1l1_intc 3>; 1178 linux,pci-domain = <3>; 1179 num-ib-windows = <8>; 1180 num-ob-windows = <8>; 1181 max-link-speed = <2>; 1182 msi-map = <0x3000 &its 0x3000 0x1000>; 1183 num-lanes = <1>; 1184 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1185 phy-names = "pcie-phy"; 1186 power-domains = <&power RK3588_PD_PHP>; 1187 ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000 1188 0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000 1189 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000 1190 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; 1191 1192 reg = <0xa 0x40c00000 0x0 0x400000>, 1193 <0x0 0xfe180000 0x0 0x10000>; 1194 reg-names = "pcie-dbi", "pcie-apb"; 1195 resets = <&cru SRST_PCIE3_POWER_UP>; 1196 reset-names = "pipe"; 1197 status = "disabled"; 1198 1199 pcie2x1l1_intc: legacy-interrupt-controller { 1200 interrupt-controller; 1201 #address-cells = <0>; 1202 #interrupt-cells = <1>; 1203 interrupt-parent = <&gic>; 1204 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>; 1205 }; 1206 }; 1207 1208 pcie2x1l2: pcie@fe190000 { 1209 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 1210 #address-cells = <3>; 1211 #size-cells = <2>; 1212 bus-range = <0x40 0x4f>; 1213 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1214 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1215 <&cru CLK_PCIE_AUX4>; 1216 clock-names = "aclk_mst", "aclk_slv", 1217 "aclk_dbi", "pclk", "aux"; 1218 device_type = "pci"; 1219 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1224 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1225 #interrupt-cells = <1>; 1226 interrupt-map-mask = <0 0 0 7>; 1227 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1228 <0 0 0 2 &pcie2x1l2_intc 1>, 1229 <0 0 0 3 &pcie2x1l2_intc 2>, 1230 <0 0 0 4 &pcie2x1l2_intc 3>; 1231 linux,pci-domain = <4>; 1232 num-ib-windows = <8>; 1233 num-ob-windows = <8>; 1234 max-link-speed = <2>; 1235 msi-map = <0x4000 &its 0x4000 0x1000>; 1236 num-lanes = <1>; 1237 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1238 phy-names = "pcie-phy"; 1239 power-domains = <&power RK3588_PD_PHP>; 1240 ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 1241 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 1242 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000 1243 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; 1244 reg = <0xa 0x41000000 0x0 0x400000>, 1245 <0x0 0xfe190000 0x0 0x10000>; 1246 reg-names = "pcie-dbi", "pcie-apb"; 1247 resets = <&cru SRST_PCIE4_POWER_UP>; 1248 reset-names = "pipe"; 1249 status = "disabled"; 1250 1251 pcie2x1l2_intc: legacy-interrupt-controller { 1252 interrupt-controller; 1253 #address-cells = <0>; 1254 #interrupt-cells = <1>; 1255 interrupt-parent = <&gic>; 1256 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>; 1257 }; 1258 }; 1259 1260 gmac1: ethernet@fe1c0000 { 1261 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1262 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1263 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1265 interrupt-names = "macirq", "eth_wake_irq"; 1266 rockchip,grf = <&sys_grf>; 1267 rockchip,php_grf = <&php_grf>; 1268 clocks = <&cru CLK_GMAC1>, <&cru ACLK_GMAC1>, 1269 <&cru PCLK_GMAC1>, <&cru CLK_GMAC1_PTP_REF>; 1270 clock-names = "stmmaceth", "aclk_mac", 1271 "pclk_mac", "ptp_ref"; 1272 resets = <&cru SRST_A_GMAC1>; 1273 reset-names = "stmmaceth"; 1274 1275 snps,mixed-burst; 1276 snps,tso; 1277 1278 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1279 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1280 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1281 status = "disabled"; 1282 1283 mdio1: mdio { 1284 compatible = "snps,dwmac-mdio"; 1285 #address-cells = <0x1>; 1286 #size-cells = <0x0>; 1287 }; 1288 1289 gmac1_stmmac_axi_setup: stmmac-axi-config { 1290 snps,wr_osr_lmt = <4>; 1291 snps,rd_osr_lmt = <8>; 1292 snps,blen = <0 0 0 0 16 8 4>; 1293 }; 1294 1295 gmac1_mtl_rx_setup: rx-queues-config { 1296 snps,rx-queues-to-use = <2>; 1297 queue0 {}; 1298 queue1 {}; 1299 }; 1300 1301 gmac1_mtl_tx_setup: tx-queues-config { 1302 snps,tx-queues-to-use = <2>; 1303 queue0 {}; 1304 queue1 {}; 1305 }; 1306 }; 1307 1308 sata0: sata@fe210000 { 1309 compatible = "snps,dwc-ahci"; 1310 reg = <0 0xfe210000 0 0x1000>; 1311 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1312 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>; 1313 clock-names = "sata", "pmalive", "rxoob", "ref"; 1314 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; 1315 interrupt-names = "hostc"; 1316 phys = <&combphy0_ps PHY_TYPE_SATA>; 1317 phy-names = "sata-phy"; 1318 ports-implemented = <0x1>; 1319 power-domains = <&power RK3588_PD_PHP>; 1320 status = "disabled"; 1321 }; 1322 1323 sata2: sata@fe230000 { 1324 compatible = "snps,dwc-ahci"; 1325 reg = <0 0xfe230000 0 0x1000>; 1326 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1327 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>; 1328 clock-names = "sata", "pmalive", "rxoob", "ref"; 1329 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; 1330 interrupt-names = "hostc"; 1331 phys = <&combphy2_psu PHY_TYPE_SATA>; 1332 phy-names = "sata-phy"; 1333 ports-implemented = <0x1>; 1334 power-domains = <&power RK3588_PD_PHP>; 1335 status = "disabled"; 1336 }; 1337 1338 sfc: spi@fe2b0000 { 1339 compatible = "rockchip,sfc"; 1340 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1341 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1342 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1343 clock-names = "clk_sfc", "hclk_sfc"; 1344 assigned-clocks = <&cru SCLK_SFC>; 1345 assigned-clock-rates = <100000000>; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 status = "disabled"; 1349 }; 1350 1351 sdmmc: mmc@fe2c0000 { 1352 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1353 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1354 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1355 clocks = <&scmi_clk SCMI_CCLK_SD>, <&scmi_clk SCMI_HCLK_SD>, 1356 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1357 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; 1358 fifo-depth = <0x100>; 1359 max-frequency = <200000000>; 1360 pinctrl-names = "default"; 1361 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1362 status = "disabled"; 1363 }; 1364 1365 sdio: mmc@fe2d0000 { 1366 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1367 reg = <0x0 0xfe2d0000 0x0 0x4000>; 1368 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1369 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1370 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1371 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1372 fifo-depth = <0x100>; 1373 max-frequency = <200000000>; 1374 status = "disabled"; 1375 }; 1376 1377 sdhci: mmc@fe2e0000 { 1378 compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci"; 1379 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1380 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1381 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>; 1382 assigned-clock-rates = <200000000>, <24000000>; 1383 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1384 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1385 <&cru TMCLK_EMMC>; 1386 clock-names = "core", "bus", "axi", "block", "timer"; 1387 max-frequency = <200000000>; 1388 status = "disabled"; 1389 }; 1390 1391 i2s0_8ch: i2s@fe470000 { 1392 compatible = "rockchip,rk3588-i2s-tdm"; 1393 reg = <0x0 0xfe470000 0x0 0x1000>; 1394 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 1395 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1396 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1397 dmas = <&dmac0 0>, <&dmac0 1>; 1398 dma-names = "tx", "rx"; 1399 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1400 reset-names = "tx-m", "rx-m"; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&i2s0_lrck 1403 &i2s0_sclk 1404 &i2s0_sdi0 1405 &i2s0_sdi1 1406 &i2s0_sdi2 1407 &i2s0_sdi3 1408 &i2s0_sdo0 1409 &i2s0_sdo1 1410 &i2s0_sdo2 1411 &i2s0_sdo3>; 1412 #sound-dai-cells = <0>; 1413 status = "disabled"; 1414 }; 1415 1416 i2s1_8ch: i2s@fe480000 { 1417 compatible = "rockchip,rk3588-i2s-tdm"; 1418 reg = <0x0 0xfe480000 0x0 0x1000>; 1419 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 1420 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1421 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1422 dmas = <&dmac0 2>, <&dmac0 3>; 1423 dma-names = "tx", "rx"; 1424 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1425 reset-names = "tx-m", "rx-m"; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&i2s1m0_lrck 1428 &i2s1m0_sclk 1429 &i2s1m0_sdi0 1430 &i2s1m0_sdi1 1431 &i2s1m0_sdi2 1432 &i2s1m0_sdi3 1433 &i2s1m0_sdo0 1434 &i2s1m0_sdo1 1435 &i2s1m0_sdo2 1436 &i2s1m0_sdo3>; 1437 #sound-dai-cells = <0>; 1438 status = "disabled"; 1439 }; 1440 1441 i2s2_2ch: i2s@fe490000 { 1442 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1443 reg = <0x0 0xfe490000 0x0 0x1000>; 1444 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 1445 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1446 clock-names = "i2s_clk", "i2s_hclk"; 1447 dmas = <&dmac1 0>, <&dmac1 1>; 1448 dma-names = "tx", "rx"; 1449 pinctrl-names = "default"; 1450 pinctrl-0 = <&i2s2m1_lrck 1451 &i2s2m1_sclk 1452 &i2s2m1_sdi 1453 &i2s2m1_sdo>; 1454 #sound-dai-cells = <0>; 1455 status = "disabled"; 1456 }; 1457 1458 i2s3_2ch: i2s@fe4a0000 { 1459 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1460 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1461 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1462 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1463 clock-names = "i2s_clk", "i2s_hclk"; 1464 dmas = <&dmac1 2>, <&dmac1 3>; 1465 dma-names = "tx", "rx"; 1466 pinctrl-names = "default"; 1467 pinctrl-0 = <&i2s3_lrck 1468 &i2s3_sclk 1469 &i2s3_sdi 1470 &i2s3_sdo>; 1471 #sound-dai-cells = <0>; 1472 status = "disabled"; 1473 }; 1474 1475 pdm0: pdm@fe4b0000 { 1476 compatible = "rockchip,rk3588-pdm"; 1477 reg = <0x0 0xfe4b0000 0x0 0x1000>; 1478 clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>; 1479 clock-names = "pdm_clk", "pdm_hclk"; 1480 dmas = <&dmac0 4>; 1481 dma-names = "rx"; 1482 pinctrl-names = "default"; 1483 pinctrl-0 = <&pdm0m0_clk 1484 &pdm0m0_clk1 1485 &pdm0m0_sdi0 1486 &pdm0m0_sdi1 1487 &pdm0m0_sdi2 1488 &pdm0m0_sdi3>; 1489 #sound-dai-cells = <0>; 1490 status = "disabled"; 1491 }; 1492 1493 pdm1: pdm@fe4c0000 { 1494 compatible = "rockchip,rk3588-pdm"; 1495 reg = <0x0 0xfe4c0000 0x0 0x1000>; 1496 clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>; 1497 clock-names = "pdm_clk", "pdm_hclk"; 1498 dmas = <&dmac1 4>; 1499 dma-names = "rx"; 1500 pinctrl-names = "default"; 1501 pinctrl-0 = <&pdm1m0_clk 1502 &pdm1m0_clk1 1503 &pdm1m0_sdi0 1504 &pdm1m0_sdi1 1505 &pdm1m0_sdi2 1506 &pdm1m0_sdi3>; 1507 #sound-dai-cells = <0>; 1508 status = "disabled"; 1509 }; 1510 1511 vad: vad@fe4d0000 { 1512 compatible = "rockchip,rk3588-vad"; 1513 reg = <0x0 0xfe4d0000 0x0 0x1000>; 1514 reg-names = "vad"; 1515 clocks = <&cru HCLK_VAD>; 1516 clock-names = "hclk"; 1517 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1518 rockchip,audio-src = <0>; 1519 rockchip,det-channel = <0>; 1520 rockchip,mode = <0>; 1521 #sound-dai-cells = <0>; 1522 status = "disabled"; 1523 }; 1524 1525 spdif_tx0: spdif-tx@fe4e0000 { 1526 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1527 reg = <0x0 0xfe4e0000 0x0 0x1000>; 1528 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1529 dmas = <&dmac0 5>; 1530 dma-names = "tx"; 1531 clock-names = "mclk", "hclk"; 1532 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; 1533 pinctrl-names = "default"; 1534 pinctrl-0 = <&spdif0m0_tx>; 1535 #sound-dai-cells = <0>; 1536 status = "disabled"; 1537 }; 1538 1539 spdif_tx1: spdif-tx@fe4f0000 { 1540 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1541 reg = <0x0 0xfe4f0000 0x0 0x1000>; 1542 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1543 dmas = <&dmac1 5>; 1544 dma-names = "tx"; 1545 clock-names = "mclk", "hclk"; 1546 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; 1547 pinctrl-names = "default"; 1548 pinctrl-0 = <&spdif1m0_tx>; 1549 #sound-dai-cells = <0>; 1550 status = "disabled"; 1551 }; 1552 1553 acdcdig_dsm: codec-digital@fe500000 { 1554 compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1"; 1555 reg = <0x0 0xfe500000 0x0 0x1000>; 1556 clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>; 1557 clock-names = "dac", "pclk"; 1558 resets = <&cru SRST_DAC_ACDCDIG>; 1559 reset-names = "reset" ; 1560 rockchip,grf = <&sys_grf>; 1561 rockchip,pwm-output-mode; 1562 pinctrl-names = "default"; 1563 pinctrl-0 = <&auddsm_pins>; 1564 #sound-dai-cells = <0>; 1565 status = "disabled"; 1566 }; 1567 1568 hwlock: hwspinlock@fe5a0000 { 1569 compatible = "rockchip,hwspinlock"; 1570 reg = <0 0xfe5a0000 0 0x100>; 1571 #hwlock-cells = <1>; 1572 }; 1573 1574 gic: interrupt-controller@fe600000 { 1575 compatible = "arm,gic-v3"; 1576 #interrupt-cells = <3>; 1577 #address-cells = <2>; 1578 #size-cells = <2>; 1579 ranges; 1580 interrupt-controller; 1581 1582 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1583 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1584 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1585 its: interrupt-controller@fe640000 { 1586 compatible = "arm,gic-v3-its"; 1587 msi-controller; 1588 #msi-cells = <1>; 1589 reg = <0x0 0xfe640000 0x0 0x20000>; 1590 }; 1591 }; 1592 1593 dmac0: dma-controller@fea10000 { 1594 compatible = "arm,pl330", "arm,primecell"; 1595 reg = <0x0 0xfea10000 0x0 0x4000>; 1596 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1598 clocks = <&cru ACLK_DMAC0>; 1599 clock-names = "apb_pclk"; 1600 #dma-cells = <1>; 1601 arm,pl330-periph-burst; 1602 }; 1603 1604 dmac1: dma-controller@fea30000 { 1605 compatible = "arm,pl330", "arm,primecell"; 1606 reg = <0x0 0xfea30000 0x0 0x4000>; 1607 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1609 clocks = <&cru ACLK_DMAC1>; 1610 clock-names = "apb_pclk"; 1611 #dma-cells = <1>; 1612 arm,pl330-periph-burst; 1613 }; 1614 1615 can0: can@fea50000 { 1616 compatible = "rockchip,canfd-1.0"; 1617 reg = <0x0 0xfea50000 0x0 0x1000>; 1618 iinterrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 1619 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 1620 clock-names = "baudclk", "apb_pclk"; 1621 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 1622 reset-names = "can", "can-apb"; 1623 pinctrl-names = "default"; 1624 pinctrl-0 = <&can0m0_pins>; 1625 tx-fifo-depth = <1>; 1626 rx-fifo-depth = <6>; 1627 status = "disabled"; 1628 }; 1629 1630 can1: can@fea60000 { 1631 compatible = "rockchip,canfd-1.0"; 1632 reg = <0x0 0xfea60000 0x0 0x1000>; 1633 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 1634 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 1635 clock-names = "baudclk", "apb_pclk"; 1636 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 1637 reset-names = "can", "can-apb"; 1638 pinctrl-names = "default"; 1639 pinctrl-0 = <&can1m0_pins>; 1640 tx-fifo-depth = <1>; 1641 rx-fifo-depth = <6>; 1642 status = "disabled"; 1643 }; 1644 1645 can2: can@fea70000 { 1646 compatible = "rockchip,canfd-1.0"; 1647 reg = <0x0 0xfea70000 0x0 0x1000>; 1648 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1649 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 1650 clock-names = "baudclk", "apb_pclk"; 1651 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; 1652 reset-names = "can", "can-apb"; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&can2m0_pins>; 1655 tx-fifo-depth = <1>; 1656 rx-fifo-depth = <6>; 1657 status = "disabled"; 1658 }; 1659 1660 hw_decompress: decompress@fea80000 { 1661 compatible = "rockchip,hw-decompress"; 1662 reg = <0x0 0xfea80000 0x0 0x1000>; 1663 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1664 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 1665 clock-names = "aclk", "dclk", "pclk"; 1666 resets = <&cru SRST_D_DECOM>; 1667 reset-names = "dresetn"; 1668 status = "disabled"; 1669 }; 1670 1671 i2c1: i2c@fea90000 { 1672 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1673 reg = <0x0 0xfea90000 0x0 0x1000>; 1674 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1675 clock-names = "i2c", "pclk"; 1676 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 1677 pinctrl-names = "default"; 1678 pinctrl-0 = <&i2c1m0_xfer>; 1679 #address-cells = <1>; 1680 #size-cells = <0>; 1681 status = "disabled"; 1682 }; 1683 1684 i2c2: i2c@feaa0000 { 1685 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1686 reg = <0x0 0xfeaa0000 0x0 0x1000>; 1687 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1688 clock-names = "i2c", "pclk"; 1689 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 1690 pinctrl-names = "default"; 1691 pinctrl-0 = <&i2c2m0_xfer>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 status = "disabled"; 1695 }; 1696 1697 i2c3: i2c@feab0000 { 1698 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1699 reg = <0x0 0xfeab0000 0x0 0x1000>; 1700 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1701 clock-names = "i2c", "pclk"; 1702 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 1703 pinctrl-names = "default"; 1704 pinctrl-0 = <&i2c3m0_xfer>; 1705 #address-cells = <1>; 1706 #size-cells = <0>; 1707 status = "disabled"; 1708 }; 1709 1710 i2c4: i2c@feac0000 { 1711 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1712 reg = <0x0 0xfeac0000 0x0 0x1000>; 1713 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1714 clock-names = "i2c", "pclk"; 1715 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1716 pinctrl-names = "default"; 1717 pinctrl-0 = <&i2c4m0_xfer>; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 status = "disabled"; 1721 }; 1722 1723 i2c5: i2c@fead0000 { 1724 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1725 reg = <0x0 0xfead0000 0x0 0x1000>; 1726 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1727 clock-names = "i2c", "pclk"; 1728 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; 1729 pinctrl-names = "default"; 1730 pinctrl-0 = <&i2c5m0_xfer>; 1731 #address-cells = <1>; 1732 #size-cells = <0>; 1733 status = "disabled"; 1734 }; 1735 1736 rktimer: timer@feae0000 { 1737 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 1738 reg = <0x0 0xfeae0000 0x0 0x20>; 1739 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 1740 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 1741 clock-names = "pclk", "timer"; 1742 }; 1743 1744 wdt: watchdog@feaf0000 { 1745 compatible = "snps,dw-wdt"; 1746 reg = <0x0 0xfeaf0000 0x0 0x100>; 1747 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1748 clock-names = "tclk", "pclk"; 1749 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1750 status = "disabled"; 1751 }; 1752 1753 spi0: spi@feb00000 { 1754 compatible = "rockchip,rk3066-spi"; 1755 reg = <0x0 0xfeb00000 0x0 0x1000>; 1756 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1760 clock-names = "spiclk", "apb_pclk"; 1761 dmas = <&dmac0 14>, <&dmac0 15>; 1762 dma-names = "tx", "rx"; 1763 pinctrl-names = "default", "high_speed"; 1764 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1765 pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>; 1766 num-cs = <2>; 1767 status = "disabled"; 1768 }; 1769 1770 spi1: spi@feb10000 { 1771 compatible = "rockchip,rk3066-spi"; 1772 reg = <0x0 0xfeb10000 0x0 0x1000>; 1773 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1777 clock-names = "spiclk", "apb_pclk"; 1778 dmas = <&dmac0 16>, <&dmac0 17>; 1779 dma-names = "tx", "rx"; 1780 pinctrl-names = "default", "high_speed"; 1781 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 1782 pinctrl-1 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins_hs>; 1783 num-cs = <2>; 1784 status = "disabled"; 1785 }; 1786 1787 spi2: spi@feb20000 { 1788 compatible = "rockchip,rk3066-spi"; 1789 reg = <0x0 0xfeb20000 0x0 0x1000>; 1790 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1791 #address-cells = <1>; 1792 #size-cells = <0>; 1793 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1794 clock-names = "spiclk", "apb_pclk"; 1795 dmas = <&dmac1 15>, <&dmac1 16>; 1796 dma-names = "tx", "rx"; 1797 pinctrl-names = "default", "high_speed"; 1798 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1799 pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>; 1800 num-cs = <2>; 1801 status = "disabled"; 1802 }; 1803 1804 spi3: spi@feb30000 { 1805 compatible = "rockchip,rk3066-spi"; 1806 reg = <0x0 0xfeb30000 0x0 0x1000>; 1807 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1811 clock-names = "spiclk", "apb_pclk"; 1812 dmas = <&dmac1 17>, <&dmac1 18>; 1813 dma-names = "tx", "rx"; 1814 pinctrl-names = "default", "high_speed"; 1815 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 1816 pinctrl-1 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins_hs>; 1817 num-cs = <2>; 1818 status = "disabled"; 1819 }; 1820 1821 uart1: serial@feb40000 { 1822 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1823 reg = <0x0 0xfeb40000 0x0 0x100>; 1824 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1825 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1826 clock-names = "baudclk", "apb_pclk"; 1827 reg-shift = <2>; 1828 reg-io-width = <4>; 1829 dmas = <&dmac0 8>, <&dmac0 9>; 1830 pinctrl-names = "default"; 1831 pinctrl-0 = <&uart1m0_xfer>; 1832 status = "disabled"; 1833 }; 1834 1835 uart2: serial@feb50000 { 1836 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1837 reg = <0x0 0xfeb50000 0x0 0x100>; 1838 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 1839 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1840 clock-names = "baudclk", "apb_pclk"; 1841 reg-shift = <2>; 1842 reg-io-width = <4>; 1843 dmas = <&dmac0 10>, <&dmac0 11>; 1844 pinctrl-names = "default"; 1845 pinctrl-0 = <&uart2m0_xfer>; 1846 status = "disabled"; 1847 }; 1848 1849 uart3: serial@feb60000 { 1850 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1851 reg = <0x0 0xfeb60000 0x0 0x100>; 1852 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 1853 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1854 clock-names = "baudclk", "apb_pclk"; 1855 reg-shift = <2>; 1856 reg-io-width = <4>; 1857 dmas = <&dmac0 12>, <&dmac0 13>; 1858 pinctrl-names = "default"; 1859 pinctrl-0 = <&uart3m0_xfer>; 1860 status = "disabled"; 1861 }; 1862 1863 uart4: serial@feb70000 { 1864 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1865 reg = <0x0 0xfeb70000 0x0 0x100>; 1866 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1867 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1868 clock-names = "baudclk", "apb_pclk"; 1869 reg-shift = <2>; 1870 reg-io-width = <4>; 1871 dmas = <&dmac1 9>, <&dmac1 10>; 1872 pinctrl-names = "default"; 1873 pinctrl-0 = <&uart4m0_xfer>; 1874 status = "disabled"; 1875 }; 1876 1877 uart5: serial@feb80000 { 1878 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1879 reg = <0x0 0xfeb80000 0x0 0x100>; 1880 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 1881 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1882 clock-names = "baudclk", "apb_pclk"; 1883 reg-shift = <2>; 1884 reg-io-width = <4>; 1885 dmas = <&dmac1 11>, <&dmac1 12>; 1886 pinctrl-names = "default"; 1887 pinctrl-0 = <&uart5m0_xfer>; 1888 status = "disabled"; 1889 }; 1890 1891 uart6: serial@feb90000 { 1892 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1893 reg = <0x0 0xfeb90000 0x0 0x100>; 1894 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 1895 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1896 clock-names = "baudclk", "apb_pclk"; 1897 reg-shift = <2>; 1898 reg-io-width = <4>; 1899 dmas = <&dmac1 13>, <&dmac1 14>; 1900 pinctrl-names = "default"; 1901 pinctrl-0 = <&uart6m0_xfer>; 1902 status = "disabled"; 1903 }; 1904 1905 uart7: serial@feba0000 { 1906 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1907 reg = <0x0 0xfeba0000 0x0 0x100>; 1908 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 1909 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1910 clock-names = "baudclk", "apb_pclk"; 1911 reg-shift = <2>; 1912 reg-io-width = <4>; 1913 dmas = <&dmac2 7>, <&dmac2 8>; 1914 pinctrl-names = "default"; 1915 pinctrl-0 = <&uart7m0_xfer>; 1916 status = "disabled"; 1917 }; 1918 1919 uart8: serial@febb0000 { 1920 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1921 reg = <0x0 0xfebb0000 0x0 0x100>; 1922 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 1923 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1924 clock-names = "baudclk", "apb_pclk"; 1925 reg-shift = <2>; 1926 reg-io-width = <4>; 1927 dmas = <&dmac2 9>, <&dmac2 10>; 1928 pinctrl-names = "default"; 1929 pinctrl-0 = <&uart8m0_xfer>; 1930 status = "disabled"; 1931 }; 1932 1933 uart9: serial@febc0000 { 1934 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1935 reg = <0x0 0xfebc0000 0x0 0x100>; 1936 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 1937 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1938 clock-names = "baudclk", "apb_pclk"; 1939 reg-shift = <2>; 1940 reg-io-width = <4>; 1941 dmas = <&dmac2 11>, <&dmac2 12>; 1942 pinctrl-names = "default"; 1943 pinctrl-0 = <&uart9m0_xfer>; 1944 status = "disabled"; 1945 }; 1946 1947 pwm4: pwm@febd0000 { 1948 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1949 reg = <0x0 0xfebd0000 0x0 0x10>; 1950 #pwm-cells = <3>; 1951 pinctrl-names = "active"; 1952 pinctrl-0 = <&pwm4m0_pins>; 1953 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1954 clock-names = "pwm", "pclk"; 1955 status = "disabled"; 1956 }; 1957 1958 pwm5: pwm@febd0010 { 1959 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1960 reg = <0x0 0xfebd0010 0x0 0x10>; 1961 #pwm-cells = <3>; 1962 pinctrl-names = "active"; 1963 pinctrl-0 = <&pwm5m0_pins>; 1964 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1965 clock-names = "pwm", "pclk"; 1966 status = "disabled"; 1967 }; 1968 1969 pwm6: pwm@febd0020 { 1970 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1971 reg = <0x0 0xfebd0020 0x0 0x10>; 1972 #pwm-cells = <3>; 1973 pinctrl-names = "active"; 1974 pinctrl-0 = <&pwm6m0_pins>; 1975 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1976 clock-names = "pwm", "pclk"; 1977 status = "disabled"; 1978 }; 1979 1980 pwm7: pwm@febd0030 { 1981 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1982 reg = <0x0 0xfebd0030 0x0 0x10>; 1983 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 1985 #pwm-cells = <3>; 1986 pinctrl-names = "active"; 1987 pinctrl-0 = <&pwm7m0_pins>; 1988 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1989 clock-names = "pwm", "pclk"; 1990 status = "disabled"; 1991 }; 1992 1993 pwm8: pwm@febe0000 { 1994 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1995 reg = <0x0 0xfebe0000 0x0 0x10>; 1996 #pwm-cells = <3>; 1997 pinctrl-names = "active"; 1998 pinctrl-0 = <&pwm8m0_pins>; 1999 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2000 clock-names = "pwm", "pclk"; 2001 status = "disabled"; 2002 }; 2003 2004 pwm9: pwm@febe0010 { 2005 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2006 reg = <0x0 0xfebe0010 0x0 0x10>; 2007 #pwm-cells = <3>; 2008 pinctrl-names = "active"; 2009 pinctrl-0 = <&pwm9m0_pins>; 2010 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2011 clock-names = "pwm", "pclk"; 2012 status = "disabled"; 2013 }; 2014 2015 pwm10: pwm@febe0020 { 2016 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2017 reg = <0x0 0xfebe0020 0x0 0x10>; 2018 #pwm-cells = <3>; 2019 pinctrl-names = "active"; 2020 pinctrl-0 = <&pwm10m0_pins>; 2021 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2022 clock-names = "pwm", "pclk"; 2023 status = "disabled"; 2024 }; 2025 2026 pwm11: pwm@febe0030 { 2027 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2028 reg = <0x0 0xfebe0030 0x0 0x10>; 2029 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 2031 #pwm-cells = <3>; 2032 pinctrl-names = "active"; 2033 pinctrl-0 = <&pwm11m0_pins>; 2034 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2035 clock-names = "pwm", "pclk"; 2036 status = "disabled"; 2037 }; 2038 2039 pwm12: pwm@febf0000 { 2040 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2041 reg = <0x0 0xfebf0000 0x0 0x10>; 2042 #pwm-cells = <3>; 2043 pinctrl-names = "active"; 2044 pinctrl-0 = <&pwm12m0_pins>; 2045 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2046 clock-names = "pwm", "pclk"; 2047 status = "disabled"; 2048 }; 2049 2050 pwm13: pwm@febf0010 { 2051 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2052 reg = <0x0 0xfebf0010 0x0 0x10>; 2053 #pwm-cells = <3>; 2054 pinctrl-names = "active"; 2055 pinctrl-0 = <&pwm13m0_pins>; 2056 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2057 clock-names = "pwm", "pclk"; 2058 status = "disabled"; 2059 }; 2060 2061 pwm14: pwm@febf0020 { 2062 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2063 reg = <0x0 0xfebf0020 0x0 0x10>; 2064 #pwm-cells = <3>; 2065 pinctrl-names = "active"; 2066 pinctrl-0 = <&pwm14m0_pins>; 2067 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2068 clock-names = "pwm", "pclk"; 2069 status = "disabled"; 2070 }; 2071 2072 pwm15: pwm@febf0030 { 2073 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2074 reg = <0x0 0xfebf0030 0x0 0x10>; 2075 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2076 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 2077 #pwm-cells = <3>; 2078 pinctrl-names = "active"; 2079 pinctrl-0 = <&pwm15m0_pins>; 2080 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2081 clock-names = "pwm", "pclk"; 2082 status = "disabled"; 2083 }; 2084 2085 tsadc: tsadc@fec00000 { 2086 compatible = "rockchip,rk3588-tsadc"; 2087 reg = <0x0 0xfec00000 0x0 0x400>; 2088 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 2089 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2090 clock-names = "tsadc", "apb_pclk"; 2091 assigned-clocks = <&cru CLK_TSADC>; 2092 assigned-clock-rates = <2000000>; 2093 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; 2094 reset-names = "tsadc", "tsadc-apb"; 2095 #thermal-sensor-cells = <1>; 2096 rockchip,hw-tshut-temp = <120000>; 2097 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 2098 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2099 pinctrl-names = "gpio", "otpout"; 2100 pinctrl-0 = <&tsadc_gpio_func>; 2101 pinctrl-1 = <&tsadc_shut_org>; 2102 status = "disabled"; 2103 }; 2104 2105 saradc: saradc@fec10000 { 2106 compatible = "rockchip,rk3588-saradc"; 2107 reg = <0x0 0xfec10000 0x0 0x10000>; 2108 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; 2109 #io-channel-cells = <1>; 2110 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2111 clock-names = "saradc", "apb_pclk"; 2112 resets = <&cru SRST_P_SARADC>; 2113 reset-names = "saradc-apb"; 2114 status = "disabled"; 2115 }; 2116 2117 mailbox0: mailbox@fec60000 { 2118 compatible = "rockchip,rk3588-mailbox", 2119 "rockchip,rk3368-mailbox"; 2120 reg = <0x0 0xfec60000 0x0 0x200>; 2121 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 2125 clocks = <&cru PCLK_MAILBOX0>; 2126 clock-names = "pclk_mailbox"; 2127 #mbox-cells = <1>; 2128 status = "disabled"; 2129 }; 2130 2131 mailbox1: mailbox@fec70000 { 2132 compatible = "rockchip,rk3588-mailbox", 2133 "rockchip,rk3368-mailbox"; 2134 reg = <0x0 0xfec70000 0x0 0x200>; 2135 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2139 clocks = <&cru PCLK_MAILBOX1>; 2140 clock-names = "pclk_mailbox"; 2141 #mbox-cells = <1>; 2142 status = "disabled"; 2143 }; 2144 2145 i2c6: i2c@fec80000 { 2146 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2147 reg = <0x0 0xfec80000 0x0 0x1000>; 2148 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2149 clock-names = "i2c", "pclk"; 2150 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 2151 pinctrl-names = "default"; 2152 pinctrl-0 = <&i2c6m0_xfer>; 2153 #address-cells = <1>; 2154 #size-cells = <0>; 2155 status = "disabled"; 2156 }; 2157 2158 i2c7: i2c@fec90000 { 2159 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2160 reg = <0x0 0xfec90000 0x0 0x1000>; 2161 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2162 clock-names = "i2c", "pclk"; 2163 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 2164 pinctrl-names = "default"; 2165 pinctrl-0 = <&i2c7m0_xfer>; 2166 #address-cells = <1>; 2167 #size-cells = <0>; 2168 status = "disabled"; 2169 }; 2170 2171 i2c8: i2c@feca0000 { 2172 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2173 reg = <0x0 0xfeca0000 0x0 0x1000>; 2174 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2175 clock-names = "i2c", "pclk"; 2176 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 2177 pinctrl-names = "default"; 2178 pinctrl-0 = <&i2c8m0_xfer>; 2179 #address-cells = <1>; 2180 #size-cells = <0>; 2181 status = "disabled"; 2182 }; 2183 2184 spi4: spi@fecb0000 { 2185 compatible = "rockchip,rk3066-spi"; 2186 reg = <0x0 0xfecb0000 0x0 0x1000>; 2187 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2188 #address-cells = <1>; 2189 #size-cells = <0>; 2190 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2191 clock-names = "spiclk", "apb_pclk"; 2192 dmas = <&dmac2 13>, <&dmac2 14>; 2193 dma-names = "tx", "rx"; 2194 pinctrl-names = "default", "high_speed"; 2195 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2196 pinctrl-1 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins_hs>; 2197 num-cs = <2>; 2198 status = "disabled"; 2199 }; 2200 2201 otp: otp@fecc0000 { 2202 compatible = "rockchip,rk3588-otp"; 2203 reg = <0x0 0xfecc0000 0x0 0x400>; 2204 #address-cells = <1>; 2205 #size-cells = <1>; 2206 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2207 <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>; 2208 clock-names = "otpc", "apb", "arb", "phy"; 2209 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2210 <&cru SRST_OTPC_ARB>; 2211 reset-names = "otpc", "apb", "arb"; 2212 }; 2213 2214 mailbox2: mailbox@fece0000 { 2215 compatible = "rockchip,rk3588-mailbox", 2216 "rockchip,rk3368-mailbox"; 2217 reg = <0x0 0xfece0000 0x0 0x200>; 2218 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2222 clocks = <&cru PCLK_MAILBOX2>; 2223 clock-names = "pclk_mailbox"; 2224 #mbox-cells = <1>; 2225 status = "disabled"; 2226 }; 2227 2228 dmac2: dma-controller@fed10000 { 2229 compatible = "arm,pl330", "arm,primecell"; 2230 reg = <0x0 0xfed10000 0x0 0x4000>; 2231 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2233 clocks = <&cru ACLK_DMAC2>; 2234 clock-names = "apb_pclk"; 2235 #dma-cells = <1>; 2236 arm,pl330-periph-burst; 2237 }; 2238 2239 hdptxphy0: phy@fed60000 { 2240 compatible = "rockchip,rk3588-hdptx-phy"; 2241 reg = <0x0 0xfed60000 0x0 0x2000>; 2242 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 2243 clock-names = "ref", "apb"; 2244 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 2245 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 2246 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 2247 <&cru SRST_HDPTX0_LCPLL>; 2248 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 2249 "lcpll"; 2250 rockchip,grf = <&hdptxphy0_grf>; 2251 #phy-cells = <0>; 2252 status = "disabled"; 2253 }; 2254 2255 usbdp_phy0: phy@fed80000 { 2256 compatible = "rockchip,rk3588-usbdp-phy"; 2257 reg = <0x0 0xfed80000 0x0 0x10000>; 2258 rockchip,usb-grf = <&usb_grf>; 2259 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 2260 rockchip,vo-grf = <&vo0_grf>; 2261 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 2262 <&cru CLK_USBDP_PHY0_IMMORTAL>, 2263 <&cru PCLK_USBDPPHY0>; 2264 clock-names = "refclk", "immortal", "pclk"; 2265 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 2266 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 2267 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 2268 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 2269 <&cru SRST_P_USBDPPHY0>; 2270 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2271 status = "disabled"; 2272 2273 usbdp_phy0_dp: dp-port { 2274 #phy-cells = <0>; 2275 status = "disabled"; 2276 }; 2277 2278 usbdp_phy0_u3: u3-port { 2279 #phy-cells = <0>; 2280 status = "disabled"; 2281 }; 2282 }; 2283 2284 combphy0_ps: phy@fee00000 { 2285 compatible = "rockchip,rk3588-naneng-combphy"; 2286 reg = <0x0 0xfee00000 0x0 0x100>; 2287 #phy-cells = <1>; 2288 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>; 2289 clock-names = "refclk", "apbclk"; 2290 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 2291 assigned-clock-rates = <100000000>; 2292 resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>; 2293 reset-names = "combphy-apb", "combphy"; 2294 rockchip,pipe-grf = <&php_grf>; 2295 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2296 status = "disabled"; 2297 }; 2298 2299 combphy2_psu: phy@fee20000 { 2300 compatible = "rockchip,rk3588-naneng-combphy"; 2301 reg = <0x0 0xfee20000 0x0 0x100>; 2302 #phy-cells = <1>; 2303 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>; 2304 clock-names = "refclk", "apbclk"; 2305 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 2306 assigned-clock-rates = <100000000>; 2307 resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>; 2308 reset-names = "combphy-apb", "combphy"; 2309 rockchip,pipe-grf = <&php_grf>; 2310 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 2311 rockchip,pcie1ln-sel-bits = <0x100 1 1 0>; 2312 status = "disabled"; 2313 }; 2314 2315 pinctrl: pinctrl { 2316 compatible = "rockchip,rk3588-pinctrl"; 2317 rockchip,grf = <&ioc>; 2318 #address-cells = <2>; 2319 #size-cells = <2>; 2320 ranges; 2321 2322 gpio0: gpio@fd8a0000 { 2323 compatible = "rockchip,gpio-bank"; 2324 reg = <0x0 0xfd8a0000 0x0 0x100>; 2325 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 2326 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2327 2328 gpio-controller; 2329 #gpio-cells = <2>; 2330 gpio-ranges = <&pinctrl 0 0 32>; 2331 interrupt-controller; 2332 #interrupt-cells = <2>; 2333 }; 2334 2335 gpio1: gpio@fec20000 { 2336 compatible = "rockchip,gpio-bank"; 2337 reg = <0x0 0xfec20000 0x0 0x100>; 2338 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 2339 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2340 2341 gpio-controller; 2342 #gpio-cells = <2>; 2343 gpio-ranges = <&pinctrl 0 32 32>; 2344 interrupt-controller; 2345 #interrupt-cells = <2>; 2346 }; 2347 2348 gpio2: gpio@fec30000 { 2349 compatible = "rockchip,gpio-bank"; 2350 reg = <0x0 0xfec30000 0x0 0x100>; 2351 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; 2352 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2353 2354 gpio-controller; 2355 #gpio-cells = <2>; 2356 gpio-ranges = <&pinctrl 0 64 32>; 2357 interrupt-controller; 2358 #interrupt-cells = <2>; 2359 }; 2360 2361 gpio3: gpio@fec40000 { 2362 compatible = "rockchip,gpio-bank"; 2363 reg = <0x0 0xfec40000 0x0 0x100>; 2364 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 2365 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2366 2367 gpio-controller; 2368 #gpio-cells = <2>; 2369 gpio-ranges = <&pinctrl 0 96 32>; 2370 interrupt-controller; 2371 #interrupt-cells = <2>; 2372 }; 2373 2374 gpio4: gpio@fec50000 { 2375 compatible = "rockchip,gpio-bank"; 2376 reg = <0x0 0xfec50000 0x0 0x100>; 2377 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; 2378 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2379 2380 gpio-controller; 2381 #gpio-cells = <2>; 2382 gpio-ranges = <&pinctrl 0 128 32>; 2383 interrupt-controller; 2384 #interrupt-cells = <2>; 2385 }; 2386 }; 2387}; 2388 2389#include "rk3588s-pinctrl.dtsi" 2390