1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/phy/phy-snps-pcie3.h> 7#include "rk3588s.dtsi" 8#include "rk3588-vccio3-pinctrl.dtsi" 9 10/ { 11 aliases { 12 edp0 = &edp0; 13 edp1 = &edp1; 14 ethernet0 = &gmac0; 15 hdptx0 = &hdptxphy0; 16 hdptx1 = &hdptxphy1; 17 }; 18 19 usbdrd3_1: usbdrd3_1 { 20 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 21 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, 22 <&cru ACLK_USB3OTG1>; 23 clock-names = "ref", "suspend", "bus"; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 status = "disabled"; 28 29 usbdrd_dwc3_1: usb@fc400000 { 30 compatible = "snps,dwc3"; 31 reg = <0x0 0xfc400000 0x0 0x400000>; 32 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 33 power-domains = <&power RK3588_PD_USB>; 34 resets = <&cru SRST_A_USB3OTG1>; 35 reset-names = "usb3-otg"; 36 dr_mode = "host"; 37 phy_type = "utmi_wide"; 38 snps,dis_enblslpm_quirk; 39 snps,dis-u2-freeclk-exists-quirk; 40 snps,dis-del-phy-power-chg-quirk; 41 snps,dis-tx-ipgap-linecheck-quirk; 42 status = "disabled"; 43 }; 44 }; 45 46 pcie30_phy_grf: syscon@fd5b8000 { 47 compatible = "rockchip,pcie30-phy-grf", "syscon"; 48 reg = <0x0 0xfd5b8000 0x0 0x10000>; 49 }; 50 51 pipe_phy1_grf: syscon@fd5c0000 { 52 compatible = "rockchip,pipe-phy-grf", "syscon"; 53 reg = <0x0 0xfd5c0000 0x0 0x100>; 54 }; 55 56 usbdpphy1_grf: syscon@fd5cc000 { 57 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 58 reg = <0x0 0xfd5cc000 0x0 0x4000>; 59 }; 60 61 usb2phy1_grf: syscon@fd5d4000 { 62 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 63 "simple-mfd"; 64 reg = <0x0 0xfd5d4000 0x0 0x4000>; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 68 u2phy1: usb2-phy@4000 { 69 compatible = "rockchip,rk3588-usb2phy"; 70 reg = <0x4000 0x10>; 71 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 72 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 73 clock-names = "phyclk"; 74 #clock-cells = <0>; 75 status = "disabled"; 76 77 u2phy1_otg: otg-port { 78 #phy-cells = <0>; 79 status = "disabled"; 80 }; 81 }; 82 }; 83 84 hdptxphy1_grf: syscon@fd5e4000 { 85 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 86 reg = <0x0 0xfd5e4000 0x0 0x100>; 87 }; 88 89 spdif_tx5: spdif-tx@fddb8000 { 90 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 91 reg = <0x0 0xfddb8000 0x0 0x1000>; 92 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 93 dmas = <&dmac1 22>; 94 dma-names = "tx"; 95 clock-names = "mclk", "hclk"; 96 clocks = <&cru MCLK_SPDIF5_DP1>, <&cru HCLK_SPDIF5_DP1>; 97 #sound-dai-cells = <0>; 98 status = "disabled"; 99 }; 100 101 i2s8_8ch: i2s@fddc8000 { 102 compatible = "rockchip,rk3588-i2s-tdm"; 103 reg = <0x0 0xfddc8000 0x0 0x1000>; 104 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 105 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 106 clock-names = "mclk_tx", "hclk"; 107 dmas = <&dmac2 22>; 108 dma-names = "tx"; 109 resets = <&cru SRST_M_I2S8_8CH_TX>; 110 reset-names = "tx-m"; 111 #sound-dai-cells = <0>; 112 status = "disabled"; 113 }; 114 115 spdif_tx4: spdif-tx@fdde8000 { 116 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 117 reg = <0x0 0xfdde8000 0x0 0x1000>; 118 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 119 dmas = <&dmac1 8>; 120 dma-names = "tx"; 121 clock-names = "mclk", "hclk"; 122 clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; 123 #sound-dai-cells = <0>; 124 status = "disabled"; 125 }; 126 127 i2s6_8ch: i2s@fddf4000 { 128 compatible = "rockchip,rk3588-i2s-tdm"; 129 reg = <0x0 0xfddf4000 0x0 0x1000>; 130 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; 132 clock-names = "mclk_tx", "hclk"; 133 dmas = <&dmac2 4>; 134 dma-names = "tx"; 135 resets = <&cru SRST_M_I2S6_8CH_TX>; 136 reset-names = "tx-m"; 137 #sound-dai-cells = <0>; 138 status = "disabled"; 139 }; 140 141 i2s7_8ch: i2s@fddf8000 { 142 compatible = "rockchip,rk3588-i2s-tdm"; 143 reg = <0x0 0xfddf8000 0x0 0x1000>; 144 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; 146 clock-names = "mclk_rx", "hclk"; 147 dmas = <&dmac2 21>; 148 dma-names = "rx"; 149 resets = <&cru SRST_M_I2S7_8CH_RX>; 150 reset-names = "rx-m"; 151 #sound-dai-cells = <0>; 152 status = "disabled"; 153 }; 154 155 i2s10_8ch: i2s@fde00000 { 156 compatible = "rockchip,rk3588-i2s-tdm"; 157 reg = <0x0 0xfde00000 0x0 0x1000>; 158 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; 160 clock-names = "mclk_rx", "hclk"; 161 dmas = <&dmac2 24>; 162 dma-names = "rx"; 163 resets = <&cru SRST_M_I2S10_8CH_RX>; 164 reset-names = "rx-m"; 165 #sound-dai-cells = <0>; 166 status = "disabled"; 167 }; 168 169 spdif_rx1: spdif-rx@fde10000 { 170 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; 171 reg = <0x0 0xfde10000 0x0 0x1000>; 172 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 173 clocks = <&cru MCLK_SPDIFRX1>, <&cru HCLK_SPDIFRX1>; 174 clock-names = "mclk", "hclk"; 175 dmas = <&dmac0 22>; 176 dma-names = "rx"; 177 resets = <&cru SRST_M_SPDIFRX1>; 178 reset-names = "spdifrx-m"; 179 #sound-dai-cells = <0>; 180 status = "disabled"; 181 }; 182 183 spdif_rx2: spdif-rx@fde18000 { 184 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; 185 reg = <0x0 0xfde18000 0x0 0x1000>; 186 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&cru MCLK_SPDIFRX2>, <&cru HCLK_SPDIFRX2>; 188 clock-names = "mclk", "hclk"; 189 dmas = <&dmac0 23>; 190 dma-names = "rx"; 191 resets = <&cru SRST_M_SPDIFRX2>; 192 reset-names = "spdifrx-m"; 193 #sound-dai-cells = <0>; 194 status = "disabled"; 195 }; 196 197 edp1: edp@fded0000 { 198 compatible = "rockchip,rk3588-edp"; 199 reg = <0x0 0xfded0000 0x0 0x1000>; 200 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 201 clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>, 202 <&cru CLK_EDP1_200M>; 203 clock-names = "dp", "pclk", "spdif"; 204 resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>; 205 reset-names = "dp", "apb"; 206 phys = <&hdptxphy1>; 207 phy-names = "dp"; 208 power-domains = <&power RK3588_PD_VO1>; 209 rockchip,grf = <&vo1_grf>; 210 status = "disabled"; 211 }; 212 213 pcie3x4: pcie@fe150000 { 214 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 215 #address-cells = <3>; 216 #size-cells = <2>; 217 bus-range = <0x00 0x0f>; 218 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 219 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 220 <&cru CLK_PCIE_AUX0>; 221 clock-names = "aclk_mst", "aclk_slv", 222 "aclk_dbi", "pclk", "aux"; 223 device_type = "pci"; 224 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 229 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 230 #interrupt-cells = <1>; 231 interrupt-map-mask = <0 0 0 7>; 232 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, 233 <0 0 0 2 &pcie3x4_intc 1>, 234 <0 0 0 3 &pcie3x4_intc 2>, 235 <0 0 0 4 &pcie3x4_intc 3>; 236 linux,pci-domain = <0>; 237 num-ib-windows = <16>; 238 num-ob-windows = <16>; 239 max-link-speed = <3>; 240 msi-map = <0x0000 &its 0x0000 0x1000>; 241 num-lanes = <4>; 242 phys = <&pcie30phy>; 243 phy-names = "pcie-phy"; 244 power-domains = <&power RK3588_PD_PCIE>; 245 ranges = <0x00000800 0x0 0x80000000 0x9 0x00000000 0x0 0x800000 246 0x81000000 0x0 0x80800000 0x9 0x00800000 0x0 0x100000 247 0x83000000 0x0 0x80900000 0x9 0x00900000 0x0 0x3f700000>; 248 reg = <0xa 0x40000000 0x0 0x400000>, 249 <0x0 0xfe150000 0x0 0x10000>; 250 reg-names = "pcie-dbi", "pcie-apb"; 251 resets = <&cru SRST_PCIE0_POWER_UP>; 252 reset-names = "pipe"; 253 status = "disabled"; 254 255 pcie3x4_intc: legacy-interrupt-controller { 256 interrupt-controller; 257 #address-cells = <0>; 258 #interrupt-cells = <1>; 259 interrupt-parent = <&gic>; 260 interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>; 261 }; 262 }; 263 264 pcie3x2: pcie@fe160000 { 265 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 266 #address-cells = <3>; 267 #size-cells = <2>; 268 bus-range = <0x10 0x1f>; 269 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, 270 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, 271 <&cru CLK_PCIE_AUX1>; 272 clock-names = "aclk_mst", "aclk_slv", 273 "aclk_dbi", "pclk", "aux"; 274 device_type = "pci"; 275 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 280 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 281 #interrupt-cells = <1>; 282 interrupt-map-mask = <0 0 0 7>; 283 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 284 <0 0 0 2 &pcie3x2_intc 1>, 285 <0 0 0 3 &pcie3x2_intc 2>, 286 <0 0 0 4 &pcie3x2_intc 3>; 287 linux,pci-domain = <1>; 288 num-ib-windows = <16>; 289 num-ob-windows = <16>; 290 max-link-speed = <3>; 291 msi-map = <0x1000 &its 0x1000 0x1000>; 292 num-lanes = <2>; 293 phys = <&pcie30phy>; 294 phy-names = "pcie-phy"; 295 power-domains = <&power RK3588_PD_PHP>; 296 ranges = <0x00000800 0x0 0x80000000 0x9 0x40000000 0x0 0x800000 297 0x81000000 0x0 0x80800000 0x9 0x40800000 0x0 0x100000 298 0x83000000 0x0 0x80900000 0x9 0x40900000 0x0 0x3f700000>; 299 reg = <0xa 0x40400000 0x0 0x400000>, 300 <0x0 0xfe160000 0x0 0x10000>; 301 reg-names = "pcie-dbi", "pcie-apb"; 302 resets = <&cru SRST_PCIE1_POWER_UP>; 303 reset-names = "pipe"; 304 status = "disabled"; 305 306 pcie3x2_intc: legacy-interrupt-controller { 307 interrupt-controller; 308 #address-cells = <0>; 309 #interrupt-cells = <1>; 310 interrupt-parent = <&gic>; 311 interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>; 312 }; 313 }; 314 315 pcie2x1l0: pcie@fe170000 { 316 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 317 #address-cells = <3>; 318 #size-cells = <2>; 319 bus-range = <0x20 0x2f>; 320 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, 321 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, 322 <&cru CLK_PCIE_AUX2>; 323 clock-names = "aclk_mst", "aclk_slv", 324 "aclk_dbi", "pclk", "aux"; 325 device_type = "pci"; 326 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 331 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 332 #interrupt-cells = <1>; 333 interrupt-map-mask = <0 0 0 7>; 334 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, 335 <0 0 0 2 &pcie2x1l0_intc 1>, 336 <0 0 0 3 &pcie2x1l0_intc 2>, 337 <0 0 0 4 &pcie2x1l0_intc 3>; 338 linux,pci-domain = <2>; 339 num-ib-windows = <8>; 340 num-ob-windows = <8>; 341 max-link-speed = <2>; 342 msi-map = <0x2000 &its 0x2000 0x1000>; 343 num-lanes = <1>; 344 phys = <&combphy1_ps PHY_TYPE_PCIE>; 345 phy-names = "pcie-phy"; 346 power-domains = <&power RK3588_PD_PHP>; 347 ranges = <0x00000800 0x0 0x80000000 0x9 0x80000000 0x0 0x800000 348 0x81000000 0x0 0x80800000 0x9 0x80800000 0x0 0x100000 349 0x83000000 0x0 0x80900000 0x9 0x80900000 0x0 0x3f700000>; 350 reg = <0xa 0x40800000 0x0 0x400000>, 351 <0x0 0xfe170000 0x0 0x10000>; 352 reg-names = "pcie-dbi", "pcie-apb"; 353 resets = <&cru SRST_PCIE2_POWER_UP>; 354 reset-names = "pipe"; 355 status = "disabled"; 356 357 pcie2x1l0_intc: legacy-interrupt-controller { 358 interrupt-controller; 359 #address-cells = <0>; 360 #interrupt-cells = <1>; 361 interrupt-parent = <&gic>; 362 interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>; 363 }; 364 }; 365 366 gmac0: ethernet@fe1b0000 { 367 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 368 reg = <0x0 0xfe1b0000 0x0 0x10000>; 369 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 371 interrupt-names = "macirq", "eth_wake_irq"; 372 rockchip,grf = <&sys_grf>; 373 rockchip,php_grf = <&php_grf>; 374 clocks = <&cru CLK_GMAC0>, <&cru ACLK_GMAC0>, 375 <&cru PCLK_GMAC0>, <&cru CLK_GMAC0_PTP_REF>; 376 clock-names = "stmmaceth", "aclk_mac", 377 "pclk_mac", "ptp_ref"; 378 resets = <&cru SRST_A_GMAC0>; 379 reset-names = "stmmaceth"; 380 381 snps,mixed-burst; 382 snps,tso; 383 384 snps,axi-config = <&gmac0_stmmac_axi_setup>; 385 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 386 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 387 status = "disabled"; 388 389 mdio0: mdio { 390 compatible = "snps,dwmac-mdio"; 391 #address-cells = <0x1>; 392 #size-cells = <0x0>; 393 }; 394 395 gmac0_stmmac_axi_setup: stmmac-axi-config { 396 snps,wr_osr_lmt = <4>; 397 snps,rd_osr_lmt = <8>; 398 snps,blen = <0 0 0 0 16 8 4>; 399 }; 400 401 gmac0_mtl_rx_setup: rx-queues-config { 402 snps,rx-queues-to-use = <2>; 403 queue0 {}; 404 queue1 {}; 405 }; 406 407 gmac0_mtl_tx_setup: tx-queues-config { 408 snps,tx-queues-to-use = <2>; 409 queue0 {}; 410 queue1 {}; 411 }; 412 }; 413 414 sata1: sata@fe220000 { 415 compatible = "snps,dwc-ahci"; 416 reg = <0 0xfe220000 0 0x1000>; 417 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 418 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>; 419 clock-names = "sata", "pmalive", "rxoob", "ref"; 420 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 421 interrupt-names = "hostc"; 422 phys = <&combphy1_ps PHY_TYPE_SATA>; 423 phy-names = "sata-phy"; 424 ports-implemented = <0x1>; 425 power-domains = <&power RK3588_PD_PHP>; 426 status = "disabled"; 427 }; 428 429 crypto: crypto@fe370000 { 430 compatible = "rockchip,rk3588-crypto"; 431 reg = <0x0 0xfe370000 0x0 0x4000>; 432 clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_CRYPTO_PKA>; 433 clock-names = "sclk_crypto", "apkclk_crypto"; 434 clock-frequency = <350000000>, <350000000>; 435 status = "disabled"; 436 }; 437 438 rng: rng@fe378000 { 439 compatible = "rockchip,trngv1"; 440 reg = <0x0 0xfe378000 0x0 0x200>; 441 status = "disabled"; 442 }; 443 444 hdptxphy1: phy@fed70000 { 445 compatible = "rockchip,rk3588-hdptx-phy"; 446 reg = <0x0 0xfed70000 0x0 0x2000>; 447 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; 448 clock-names = "ref", "apb"; 449 resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, 450 <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, 451 <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, 452 <&cru SRST_HDPTX1_LCPLL>; 453 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 454 "lcpll"; 455 rockchip,grf = <&hdptxphy1_grf>; 456 #phy-cells = <0>; 457 status = "disabled"; 458 }; 459 460 usbdp_phy1: phy@fed90000 { 461 compatible = "rockchip,rk3588-usbdp-phy"; 462 reg = <0x0 0xfed90000 0x0 0x10000>; 463 rockchip,usb-grf = <&usb_grf>; 464 rockchip,usbdpphy-grf = <&usbdpphy1_grf>; 465 rockchip,vo-grf = <&vo0_grf>; 466 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 467 <&cru CLK_USBDP_PHY1_IMMORTAL>, 468 <&cru PCLK_USBDPPHY1>; 469 clock-names = "refclk", "immortal", "pclk"; 470 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, 471 <&cru SRST_USBDP_COMBO_PHY1_CMN>, 472 <&cru SRST_USBDP_COMBO_PHY1_LANE>, 473 <&cru SRST_USBDP_COMBO_PHY1_PCS>, 474 <&cru SRST_P_USBDPPHY1>; 475 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 476 status = "disabled"; 477 478 usbdp_phy1_dp: dp-port { 479 #phy-cells = <0>; 480 status = "disabled"; 481 }; 482 483 usbdp_phy1_u3: u3-port { 484 #phy-cells = <0>; 485 status = "disabled"; 486 }; 487 }; 488 489 combphy1_ps: phy@fee10000 { 490 compatible = "rockchip,rk3588-naneng-combphy"; 491 reg = <0x0 0xfee10000 0x0 0x100>; 492 #phy-cells = <1>; 493 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>; 494 clock-names = "refclk", "apbclk"; 495 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; 496 assigned-clock-rates = <100000000>; 497 resets = <&cru SRST_P_PCIE2_PHY1>, <&cru SRST_REF_PIPE_PHY1>; 498 reset-names = "combphy-apb", "combphy"; 499 rockchip,pipe-grf = <&php_grf>; 500 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 501 rockchip,pcie1ln-sel-bits = <0x100 0 0 0>; 502 status = "disabled"; 503 }; 504 505 pcie30phy: phy@fee80000 { 506 compatible = "rockchip,rk3588-pcie3-phy"; 507 reg = <0x0 0xfee80000 0x0 0x20000>; 508 #phy-cells = <0>; 509 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; 510 clock-names = "pclk"; 511 resets = <&cru SRST_PCIE30_PHY>; 512 reset-names = "phy"; 513 rockchip,pipe-grf = <&php_grf>; 514 rockchip,phy-grf = <&pcie30_phy_grf>; 515 status = "disabled"; 516 }; 517 518}; 519