1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3576-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rk3576-power.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/soc/rockchip-system-status.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 compatible = "rockchip,rk3576"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 csi2dcphy0 = &csi2_dcphy0; 25 csi2dphy0 = &csi2_dphy0; 26 csi2dphy1 = &csi2_dphy1; 27 csi2dphy2 = &csi2_dphy2; 28 csi2dphy3 = &csi2_dphy3; 29 csi2dphy4 = &csi2_dphy4; 30 csi2dphy5 = &csi2_dphy5; 31 ethernet0 = &gmac0; 32 ethernet1 = &gmac1; 33 gpio0 = &gpio0; 34 gpio1 = &gpio1; 35 gpio2 = &gpio2; 36 gpio3 = &gpio3; 37 gpio4 = &gpio4; 38 hdcp0 = &hdcp0; 39 hdcp1 = &hdcp1; 40 i2c0 = &i2c0; 41 i2c1 = &i2c1; 42 i2c2 = &i2c2; 43 i2c3 = &i2c3; 44 i2c4 = &i2c4; 45 i2c5 = &i2c5; 46 i2c6 = &i2c6; 47 i2c7 = &i2c7; 48 i2c8 = &i2c8; 49 i2c9 = &i2c9; 50 i3c0 = &i3c0; 51 i3c1 = &i3c1; 52 rkcif_mipi_lvds0 = &rkcif_mipi_lvds; 53 rkcif_mipi_lvds1 = &rkcif_mipi_lvds1; 54 rkcif_mipi_lvds2 = &rkcif_mipi_lvds2; 55 rkcif_mipi_lvds3 = &rkcif_mipi_lvds3; 56 rkcif_mipi_lvds4 = &rkcif_mipi_lvds4; 57 serial0 = &uart0; 58 serial1 = &uart1; 59 serial2 = &uart2; 60 serial3 = &uart3; 61 serial4 = &uart4; 62 serial5 = &uart5; 63 serial6 = &uart6; 64 serial7 = &uart7; 65 serial8 = &uart8; 66 serial9 = &uart9; 67 serial10 = &uart10; 68 serial11 = &uart11; 69 spi0 = &spi0; 70 spi1 = &spi1; 71 spi2 = &spi2; 72 spi3 = &spi3; 73 spi4 = &spi4; 74 spi5 = &sfc0; 75 spi6 = &sfc1; 76 }; 77 78 clocks { 79 compatible = "simple-bus"; 80 #address-cells = <2>; 81 #size-cells = <2>; 82 ranges; 83 84 xin32k: xin32k { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <32768>; 88 clock-output-names = "xin32k"; 89 }; 90 91 xin24m: xin24m { 92 compatible = "fixed-clock"; 93 #clock-cells = <0>; 94 clock-frequency = <24000000>; 95 clock-output-names = "xin24m"; 96 }; 97 98 spll: spll { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <702000000>; 102 clock-output-names = "spll"; 103 }; 104 105 mclkin_sai0: mclkin-sai0 { 106 compatible = "fixed-clock"; 107 #clock-cells = <0>; 108 clock-frequency = <0>; 109 clock-output-names = "sai0_mclkin"; 110 }; 111 112 mclkin_sai1: mclkin-sai1 { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <0>; 116 clock-output-names = "sai1_mclkin"; 117 }; 118 119 mclkin_sai2: mclkin-sai2 { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 clock-frequency = <0>; 123 clock-output-names = "sai2_mclkin"; 124 }; 125 126 mclkin_sai3: mclkin-sai3 { 127 compatible = "fixed-clock"; 128 #clock-cells = <0>; 129 clock-frequency = <0>; 130 clock-output-names = "sai3_mclkin"; 131 }; 132 133 mclkin_sai4: mclkin-sai4 { 134 compatible = "fixed-clock"; 135 #clock-cells = <0>; 136 clock-frequency = <0>; 137 clock-output-names = "sai4_mclkin"; 138 }; 139 140 mclkout_sai0: mclkout-sai0@26046400 { 141 compatible = "rockchip,clk-out"; 142 reg = <0 0x26046400 0 0x4>; 143 clocks = <&cru CLK_SAI0_MCLKOUT>; 144 #clock-cells = <0>; 145 clock-output-names = "mclk_sai0_to_io"; 146 rockchip,bit-shift = <0>; 147 rockchip,bit-set-to-disable; 148 }; 149 150 mclkout_sai1: mclkout-sai1@26046400 { 151 compatible = "rockchip,clk-out"; 152 reg = <0 0x26046400 0 0x4>; 153 clocks = <&cru CLK_SAI1_MCLKOUT>; 154 #clock-cells = <0>; 155 clock-output-names = "mclk_sai1_to_io"; 156 rockchip,bit-shift = <1>; 157 rockchip,bit-set-to-disable; 158 }; 159 160 mclkout_sai2: mclkout-sai2@26046400 { 161 compatible = "rockchip,clk-out"; 162 reg = <0 0x26046400 0 0x4>; 163 clocks = <&cru CLK_SAI2_MCLKOUT>; 164 #clock-cells = <0>; 165 clock-output-names = "mclk_sai2_to_io"; 166 rockchip,bit-shift = <2>; 167 rockchip,bit-set-to-disable; 168 }; 169 170 mclkout_sai3: mclkout-sai3@26046400 { 171 compatible = "rockchip,clk-out"; 172 reg = <0 0x26046400 0 0x4>; 173 clocks = <&cru CLK_SAI3_MCLKOUT>; 174 #clock-cells = <0>; 175 clock-output-names = "mclk_sai3_to_io"; 176 rockchip,bit-shift = <3>; 177 rockchip,bit-set-to-disable; 178 }; 179 180 mclkout_sai4: mclkout-sai4@26046400 { 181 compatible = "rockchip,clk-out"; 182 reg = <0 0x26046400 0 0x4>; 183 clocks = <&cru CLK_SAI4_MCLKOUT>; 184 #clock-cells = <0>; 185 clock-output-names = "mclk_sai4_to_io"; 186 rockchip,bit-shift = <4>; 187 rockchip,bit-set-to-disable; 188 }; 189 190 mclkout_sai4m2: mclkout-sai4m2@2604a400 { 191 compatible = "rockchip,clk-out"; 192 reg = <0 0x2604a400 0 0x4>; 193 clocks = <&cru CLK_SAI4_MCLKOUT>; 194 #clock-cells = <0>; 195 clock-output-names = "mclk_sai4_to_io"; 196 rockchip,bit-shift = <0>; 197 rockchip,bit-set-to-disable; 198 }; 199 200 sclkin_sai0: sclkin-sai0 { 201 compatible = "fixed-clock"; 202 #clock-cells = <0>; 203 clock-frequency = <0>; 204 clock-output-names = "sai0_sclk_in"; 205 }; 206 207 sclkin_sai1: sclkin-sai1 { 208 compatible = "fixed-clock"; 209 #clock-cells = <0>; 210 clock-frequency = <0>; 211 clock-output-names = "sai1_sclk_in"; 212 }; 213 214 sclkin_sai2: sclkin-sai2 { 215 compatible = "fixed-clock"; 216 #clock-cells = <0>; 217 clock-frequency = <0>; 218 clock-output-names = "sai2_sclk_in"; 219 }; 220 221 sclkin_sai3: sclkin-sai3 { 222 compatible = "fixed-clock"; 223 #clock-cells = <0>; 224 clock-frequency = <0>; 225 clock-output-names = "sai3_sclk_in"; 226 }; 227 228 sclkin_sai4: sclkin-sai4 { 229 compatible = "fixed-clock"; 230 #clock-cells = <0>; 231 clock-frequency = <0>; 232 clock-output-names = "sai4_sclk_in"; 233 }; 234 235 clk_pvtm_clkout: clk_pvtm_clkout { 236 compatible = "fixed-clock"; 237 #clock-cells = <0>; 238 clock-frequency = <32768>; 239 clock-output-names = "clk_pvtm_clkout"; 240 }; 241 242 aclk_usb: aclk_usb@272008bc { 243 compatible = "rockchip,rk3576-clock-gate-link"; 244 reg = <0 0x272008bc 0 0x10>; 245 clock-names = "link"; 246 clocks = <&cru ACLK_VOP_ROOT>; 247 #power-domain-cells = <1>; 248 #clock-cells = <0>; 249 }; 250 251 aclk_ufs: aclk_ufs@272008bc { 252 compatible = "rockchip,rk3576-clock-gate-link"; 253 reg = <0 0x272008bc 0 0x10>; 254 clock-names = "link"; 255 clocks = <&aclk_usb>; 256 #power-domain-cells = <1>; 257 #clock-cells = <0>; 258 }; 259 260 pclk_usbufs: pclk_usbufs@272008bc { 261 compatible = "rockchip,rk3576-clock-gate-link"; 262 reg = <0 0x272008bc 0 0x10>; 263 clock-names = "link"; 264 clocks = <&cru HCLK_VOP_ROOT>; 265 #power-domain-cells = <1>; 266 #clock-cells = <0>; 267 }; 268 269 aclk_hdcp1: aclk_hdcp1@27200910 { 270 compatible = "rockchip,rk3576-clock-gate-link"; 271 reg = <0 0x27200910 0 0x10>; 272 clock-names = "link"; 273 clocks = <&cru ACLK_VOP_ROOT>; 274 #power-domain-cells = <1>; 275 #clock-cells = <0>; 276 }; 277 278 aclk_hdcp0: aclk_hdcp0@272008fc { 279 compatible = "rockchip,rk3576-clock-gate-link"; 280 reg = <0 0x272008fc 0 0x10>; 281 clock-names = "link"; 282 clocks = <&cru ACLK_VOP_ROOT>; 283 #power-domain-cells = <1>; 284 #clock-cells = <0>; 285 }; 286 287 aclk_sdgmac: aclk_sdgmac@272008a8 { 288 compatible = "rockchip,rk3576-clock-gate-link"; 289 reg = <0 0x272008a8 0 0x10>; 290 clock-names = "link"; 291 clocks = <&cru ACLK_NVM_ROOT>; 292 #power-domain-cells = <1>; 293 #clock-cells = <0>; 294 }; 295 296 hclk_sdgmac: hclk_sdgmac@272008a8 { 297 compatible = "rockchip,rk3576-clock-gate-link"; 298 reg = <0 0x272008a8 0 0x10>; 299 clock-names = "link"; 300 clocks = <&aclk_sdgmac>; 301 #power-domain-cells = <1>; 302 #clock-cells = <0>; 303 }; 304 305 aclk_vdpp: aclk_vdpp@272008c8 { 306 compatible = "rockchip,rk3576-clock-gate-link"; 307 reg = <0 0x272008c8 0 0x10>; 308 clock-names = "link"; 309 clocks = <&cru ACLK_VPU_ROOT>; 310 #power-domain-cells = <1>; 311 #clock-cells = <0>; 312 }; 313 314 aclk_ebc: aclk_ebc@272008c8 { 315 compatible = "rockchip,rk3576-clock-gate-link"; 316 reg = <0 0x272008c8 0 0x10>; 317 clock-names = "link"; 318 clocks = <&cru ACLK_VPU_ROOT>; 319 #power-domain-cells = <1>; 320 #clock-cells = <0>; 321 }; 322 323 aclk_jpeg: aclk_jpeg@272008c8 { 324 compatible = "rockchip,rk3576-clock-gate-link"; 325 reg = <0 0x272008c8 0 0x10>; 326 clock-names = "link"; 327 clocks = <&cru ACLK_VPU_ROOT>; 328 #power-domain-cells = <1>; 329 #clock-cells = <0>; 330 }; 331 332 aclk_vepu0: aclk_vepu0@272008cc { 333 compatible = "rockchip,rk3576-clock-gate-link"; 334 reg = <0 0x272008cc 0 0x10>; 335 clock-names = "link"; 336 clocks = <&cru ACLK_VI_ROOT>; 337 #power-domain-cells = <1>; 338 #clock-cells = <0>; 339 }; 340 341 hclk_vo1: hclk_vo1@2720090c { 342 compatible = "rockchip,rk3576-clock-gate-link"; 343 reg = <0 0x2720090c 0 0x10>; 344 clock-names = "link"; 345 clocks = <&cru HCLK_VOP_ROOT>; 346 #power-domain-cells = <1>; 347 #clock-cells = <0>; 348 }; 349 350 hclk_vo0: hclk_vo0@272008fc { 351 compatible = "rockchip,rk3576-clock-gate-link"; 352 reg = <0 0x272008fc 0 0x10>; 353 clock-names = "link"; 354 clocks = <&cru HCLK_VOP_ROOT>; 355 #power-domain-cells = <1>; 356 #clock-cells = <0>; 357 }; 358 359 aclk_dsmc: aclk_dsmc@272008ac { 360 compatible = "rockchip,rk3576-clock-gate-link"; 361 reg = <0 0x272008ac 0 0x10>; 362 clock-names = "link"; 363 clocks = <&cru HCLK_NVM_ROOT>; 364 #power-domain-cells = <1>; 365 #clock-cells = <0>; 366 }; 367 368 pclk_sdgmac: pclk_sdgmac@272008a8 { 369 compatible = "rockchip,rk3576-clock-gate-link"; 370 reg = <0 0x272008a8 0 0x10>; 371 clock-names = "link"; 372 clocks = <&aclk_dsmc>; 373 #power-domain-cells = <1>; 374 #clock-cells = <0>; 375 }; 376 377 hclk_vepu0: hclk_vepu0@272008cc { 378 compatible = "rockchip,rk3576-clock-gate-link"; 379 reg = <0 0x272008cc 0 0x10>; 380 clock-names = "link"; 381 clocks = <&cru HCLK_VI_ROOT>; 382 #power-domain-cells = <1>; 383 #clock-cells = <0>; 384 }; 385 }; 386 387 cpus { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 391 cpu-map { 392 cluster0 { 393 core0 { 394 cpu = <&cpu_l0>; 395 }; 396 core1 { 397 cpu = <&cpu_l1>; 398 }; 399 core2 { 400 cpu = <&cpu_l2>; 401 }; 402 core3 { 403 cpu = <&cpu_l3>; 404 }; 405 }; 406 cluster1 { 407 core0 { 408 cpu = <&cpu_b0>; 409 }; 410 core1 { 411 cpu = <&cpu_b1>; 412 }; 413 core2 { 414 cpu = <&cpu_b2>; 415 }; 416 core3 { 417 cpu = <&cpu_b3>; 418 }; 419 }; 420 }; 421 422 cpu_l0: cpu@0 { 423 device_type = "cpu"; 424 compatible = "arm,cortex-a53"; 425 reg = <0x0>; 426 enable-method = "psci"; 427 capacity-dmips-mhz = <485>; 428 clocks = <&cru ARMCLK_L>; 429 operating-points-v2 = <&cluster0_opp_table>; 430 }; 431 432 cpu_l1: cpu@1 { 433 device_type = "cpu"; 434 compatible = "arm,cortex-a53"; 435 reg = <0x1>; 436 enable-method = "psci"; 437 capacity-dmips-mhz = <485>; 438 clocks = <&cru ARMCLK_L>; 439 operating-points-v2 = <&cluster0_opp_table>; 440 }; 441 442 cpu_l2: cpu@2 { 443 device_type = "cpu"; 444 compatible = "arm,cortex-a53"; 445 reg = <0x2>; 446 enable-method = "psci"; 447 capacity-dmips-mhz = <485>; 448 clocks = <&cru ARMCLK_L>; 449 operating-points-v2 = <&cluster0_opp_table>; 450 }; 451 452 cpu_l3: cpu@3 { 453 device_type = "cpu"; 454 compatible = "arm,cortex-a53"; 455 reg = <0x3>; 456 enable-method = "psci"; 457 capacity-dmips-mhz = <485>; 458 clocks = <&cru ARMCLK_L>; 459 operating-points-v2 = <&cluster0_opp_table>; 460 }; 461 462 cpu_b0: cpu@100 { 463 device_type = "cpu"; 464 compatible = "arm,cortex-a72"; 465 reg = <0x100>; 466 enable-method = "psci"; 467 capacity-dmips-mhz = <1024>; 468 clocks = <&cru ARMCLK_B>; 469 operating-points-v2 = <&cluster1_opp_table>; 470 }; 471 472 cpu_b1: cpu@101 { 473 device_type = "cpu"; 474 compatible = "arm,cortex-a72"; 475 reg = <0x101>; 476 enable-method = "psci"; 477 capacity-dmips-mhz = <1024>; 478 clocks = <&cru ARMCLK_B>; 479 operating-points-v2 = <&cluster1_opp_table>; 480 }; 481 482 cpu_b2: cpu@102 { 483 device_type = "cpu"; 484 compatible = "arm,cortex-a72"; 485 reg = <0x102>; 486 enable-method = "psci"; 487 capacity-dmips-mhz = <1024>; 488 clocks = <&cru ARMCLK_B>; 489 operating-points-v2 = <&cluster1_opp_table>; 490 }; 491 492 cpu_b3: cpu@103 { 493 device_type = "cpu"; 494 compatible = "arm,cortex-a72"; 495 reg = <0x103>; 496 enable-method = "psci"; 497 capacity-dmips-mhz = <1024>; 498 clocks = <&cru ARMCLK_B>; 499 operating-points-v2 = <&cluster1_opp_table>; 500 }; 501 }; 502 503 cluster0_opp_table: cluster0-opp-table { 504 compatible = "operating-points-v2"; 505 opp-shared; 506 507 opp-408000000 { 508 opp-hz = /bits/ 64 <408000000>; 509 opp-microvolt = <950000 950000 950000>; 510 clock-latency-ns = <40000>; 511 }; 512 opp-600000000 { 513 opp-hz = /bits/ 64 <600000000>; 514 opp-microvolt = <950000 950000 950000>; 515 clock-latency-ns = <40000>; 516 }; 517 opp-816000000 { 518 opp-hz = /bits/ 64 <816000000>; 519 opp-microvolt = <950000 950000 950000>; 520 clock-latency-ns = <40000>; 521 }; 522 opp-1008000000 { 523 opp-hz = /bits/ 64 <1008000000>; 524 opp-microvolt = <950000 950000 950000>; 525 clock-latency-ns = <40000>; 526 }; 527 opp-1200000000 { 528 opp-hz = /bits/ 64 <1200000000>; 529 opp-microvolt = <950000 950000 950000>; 530 clock-latency-ns = <40000>; 531 }; 532 opp-1416000000 { 533 opp-hz = /bits/ 64 <1416000000>; 534 opp-microvolt = <950000 950000 950000>; 535 clock-latency-ns = <40000>; 536 }; 537 }; 538 539 cluster1_opp_table: cluster1-opp-table { 540 compatible = "operating-points-v2"; 541 opp-shared; 542 543 opp-408000000 { 544 opp-hz = /bits/ 64 <408000000>; 545 opp-microvolt = <950000 950000 950000>; 546 clock-latency-ns = <40000>; 547 }; 548 opp-600000000 { 549 opp-hz = /bits/ 64 <600000000>; 550 opp-microvolt = <950000 950000 950000>; 551 clock-latency-ns = <40000>; 552 }; 553 opp-816000000 { 554 opp-hz = /bits/ 64 <816000000>; 555 opp-microvolt = <950000 950000 950000>; 556 clock-latency-ns = <40000>; 557 }; 558 opp-1008000000 { 559 opp-hz = /bits/ 64 <1008000000>; 560 opp-microvolt = <950000 950000 950000>; 561 clock-latency-ns = <40000>; 562 }; 563 opp-1200000000 { 564 opp-hz = /bits/ 64 <1200000000>; 565 opp-microvolt = <950000 950000 950000>; 566 clock-latency-ns = <40000>; 567 }; 568 opp-1416000000 { 569 opp-hz = /bits/ 64 <1416000000>; 570 opp-microvolt = <950000 950000 950000>; 571 clock-latency-ns = <40000>; 572 }; 573 opp-1608000000 { 574 opp-hz = /bits/ 64 <1608000000>; 575 opp-microvolt = <950000 950000 950000>; 576 clock-latency-ns = <40000>; 577 }; 578 }; 579 580 cpuinfo { 581 compatible = "rockchip,cpuinfo"; 582 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 583 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 584 }; 585 586 csi2_dcphy0: csi2-dcphy0 { 587 compatible = "rockchip,rk3576-csi2-dphy"; 588 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 589 phys = <&mipidcphy0>; 590 phy-names = "dcphy0"; 591 status = "disabled"; 592 }; 593 594 csi2_dphy0: csi2-dphy0 { 595 compatible = "rockchip,rk3576-csi2-dphy"; 596 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 597 phys = <&mipidcphy0>; 598 phy-names = "dcphy0"; 599 status = "disabled"; 600 }; 601 602 csi2_dphy1: csi2-dphy1 { 603 compatible = "rockchip,rk3576-csi2-dphy"; 604 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 605 phys = <&mipidcphy0>; 606 phy-names = "dcphy0"; 607 status = "disabled"; 608 }; 609 610 csi2_dphy2: csi2-dphy2 { 611 compatible = "rockchip,rk3576-csi2-dphy"; 612 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 613 phys = <&mipidcphy0>; 614 phy-names = "dcphy0"; 615 status = "disabled"; 616 }; 617 618 csi2_dphy3: csi2-dphy3 { 619 compatible = "rockchip,rk3576-csi2-dphy"; 620 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 621 phys = <&mipidcphy0>; 622 phy-names = "dcphy0"; 623 status = "disabled"; 624 }; 625 626 csi2_dphy4: csi2-dphy4 { 627 compatible = "rockchip,rk3576-csi2-dphy"; 628 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 629 phys = <&mipidcphy0>; 630 phy-names = "dcphy0"; 631 status = "disabled"; 632 }; 633 634 csi2_dphy5: csi2-dphy5 { 635 compatible = "rockchip,rk3576-csi2-dphy"; 636 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 637 phys = <&mipidcphy0>; 638 phy-names = "dcphy0"; 639 status = "disabled"; 640 }; 641 642 display_subsystem: display-subsystem { 643 compatible = "rockchip,display-subsystem"; 644 ports = <&vop_out>, <&vopl_out>; 645 646 route { 647 route_dsi: route-dsi { 648 status = "disabled"; 649 logo,uboot = "logo.bmp"; 650 logo,kernel = "logo_kernel.bmp"; 651 logo,mode = "center"; 652 charge_logo,mode = "center"; 653 connect = <&vp2_out_dsi>; 654 }; 655 656 route_edp: route-edp { 657 status = "disabled"; 658 logo,uboot = "logo.bmp"; 659 logo,kernel = "logo_kernel.bmp"; 660 logo,mode = "center"; 661 charge_logo,mode = "center"; 662 connect = <&vp1_out_edp>; 663 }; 664 665 route_hdmi: route-hdmi { 666 status = "disabled"; 667 logo,uboot = "logo.bmp"; 668 logo,kernel = "logo_kernel.bmp"; 669 logo,mode = "center"; 670 charge_logo,mode = "center"; 671 connect = <&vp0_out_hdmi>; 672 }; 673 674 route_dp0: route-dp0 { 675 status = "disabled"; 676 logo,uboot = "logo.bmp"; 677 logo,kernel = "logo_kernel.bmp"; 678 logo,mode = "center"; 679 charge_logo,mode = "center"; 680 connect = <&vp0_out_dp0>; 681 }; 682 683 route_rgb: route-rgb { 684 status = "disabled"; 685 logo,uboot = "logo.bmp"; 686 logo,kernel = "logo_kernel.bmp"; 687 logo,mode = "center"; 688 charge_logo,mode = "center"; 689 connect = <&vp2_out_rgb>; 690 }; 691 }; 692 }; 693 694 firmware: firmware { 695 scmi: scmi { 696 compatible = "arm,scmi-smc"; 697 arm,smc-id = <0x82000010>; 698 shmem = <&scmi_shmem>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 702 scmi_clk: protocol@14 { 703 reg = <0x14>; 704 #clock-cells = <1>; 705 }; 706 }; 707 }; 708 709 mipi0_csi2: mipi0-csi2 { 710 compatible = "rockchip,rk3576-mipi-csi2"; 711 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 712 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 713 <&mipi4_csi2_hw>; 714 status = "disabled"; 715 }; 716 717 mipi1_csi2: mipi1-csi2 { 718 compatible = "rockchip,rk3576-mipi-csi2"; 719 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 720 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 721 <&mipi4_csi2_hw>; 722 status = "disabled"; 723 }; 724 725 mipi2_csi2: mipi2-csi2 { 726 compatible = "rockchip,rk3576-mipi-csi2"; 727 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 728 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 729 <&mipi4_csi2_hw>; 730 status = "disabled"; 731 }; 732 733 mipi3_csi2: mipi3-csi2 { 734 compatible = "rockchip,rk3576-mipi-csi2"; 735 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 736 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 737 <&mipi4_csi2_hw>; 738 status = "disabled"; 739 }; 740 741 mipi4_csi2: mipi4-csi2 { 742 compatible = "rockchip,rk3576-mipi-csi2"; 743 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 744 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 745 <&mipi4_csi2_hw>; 746 status = "disabled"; 747 }; 748 749 mpp_srv: mpp-srv { 750 compatible = "rockchip,mpp-service"; 751 rockchip,taskqueue-count = <6>; 752 rockchip,resetgroup-count = <1>; 753 status = "disabled"; 754 }; 755 756 pmu_a53: pmu-a53 { 757 compatible = "arm,cortex-a53-pmu"; 758 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 762 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>; 763 }; 764 765 pmu_a72: pmu-a72 { 766 compatible = "arm,cortex-a72-pmu"; 767 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 771 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 772 }; 773 774 psci: psci { 775 compatible = "arm,psci-1.0"; 776 method = "smc"; 777 }; 778 779 rkcif_dvp: rkcif-dvp { 780 compatible = "rockchip,rkcif-dvp"; 781 rockchip,hw = <&rkcif>; 782 iommus = <&rkcif_mmu>; 783 status = "disabled"; 784 }; 785 786 rkcif_dvp_sditf: rkcif-dvp-sditf { 787 compatible = "rockchip,rkcif-sditf"; 788 rockchip,cif = <&rkcif_dvp>; 789 status = "disabled"; 790 }; 791 792 rkcif_mipi_lvds: rkcif-mipi-lvds { 793 compatible = "rockchip,rkcif-mipi-lvds"; 794 rockchip,hw = <&rkcif>; 795 iommus = <&rkcif_mmu>; 796 status = "disabled"; 797 }; 798 799 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { 800 compatible = "rockchip,rkcif-sditf"; 801 rockchip,cif = <&rkcif_mipi_lvds>; 802 status = "disabled"; 803 }; 804 805 rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 { 806 compatible = "rockchip,rkcif-sditf"; 807 rockchip,cif = <&rkcif_mipi_lvds>; 808 status = "disabled"; 809 }; 810 811 rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 { 812 compatible = "rockchip,rkcif-sditf"; 813 rockchip,cif = <&rkcif_mipi_lvds>; 814 status = "disabled"; 815 }; 816 817 rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 { 818 compatible = "rockchip,rkcif-sditf"; 819 rockchip,cif = <&rkcif_mipi_lvds>; 820 status = "disabled"; 821 }; 822 823 rkcif_mipi_lvds1: rkcif-mipi-lvds1 { 824 compatible = "rockchip,rkcif-mipi-lvds"; 825 rockchip,hw = <&rkcif>; 826 iommus = <&rkcif_mmu>; 827 status = "disabled"; 828 }; 829 830 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { 831 compatible = "rockchip,rkcif-sditf"; 832 rockchip,cif = <&rkcif_mipi_lvds1>; 833 status = "disabled"; 834 }; 835 836 rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 { 837 compatible = "rockchip,rkcif-sditf"; 838 rockchip,cif = <&rkcif_mipi_lvds1>; 839 status = "disabled"; 840 }; 841 842 rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 { 843 compatible = "rockchip,rkcif-sditf"; 844 rockchip,cif = <&rkcif_mipi_lvds1>; 845 status = "disabled"; 846 }; 847 848 rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 { 849 compatible = "rockchip,rkcif-sditf"; 850 rockchip,cif = <&rkcif_mipi_lvds1>; 851 status = "disabled"; 852 }; 853 854 rkcif_mipi_lvds2: rkcif-mipi-lvds2 { 855 compatible = "rockchip,rkcif-mipi-lvds"; 856 rockchip,hw = <&rkcif>; 857 iommus = <&rkcif_mmu>; 858 status = "disabled"; 859 }; 860 861 rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf { 862 compatible = "rockchip,rkcif-sditf"; 863 rockchip,cif = <&rkcif_mipi_lvds2>; 864 status = "disabled"; 865 }; 866 867 rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 { 868 compatible = "rockchip,rkcif-sditf"; 869 rockchip,cif = <&rkcif_mipi_lvds2>; 870 status = "disabled"; 871 }; 872 873 rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 { 874 compatible = "rockchip,rkcif-sditf"; 875 rockchip,cif = <&rkcif_mipi_lvds2>; 876 status = "disabled"; 877 }; 878 879 rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 { 880 compatible = "rockchip,rkcif-sditf"; 881 rockchip,cif = <&rkcif_mipi_lvds2>; 882 status = "disabled"; 883 }; 884 885 rkcif_mipi_lvds3: rkcif-mipi-lvds3 { 886 compatible = "rockchip,rkcif-mipi-lvds"; 887 rockchip,hw = <&rkcif>; 888 iommus = <&rkcif_mmu>; 889 status = "disabled"; 890 }; 891 892 rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf { 893 compatible = "rockchip,rkcif-sditf"; 894 rockchip,cif = <&rkcif_mipi_lvds3>; 895 status = "disabled"; 896 }; 897 898 rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 { 899 compatible = "rockchip,rkcif-sditf"; 900 rockchip,cif = <&rkcif_mipi_lvds3>; 901 status = "disabled"; 902 }; 903 904 rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 { 905 compatible = "rockchip,rkcif-sditf"; 906 rockchip,cif = <&rkcif_mipi_lvds3>; 907 status = "disabled"; 908 }; 909 910 rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 { 911 compatible = "rockchip,rkcif-sditf"; 912 rockchip,cif = <&rkcif_mipi_lvds3>; 913 status = "disabled"; 914 }; 915 916 rkcif_mipi_lvds4: rkcif-mipi-lvds4 { 917 compatible = "rockchip,rkcif-mipi-lvds"; 918 rockchip,hw = <&rkcif>; 919 iommus = <&rkcif_mmu>; 920 status = "disabled"; 921 }; 922 923 rkcif_mipi_lvds4_sditf: rkcif-mipi-lvds4-sditf { 924 compatible = "rockchip,rkcif-sditf"; 925 rockchip,cif = <&rkcif_mipi_lvds4>; 926 status = "disabled"; 927 }; 928 929 rkcif_mipi_lvds4_sditf_vir1: rkcif-mipi-lvds4-sditf-vir1 { 930 compatible = "rockchip,rkcif-sditf"; 931 rockchip,cif = <&rkcif_mipi_lvds4>; 932 status = "disabled"; 933 }; 934 935 rkcif_mipi_lvds4_sditf_vir2: rkcif-mipi-lvds4-sditf-vir2 { 936 compatible = "rockchip,rkcif-sditf"; 937 rockchip,cif = <&rkcif_mipi_lvds4>; 938 status = "disabled"; 939 }; 940 941 rkcif_mipi_lvds4_sditf_vir3: rkcif-mipi-lvds4-sditf-vir3 { 942 compatible = "rockchip,rkcif-sditf"; 943 rockchip,cif = <&rkcif_mipi_lvds4>; 944 status = "disabled"; 945 }; 946 947 rkisp_vir0: rkisp-vir0 { 948 compatible = "rockchip,rkisp-vir"; 949 rockchip,hw = <&rkisp>; 950 status = "disabled"; 951 }; 952 953 rkisp_vir1: rkisp-vir1 { 954 compatible = "rockchip,rkisp-vir"; 955 rockchip,hw = <&rkisp>; 956 status = "disabled"; 957 }; 958 959 rkisp_vir2: rkisp-vir2 { 960 compatible = "rockchip,rkisp-vir"; 961 rockchip,hw = <&rkisp>; 962 status = "disabled"; 963 }; 964 965 rkisp_vir3: rkisp-vir3 { 966 compatible = "rockchip,rkisp-vir"; 967 rockchip,hw = <&rkisp>; 968 status = "disabled"; 969 }; 970 971 rkisp_vir4: rkisp-vir4 { 972 compatible = "rockchip,rkisp-vir"; 973 rockchip,hw = <&rkisp>; 974 status = "disabled"; 975 }; 976 977 rkisp_vir5: rkisp-vir5 { 978 compatible = "rockchip,rkisp-vir"; 979 rockchip,hw = <&rkisp>; 980 status = "disabled"; 981 }; 982 983 rkisp_vir0_sditf: rkisp-vir0-sditf { 984 compatible = "rockchip,rkisp-sditf"; 985 rockchip,isp = <&rkisp_vir0>; 986 status = "disabled"; 987 988 port { 989 isp_sditf0: endpoint { 990 remote-endpoint = <&vpss0_in>; 991 }; 992 }; 993 }; 994 995 rkisp_vir1_sditf: rkisp-vir1-sditf { 996 compatible = "rockchip,rkisp-sditf"; 997 rockchip,isp = <&rkisp_vir1>; 998 status = "disabled"; 999 1000 port { 1001 isp_sditf1: endpoint { 1002 remote-endpoint = <&vpss1_in>; 1003 }; 1004 }; 1005 }; 1006 1007 rkisp_vir2_sditf: rkisp-vir2-sditf { 1008 compatible = "rockchip,rkisp-sditf"; 1009 rockchip,isp = <&rkisp_vir2>; 1010 status = "disabled"; 1011 1012 port { 1013 isp_sditf2: endpoint { 1014 remote-endpoint = <&vpss2_in>; 1015 }; 1016 }; 1017 }; 1018 1019 rkisp_vir3_sditf: rkisp-vir3-sditf { 1020 compatible = "rockchip,rkisp-sditf"; 1021 rockchip,isp = <&rkisp_vir3>; 1022 status = "disabled"; 1023 1024 port { 1025 isp_sditf3: endpoint { 1026 remote-endpoint = <&vpss3_in>; 1027 }; 1028 }; 1029 }; 1030 1031 rkisp_vir4_sditf: rkisp-vir4-sditf { 1032 compatible = "rockchip,rkisp-sditf"; 1033 rockchip,isp = <&rkisp_vir4>; 1034 status = "disabled"; 1035 1036 port { 1037 isp_sditf4: endpoint { 1038 remote-endpoint = <&vpss4_in>; 1039 }; 1040 }; 1041 }; 1042 1043 rkisp_vir5_sditf: rkisp-vir5-sditf { 1044 compatible = "rockchip,rkisp-sditf"; 1045 rockchip,isp = <&rkisp_vir5>; 1046 status = "disabled"; 1047 1048 port { 1049 isp_sditf5: endpoint { 1050 remote-endpoint = <&vpss5_in>; 1051 }; 1052 }; 1053 }; 1054 1055 rkvenc_ccu: rkvenc-ccu { 1056 compatible = "rockchip,rkv-encoder-rk3576-ccu", "rockchip,rkv-encoder-v2-ccu"; 1057 status = "disabled"; 1058 }; 1059 1060 rkvpss_vir0: rkvpss-vir0 { 1061 compatible = "rockchip,rkvpss-vir"; 1062 rockchip,hw = <&rkvpss>; 1063 status = "disabled"; 1064 1065 port { 1066 vpss0_in: endpoint { 1067 remote-endpoint = <&isp_sditf0>; 1068 }; 1069 }; 1070 }; 1071 1072 rkvpss_vir1: rkvpss-vir1 { 1073 compatible = "rockchip,rkvpss-vir"; 1074 rockchip,hw = <&rkvpss>; 1075 status = "disabled"; 1076 1077 port { 1078 vpss1_in: endpoint { 1079 remote-endpoint = <&isp_sditf1>; 1080 }; 1081 }; 1082 }; 1083 1084 rkvpss_vir2: rkvpss-vir2 { 1085 compatible = "rockchip,rkvpss-vir"; 1086 rockchip,hw = <&rkvpss>; 1087 status = "disabled"; 1088 1089 port { 1090 vpss2_in: endpoint { 1091 remote-endpoint = <&isp_sditf2>; 1092 }; 1093 }; 1094 }; 1095 1096 rkvpss_vir3: rkvpss-vir3 { 1097 compatible = "rockchip,rkvpss-vir"; 1098 rockchip,hw = <&rkvpss>; 1099 status = "disabled"; 1100 1101 port { 1102 vpss3_in: endpoint { 1103 remote-endpoint = <&isp_sditf3>; 1104 }; 1105 }; 1106 }; 1107 1108 rkvpss_vir4: rkvpss-vir4 { 1109 compatible = "rockchip,rkvpss-vir"; 1110 rockchip,hw = <&rkvpss>; 1111 status = "disabled"; 1112 1113 port { 1114 vpss4_in: endpoint { 1115 remote-endpoint = <&isp_sditf4>; 1116 }; 1117 }; 1118 }; 1119 1120 rkvpss_vir5: rkvpss-vir5 { 1121 compatible = "rockchip,rkvpss-vir"; 1122 rockchip,hw = <&rkvpss>; 1123 status = "disabled"; 1124 1125 port { 1126 vpss5_in: endpoint { 1127 remote-endpoint = <&isp_sditf5>; 1128 }; 1129 }; 1130 }; 1131 1132 thermal_zones: thermal-zones { 1133 soc_thermal: soc-thermal { 1134 polling-delay-passive = <20>; /* milliseconds */ 1135 polling-delay = <1000>; /* milliseconds */ 1136 thermal-sensors = <&tsadc 0>; 1137 trips { 1138 soc_crit: soc-crit { 1139 /* millicelsius */ 1140 temperature = <115000>; 1141 /* millicelsius */ 1142 hysteresis = <2000>; 1143 type = "critical"; 1144 }; 1145 }; 1146 }; 1147 bigcore_thermal: bigcore-thermal { 1148 polling-delay-passive = <20>; /* milliseconds */ 1149 polling-delay = <1000>; /* milliseconds */ 1150 thermal-sensors = <&tsadc 1>; 1151 trips { 1152 bigcore_crit: bigcore-crit { 1153 /* millicelsius */ 1154 temperature = <115000>; 1155 /* millicelsius */ 1156 hysteresis = <2000>; 1157 type = "critical"; 1158 }; 1159 }; 1160 }; 1161 little_core_thermal: little-core-thermal { 1162 polling-delay-passive = <20>; /* milliseconds */ 1163 polling-delay = <1000>; /* milliseconds */ 1164 thermal-sensors = <&tsadc 2>; 1165 trips { 1166 little_core_crit: little-core-crit { 1167 /* millicelsius */ 1168 temperature = <115000>; 1169 /* millicelsius */ 1170 hysteresis = <2000>; 1171 type = "critical"; 1172 }; 1173 }; 1174 }; 1175 ddr_thermal: ddr-thermal { 1176 polling-delay-passive = <20>; /* milliseconds */ 1177 polling-delay = <1000>; /* milliseconds */ 1178 thermal-sensors = <&tsadc 3>; 1179 trips { 1180 ddr_crit: ddr-crit { 1181 /* millicelsius */ 1182 temperature = <115000>; 1183 /* millicelsius */ 1184 hysteresis = <2000>; 1185 type = "critical"; 1186 }; 1187 }; 1188 }; 1189 npu_thermal: npu-thermal { 1190 polling-delay-passive = <20>; /* milliseconds */ 1191 polling-delay = <1000>; /* milliseconds */ 1192 thermal-sensors = <&tsadc 4>; 1193 trips { 1194 npu_crit: npu-crit { 1195 /* millicelsius */ 1196 temperature = <115000>; 1197 /* millicelsius */ 1198 hysteresis = <2000>; 1199 type = "critical"; 1200 }; 1201 }; 1202 }; 1203 gpu_thermal: gpu-thermal { 1204 polling-delay-passive = <20>; /* milliseconds */ 1205 polling-delay = <1000>; /* milliseconds */ 1206 thermal-sensors = <&tsadc 5>; 1207 trips { 1208 gpu_crit: gpu-crit { 1209 /* millicelsius */ 1210 temperature = <115000>; 1211 /* millicelsius */ 1212 hysteresis = <2000>; 1213 type = "critical"; 1214 }; 1215 }; 1216 }; 1217 }; 1218 1219 timer { 1220 compatible = "arm,armv8-timer"; 1221 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1222 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1223 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1224 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 1225 }; 1226 1227 usb_drd0_dwc3: usb@23000000 { 1228 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 1229 reg = <0x0 0x23000000 0x0 0x400000>; 1230 clocks = <&cru CLK_REF_USB3OTG0>, 1231 <&cru CLK_SUSPEND_USB3OTG0>, 1232 <&cru ACLK_USB3OTG0>; 1233 clock-names = "ref", "suspend", "bus_clk"; 1234 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1235 power-domains = <&power RK3576_PD_USB>; 1236 resets = <&cru SRST_A_USB3OTG0>; 1237 reset-names = "usb3-otg"; 1238 dr_mode = "otg"; 1239 phys = <&u2phy0_otg>, <&usbdp_phy_u3>; 1240 phy-names = "usb2-phy", "usb3-phy"; 1241 phy_type = "utmi_wide"; 1242 snps,dis_enblslpm_quirk; 1243 snps,dis-u1-entry-quirk; 1244 snps,dis-u2-entry-quirk; 1245 snps,dis-u2-freeclk-exists-quirk; 1246 snps,dis-del-phy-power-chg-quirk; 1247 snps,dis-tx-ipgap-linecheck-quirk; 1248 snps,parkmode-disable-hs-quirk; 1249 snps,parkmode-disable-ss-quirk; 1250 status = "disabled"; 1251 }; 1252 1253 usb_drd1_dwc3: usb@23400000 { 1254 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 1255 reg = <0x0 0x23400000 0x0 0x400000>; 1256 clocks = <&cru CLK_REF_USB3OTG1>, 1257 <&cru CLK_SUSPEND_USB3OTG1>, 1258 <&cru ACLK_USB3OTG1>; 1259 clock-names = "ref", "suspend", "bus_clk"; 1260 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 1261 power-domains = <&power RK3576_PD_PHP>; 1262 resets = <&cru SRST_A_USB3OTG1>; 1263 reset-names = "usb3-otg"; 1264 dr_mode = "otg"; 1265 phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>; 1266 phy-names = "usb2-phy", "usb3-phy"; 1267 phy_type = "utmi_wide"; 1268 snps,dis_enblslpm_quirk; 1269 snps,dis-u1-entry-quirk; 1270 snps,dis-u2-entry-quirk; 1271 snps,dis-u2-freeclk-exists-quirk; 1272 snps,dis-del-phy-power-chg-quirk; 1273 snps,dis-tx-ipgap-linecheck-quirk; 1274 snps,dis_rxdet_inp3_quirk; 1275 snps,parkmode-disable-hs-quirk; 1276 snps,parkmode-disable-ss-quirk; 1277 status = "disabled"; 1278 }; 1279 1280 sys_grf: syscon@2600a000 { 1281 compatible = "rockchip,rk3576-sys-grf", "syscon", "simple-mfd"; 1282 reg = <0x0 0x2600a000 0x0 0x10000>; 1283 }; 1284 1285 vo0_grf: syscon@2601a000 { 1286 compatible = "rockchip,rk3576-vo0-grf", "syscon"; 1287 reg = <0x0 0x2601a000 0x0 0x2000>; 1288 clocks = <&cru PCLK_VO0_ROOT>; 1289 }; 1290 1291 usb_grf: syscon@2601e000 { 1292 compatible = "rockchip,rk3576-usb-grf", "syscon"; 1293 reg = <0x0 0x2601e000 0x0 0x1000>; 1294 clocks = <&cru PCLK_USB_ROOT>; 1295 }; 1296 1297 php_grf: syscon@26020000 { 1298 compatible = "rockchip,rk3576-php-grf", "syscon"; 1299 reg = <0x0 0x26020000 0x0 0x2000>; 1300 clocks = <&cru PCLK_PHP_ROOT>; 1301 }; 1302 1303 pmu0_grf: syscon@26024000 { 1304 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd"; 1305 reg = <0x0 0x26024000 0x0 0x1000>; 1306 1307 reboot_mode: reboot-mode { 1308 compatible = "syscon-reboot-mode"; 1309 offset = <0x40>; 1310 mode-bootloader = <BOOT_BL_DOWNLOAD>; 1311 mode-charge = <BOOT_CHARGING>; 1312 mode-fastboot = <BOOT_FASTBOOT>; 1313 mode-loader = <BOOT_BL_DOWNLOAD>; 1314 mode-normal = <BOOT_NORMAL>; 1315 mode-recovery = <BOOT_RECOVERY>; 1316 mode-ums = <BOOT_UMS>; 1317 mode-panic = <BOOT_PANIC>; 1318 mode-watchdog = <BOOT_WATCHDOG>; 1319 mode-quiescent = <BOOT_QUIESCENT>; 1320 /* add a mode to capture the ramdump through usb */ 1321 mode-winusb = <BOOT_WINUSB>; 1322 }; 1323 }; 1324 1325 pipe_phy0_grf: syscon@26028000 { 1326 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 1327 reg = <0x0 0x26028000 0x0 0x2000>; 1328 clocks = <&cru PCLK_PCIE2_COMBOPHY0>; 1329 }; 1330 1331 pipe_phy1_grf: syscon@2602a000 { 1332 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 1333 reg = <0x0 0x2602a000 0x0 0x2000>; 1334 clocks = <&cru PCLK_PCIE2_COMBOPHY1>; 1335 }; 1336 1337 usbdpphy_grf: syscon@2602c000 { 1338 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon"; 1339 reg = <0x0 0x2602c000 0x0 0x2000>; 1340 clocks = <&cru PCLK_PMUPHY_ROOT>; 1341 }; 1342 1343 usb2phy_grf: syscon@2602e000 { 1344 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd"; 1345 reg = <0x0 0x2602e000 0x0 0x4000>; 1346 #address-cells = <1>; 1347 #size-cells = <1>; 1348 clocks = <&cru PCLK_PMUPHY_ROOT>; 1349 1350 u2phy0: usb2-phy@0 { 1351 compatible = "rockchip,rk3576-usb2phy"; 1352 reg = <0x0 0x10>; 1353 resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>; 1354 reset-names = "phy", "apb"; 1355 clocks = <&cru CLK_PHY_REF_SRC>; 1356 clock-names = "phyclk"; 1357 clock-output-names = "usb480m_phy0"; 1358 #clock-cells = <0>; 1359 rockchip,usbctrl-grf = <&usb_grf>; 1360 status = "disabled"; 1361 1362 u2phy0_otg: otg-port { 1363 #phy-cells = <0>; 1364 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1367 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 1368 status = "disabled"; 1369 }; 1370 }; 1371 1372 u2phy1: usb2-phy@2000 { 1373 compatible = "rockchip,rk3576-usb2phy"; 1374 reg = <0x2000 0x10>; 1375 resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>; 1376 reset-names = "phy", "apb"; 1377 clocks = <&cru CLK_PHY_REF_SRC>; 1378 clock-names = "phyclk"; 1379 clock-output-names = "usb480m_phy1"; 1380 #clock-cells = <0>; 1381 rockchip,usbctrl-grf = <&php_grf>; 1382 status = "disabled"; 1383 1384 u2phy1_otg: otg-port { 1385 #phy-cells = <0>; 1386 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1389 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 1390 status = "disabled"; 1391 }; 1392 }; 1393 }; 1394 1395 hdptxphy_grf: syscon@26032000 { 1396 compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; 1397 reg = <0x0 0x26032000 0x0 0x100>; 1398 clocks = <&cru PCLK_PMUPHY_ROOT>; 1399 }; 1400 1401 mipidcphy0_grf: syscon@26034000 { 1402 compatible = "rockchip,rk3576-mipi-dcphy-grf", "syscon"; 1403 reg = <0x0 0x26034000 0x0 0x2000>; 1404 clocks = <&cru PCLK_PMUPHY_ROOT>; 1405 }; 1406 1407 vo1_grf: syscon@26036000 { 1408 compatible = "rockchip,rk3576-vo-grf", "syscon"; 1409 reg = <0x0 0x26036000 0x0 0x100>; 1410 clocks = <&cru PCLK_VO1_ROOT>; 1411 }; 1412 1413 sdgmac_grf: syscon@26038000 { 1414 compatible = "rockchip,rk3576-sdgmac-grf", "syscon"; 1415 reg = <0x0 0x26038000 0x0 0x1000>; 1416 clocks = <&cru PCLK_SDGMAC_ROOT>; 1417 }; 1418 1419 mipidphy0_grf: syscon@2603a000 { 1420 compatible = "rockchip,rk3576-mipi-dphy-grf", "syscon"; 1421 reg = <0x0 0x2603a000 0x0 0x2000>; 1422 clocks = <&cru PCLK_PMUPHY_ROOT>; 1423 }; 1424 1425 ioc_grf: syscon@26040000 { 1426 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd"; 1427 reg = <0x0 0x26040000 0x0 0xc000>; 1428 1429 rgb: rgb { 1430 compatible = "rockchip,rk3576-rgb"; 1431 pinctrl-names = "default"; 1432 status = "disabled"; 1433 1434 ports { 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 1438 port@0 { 1439 reg = <0>; 1440 #address-cells = <1>; 1441 #size-cells = <0>; 1442 1443 rgb_in_vopl: endpoint@0 { 1444 reg = <0>; 1445 remote-endpoint = <&vopl_out_rgb>; 1446 status = "disabled"; 1447 }; 1448 1449 rgb_in_vp1: endpoint@1 { 1450 reg = <1>; 1451 remote-endpoint = <&vp1_out_rgb>; 1452 status = "disabled"; 1453 }; 1454 1455 rgb_in_vp2: endpoint@2 { 1456 reg = <2>; 1457 remote-endpoint = <&vp2_out_rgb>; 1458 status = "disabled"; 1459 }; 1460 }; 1461 }; 1462 }; 1463 }; 1464 1465 mipidphy1_grf: syscon@2604c000 { 1466 compatible = "rockchip,rk3576-mipi-dphy-grf", "syscon"; 1467 reg = <0x0 0x2604c000 0x0 0x2000>; 1468 }; 1469 1470 cru: clock-controller@27200000 { 1471 compatible = "rockchip,rk3576-cru"; 1472 reg = <0x0 0x27200000 0x0 0x50000>; 1473 rockchip,grf = <&pmu0_grf>; 1474 #clock-cells = <1>; 1475 #reset-cells = <1>; 1476 1477 assigned-clocks = 1478 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1479 <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>, 1480 <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>; 1481 assigned-clock-rates = 1482 <1188000000>, <1000000000>, 1483 <786432000>, <18432000>, 1484 <48000000>, <64000000>; 1485 }; 1486 1487 i2c0: i2c@27300000 { 1488 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1489 reg = <0x0 0x27300000 0x0 0x1000>; 1490 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 1491 clock-names = "i2c", "pclk"; 1492 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1493 pinctrl-names = "default"; 1494 pinctrl-0 = <&i2c0m0_xfer>; 1495 resets = <&cru SRST_I2C0>, <&cru SRST_P_I2C0>; 1496 reset-names = "i2c", "apb"; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 status = "disabled"; 1500 }; 1501 1502 uart1: serial@27310000 { 1503 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1504 reg = <0x0 0x27310000 0x0 0x100>; 1505 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1506 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1507 clock-names = "baudclk", "apb_pclk"; 1508 reg-shift = <2>; 1509 reg-io-width = <4>; 1510 dmas = <&dmac0 8>, <&dmac0 9>; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&uart1m0_xfer>; 1513 status = "disabled"; 1514 }; 1515 1516 pwm0_2ch_0: pwm@27330000 { 1517 compatible = "rockchip,rk3576-pwm"; 1518 reg = <0x0 0x27330000 0x0 0x1000>; 1519 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1520 #pwm-cells = <3>; 1521 pinctrl-names = "active"; 1522 pinctrl-0 = <&pwm0m0_ch0>; 1523 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 1524 clock-names = "pwm", "pclk"; 1525 status = "disabled"; 1526 }; 1527 1528 pwm0_2ch_1: pwm@27331000 { 1529 compatible = "rockchip,rk3576-pwm"; 1530 reg = <0x0 0x27331000 0x0 0x1000>; 1531 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1532 #pwm-cells = <3>; 1533 pinctrl-names = "active"; 1534 pinctrl-0 = <&pwm0m0_ch1>; 1535 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 1536 clock-names = "pwm", "pclk"; 1537 status = "disabled"; 1538 }; 1539 1540 pmu: power-management@27380000 { 1541 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd"; 1542 reg = <0x0 0x27380000 0x0 0x800>; 1543 1544 power: power-controller { 1545 compatible = "rockchip,rk3576-power-controller"; 1546 #power-domain-cells = <1>; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 status = "okay"; 1550 1551 /* These power domains are grouped by VD_NPU */ 1552 power-domain@RK3576_PD_NPU { 1553 reg = <RK3576_PD_NPU>; 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 1557 power-domain@RK3576_PD_NPUTOP { 1558 reg = <RK3576_PD_NPUTOP>; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 1562 power-domain@RK3576_PD_NPU0 { 1563 reg = <RK3576_PD_NPU0>; 1564 }; 1565 power-domain@RK3576_PD_NPU1 { 1566 reg = <RK3576_PD_NPU1>; 1567 }; 1568 }; 1569 }; 1570 /* These power domains are grouped by VD_GPU */ 1571 power-domain@RK3576_PD_GPU { 1572 reg = <RK3576_PD_GPU>; 1573 }; 1574 /* These power domains are grouped by VD_LOGIC */ 1575 power-domain@RK3576_PD_NVM { 1576 reg = <RK3576_PD_NVM>; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 1580 power-domain@RK3576_PD_SDGMAC { 1581 reg = <RK3576_PD_SDGMAC>; 1582 }; 1583 }; 1584 power-domain@RK3576_PD_PHP { 1585 reg = <RK3576_PD_PHP>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 1589 power-domain@RK3576_PD_SUBPHP { 1590 reg = <RK3576_PD_SUBPHP>; 1591 }; 1592 }; 1593 power-domain@RK3576_PD_AUDIO { 1594 reg = <RK3576_PD_AUDIO>; 1595 }; 1596 power-domain@RK3576_PD_VEPU1 { 1597 reg = <RK3576_PD_VEPU1>; 1598 }; 1599 power-domain@RK3576_PD_VPU { 1600 reg = <RK3576_PD_VPU>; 1601 }; 1602 power-domain@RK3576_PD_VDEC { 1603 reg = <RK3576_PD_VDEC>; 1604 }; 1605 power-domain@RK3576_PD_VI { 1606 reg = <RK3576_PD_VI>; 1607 #address-cells = <1>; 1608 #size-cells = <0>; 1609 1610 power-domain@RK3576_PD_VEPU0 { 1611 reg = <RK3576_PD_VEPU0>; 1612 }; 1613 }; 1614 power-domain@RK3576_PD_VOP { 1615 reg = <RK3576_PD_VOP>; 1616 #address-cells = <1>; 1617 #size-cells = <0>; 1618 1619 power-domain@RK3576_PD_USB { 1620 reg = <RK3576_PD_USB>; 1621 }; 1622 power-domain@RK3576_PD_VO0 { 1623 reg = <RK3576_PD_VO0>; 1624 }; 1625 power-domain@RK3576_PD_VO1 { 1626 reg = <RK3576_PD_VO1>; 1627 }; 1628 }; 1629 }; 1630 }; 1631 1632 pdm0: pdm@273b0000 { 1633 compatible = "rockchip,rk3576-pdm"; 1634 reg = <0x0 0x273b0000 0x0 0x1000>; 1635 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1636 clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>, <&cru CLK_PDM0_OUT>; 1637 clock-names = "pdm_clk", "pdm_hclk", "pdm_clk_out"; 1638 dmas = <&dmac0 4>; 1639 dma-names = "rx"; 1640 pinctrl-names = "default"; 1641 pinctrl-0 = <&pdm0m0_clk0 1642 &pdm0m0_clk1 1643 &pdm0m0_sdi0 1644 &pdm0m0_sdi1 1645 &pdm0m0_sdi2 1646 &pdm0m0_sdi3>; 1647 #sound-dai-cells = <0>; 1648 sound-name-prefix = "PDM0"; 1649 status = "disabled"; 1650 }; 1651 1652 rknpu: npu@27700000 { 1653 compatible = "rockchip,rk3576-rknpu"; 1654 reg = <0x0 0x27700000 0x0 0x8000>, 1655 <0x0 0x27708000 0x0 0x8000>; 1656 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 1658 interrupt-names = "npu0_irq", "npu1_irq"; 1659 clocks = <&cru ACLK_RKNN0>, <&cru ACLK_RKNN1>, <&cru HCLK_RKNN_ROOT>, 1660 <&cru ACLK_RKNN_CBUF>, <&cru HCLK_RKNN_CBUF>; 1661 clock-names = "aclk0", "aclk1", "hclk_root", 1662 "aclk_cbuf", "hclk_cbuf"; 1663 resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, 1664 <&cru SRST_A_RKNN_CBUF>, <&cru SRST_A_RKNN_CBUF>; 1665 reset-names = "srst_a0", "srst_a1", 1666 "srst_a_cbuf", "srst_h_cbuf"; 1667 power-domains = <&power RK3576_PD_NPU0>, <&power RK3576_PD_NPU1>; 1668 power-domain-names = "npu0", "npu1"; 1669 iommus = <&rknpu_mmu>; 1670 status = "disabled"; 1671 }; 1672 1673 rknpu_mmu: iommu@27702000 { 1674 compatible = "rockchip,iommu-v2"; 1675 reg = <0x0 0x27702000 0x0 0x100>, 1676 <0x0 0x27702100 0x0 0x100>, 1677 <0x0 0x2770a000 0x0 0x100>, 1678 <0x0 0x2770a100 0x0 0x100>; 1679 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 1681 interrupt-names = "npu0_mmu", "npu1_mmu"; 1682 clocks = <&cru ACLK_RKNN0>, <&cru ACLK_RKNN1>, <&cru HCLK_RKNN_ROOT>; 1683 clock-names = "aclk0", "aclk1", "iface"; 1684 #iommu-cells = <0>; 1685 status = "disabled"; 1686 }; 1687 1688 gpu: gpu@27800000 { 1689 compatible = "arm,mali-bifrost"; 1690 reg = <0x0 0x27800000 0x0 0x20000>; 1691 1692 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 1695 interrupt-names = "GPU", "MMU", "JOB"; 1696 1697 upthreshold = <40>; 1698 downdifferential = <10>; 1699 1700 clocks = <&cru CLK_GPU>; 1701 clock-names = "clk_mali"; 1702 power-domains = <&power RK3576_PD_GPU>; 1703 operating-points-v2 = <&gpu_opp_table>; 1704 #cooling-cells = <2>; 1705 1706 status = "disabled"; 1707 }; 1708 1709 gpu_opp_table: gpu-opp-table { 1710 compatible = "operating-points-v2"; 1711 1712 opp-300000000 { 1713 opp-hz = /bits/ 64 <300000000>; 1714 opp-microvolt = <850000 850000 850000>; 1715 }; 1716 opp-400000000 { 1717 opp-hz = /bits/ 64 <400000000>; 1718 opp-microvolt = <850000 850000 850000>; 1719 }; 1720 opp-500000000 { 1721 opp-hz = /bits/ 64 <500000000>; 1722 opp-microvolt = <850000 850000 850000>; 1723 }; 1724 opp-600000000 { 1725 opp-hz = /bits/ 64 <600000000>; 1726 opp-microvolt = <850000 850000 850000>; 1727 }; 1728 }; 1729 1730 ebc: ebc@27900000 { 1731 compatible = "rockchip,rk3576-ebc-tcon"; 1732 reg = <0x0 0x27900000 0x0 0x5000>; 1733 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 1734 clocks = <&cru HCLK_EBC>, <&cru ACLK_EBC>, <&cru DCLK_EBC>; 1735 clock-names = "hclk", "aclk", "dclk"; 1736 pinctrl-names = "default"; 1737 pinctrl-0 = <&vo_ebc_pins>; 1738 power-domains = <&power RK3576_PD_VPU>; 1739 rockchip,grf = <&sys_grf>; 1740 status = "disabled"; 1741 }; 1742 1743 vopl: vop@27900000 { 1744 compatible = "rockchip,rk3576-vop-lit"; 1745 reg = <0x0 0x27900000 0x0 0x200>; 1746 reg-names = "regs"; 1747 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 1748 clocks = <&cru ACLK_EBC>, <&cru DCLK_EBC>, <&cru HCLK_EBC>; 1749 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1750 power-domains = <&power RK3576_PD_VPU>; 1751 rockchip,grf = <&ioc_grf>; 1752 rockchip,vo0_grf = <&vo0_grf>; 1753 status = "disabled"; 1754 1755 vopl_out: port { 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 1759 vopl_out_rgb: endpoint@0 { 1760 reg = <0>; 1761 remote-endpoint = <&rgb_in_vopl>; 1762 }; 1763 1764 vopl_out_dsi: endpoint@1 { 1765 reg = <1>; 1766 remote-endpoint = <&dsi_in_vopl>; 1767 }; 1768 1769 vopl_out_edp: endpoint@2 { 1770 reg = <2>; 1771 remote-endpoint = <&edp_in_vopl>; 1772 }; 1773 1774 vopl_out_hdmi: endpoint@3 { 1775 reg = <3>; 1776 remote-endpoint = <&hdmi_in_vopl>; 1777 }; 1778 }; 1779 }; 1780 1781 jpegd: jpegd@27910000 { 1782 compatible = "rockchip,rkv-jpeg-decoder-v1"; 1783 reg = <0x0 0x27910000 0x0 0x330>; 1784 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1785 interrupt-names = "irq_jpegd"; 1786 clocks = <&aclk_jpeg>, <&cru HCLK_JPEG>; 1787 clock-names = "aclk_vcodec", "hclk_vcodec"; 1788 rockchip,normal-rates = <700000000>, <0>; 1789 assigned-clocks = <&aclk_jpeg>; 1790 assigned-clock-rates = <700000000>; 1791 resets = <&cru SRST_A_JPEG>, <&cru SRST_H_JPEG>; 1792 reset-names = "shared_video_a", "shared_video_h"; 1793 rockchip,skip-pmu-idle-request; 1794 iommus = <&jpeg_mmu>; 1795 rockchip,srv = <&mpp_srv>; 1796 rockchip,taskqueue-node = <0>; 1797 rockchip,resetgroup-node = <0>; 1798 power-domains = <&power RK3576_PD_VPU>; 1799 status = "disabled"; 1800 }; 1801 1802 jpege: jpege@27910800 { 1803 compatible = "rockchip,rkv-jpeg-encoder-v1"; 1804 reg = <0x0 0x27910800 0x0 0x13c>; 1805 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1806 interrupt-names = "irq_jpege"; 1807 clocks = <&aclk_jpeg>, <&cru HCLK_JPEG>; 1808 clock-names = "aclk_vcodec", "hclk_vcodec"; 1809 rockchip,normal-rates = <700000000>, <0>; 1810 assigned-clocks = <&aclk_jpeg>; 1811 assigned-clock-rates = <700000000>; 1812 resets = <&cru SRST_A_JPEG>, <&cru SRST_H_JPEG>; 1813 reset-names = "shared_video_a", "shared_video_h"; 1814 rockchip,skip-pmu-idle-request; 1815 iommus = <&jpeg_mmu>; 1816 rockchip,srv = <&mpp_srv>; 1817 rockchip,taskqueue-node = <0>; 1818 rockchip,resetgroup-node = <0>; 1819 power-domains = <&power RK3576_PD_VPU>; 1820 status = "disabled"; 1821 }; 1822 1823 jpeg_mmu: iommu@27910f00 { 1824 compatible = "rockchip,iommu-v2"; 1825 reg = <0x0 0x27910f00 0x0 0x28>; 1826 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1827 interrupt-names = "irq_jpeg_mmu"; 1828 clocks = <&aclk_jpeg>, <&cru HCLK_JPEG>; 1829 clock-name = "aclk", "iface"; 1830 #iommu-cells = <0>; 1831 rockchip,shootdown-entire; 1832 power-domains = <&power RK3576_PD_VPU>; 1833 status = "disabled"; 1834 }; 1835 1836 rga2_core0: rga@27920000 { 1837 compatible = "rockchip,rga2_core0"; 1838 reg = <0x0 0x27920000 0x0 0x1000>; 1839 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1840 interrupt-names = "rga2_core0_irq"; 1841 clocks = <&cru ACLK_RGA2E_0>, <&cru HCLK_RGA2E_0>, <&cru CLK_CORE_RGA2E_0>; 1842 clock-names = "aclk_rga2e_0", "hclk_rga2e_0", "clk_rga2e_0"; 1843 power-domains = <&power RK3576_PD_VPU>; 1844 iommus = <&rga2_core0_mmu>; 1845 status = "disabled"; 1846 }; 1847 1848 rga2_core0_mmu: iommu@27920f00 { 1849 compatible = "rockchip,iommu-v2"; 1850 reg = <0x0 0x27920f00 0x0 0x100>; 1851 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1852 interrupt-names = "rga2_0_mmu"; 1853 clocks = <&cru ACLK_RGA2E_0>, <&cru HCLK_RGA2E_0>; 1854 clock-names = "aclk", "iface"; 1855 power-domains = <&power RK3576_PD_VPU>; 1856 #iommu-cells = <0>; 1857 status = "disabled"; 1858 }; 1859 1860 rga2_core1: rga@27930000 { 1861 compatible = "rockchip,rga2_core1"; 1862 reg = <0x0 0x27930000 0x0 0x1000>; 1863 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1864 interrupt-names = "rga2_core1_irq"; 1865 clocks = <&cru ACLK_RGA2E_1>, <&cru HCLK_RGA2E_1>, <&cru CLK_CORE_RGA2E_1>; 1866 clock-names = "aclk_rga2e_1", "hclk_rga2e_1", "clk_rga2e_1"; 1867 power-domains = <&power RK3576_PD_VPU>; 1868 iommus = <&rga2_core1_mmu>; 1869 status = "disabled"; 1870 }; 1871 1872 rga2_core1_mmu: iommu@27930f00 { 1873 compatible = "rockchip,iommu-v2"; 1874 reg = <0x0 0x27930f00 0x0 0x100>; 1875 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1876 interrupt-names = "rga2_1_mmu"; 1877 clocks = <&cru ACLK_RGA2E_1>, <&cru HCLK_RGA2E_1>; 1878 clock-names = "aclk", "iface"; 1879 power-domains = <&power RK3576_PD_VPU>; 1880 #iommu-cells = <0>; 1881 status = "disabled"; 1882 }; 1883 1884 iep: iep@27960000 { 1885 compatible = "rockchip,iep-v2"; 1886 reg = <0x0 0x27960000 0x0 0x500>; 1887 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 1888 interrupt-names = "irq_vdpp"; 1889 clocks = <&aclk_vdpp>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>; 1890 clock-names = "aclk", "hclk", "sclk"; 1891 rockchip,normal-rates = <340000000>, <0>, <340000000>; 1892 assigned-clocks = <&aclk_vdpp>, <&cru CLK_CORE_VDPP>; 1893 assigned-clock-rates = <340000000>, <340000000>; 1894 resets = <&cru SRST_A_VDPP>, <&cru SRST_H_VDPP>, <&cru SRST_CORE_VDPP>; 1895 reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s"; 1896 rockchip,skip-pmu-idle-request; 1897 rockchip,srv = <&mpp_srv>; 1898 rockchip,taskqueue-node = <2>; 1899 iommus = <&iep_mmu>; 1900 power-domains = <&power RK3576_PD_VPU>; 1901 status = "disabled"; 1902 }; 1903 1904 iep_mmu: iommu@27960800 { 1905 compatible = "rockchip,iommu-v2"; 1906 reg = <0x0 0x27960800 0x0 0x100>; 1907 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 1908 interrupt-names = "iep_mmu"; 1909 clocks = <&aclk_vdpp>, <&cru HCLK_VDPP>; 1910 clock-names = "aclk", "iface"; 1911 #iommu-cells = <0>; 1912 rockchip,shootdown-entire; 1913 power-domains = <&power RK3576_PD_VPU>; 1914 status = "disabled"; 1915 }; 1916 1917 vdpp: vdpp@27961000 { 1918 compatible = "rockchip,vdpp-rk3576"; 1919 reg = <0x0 0x27961000 0x0 0x500>, <0x0 0x27962000 0x0 0x900>; 1920 reg-names = "vdpp_regs", "zme_regs"; 1921 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 1922 interrupt-names = "irq_vdpp"; 1923 clocks = <&aclk_vdpp>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>; 1924 clock-names = "aclk", "hclk", "sclk"; 1925 rockchip,normal-rates = <340000000>, <0>, <340000000>; 1926 assigned-clocks = <&aclk_vdpp>, <&cru CLK_CORE_VDPP>; 1927 assigned-clock-rates = <340000000>, <340000000>; 1928 resets = <&cru SRST_A_VDPP>, <&cru SRST_H_VDPP>, <&cru SRST_CORE_VDPP>; 1929 reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s"; 1930 rockchip,skip-pmu-idle-request; 1931 rockchip,srv = <&mpp_srv>; 1932 rockchip,taskqueue-node = <2>; 1933 rockchip,disable-auto-freq; 1934 iommus = <&iep_mmu>; 1935 power-domains = <&power RK3576_PD_VPU>; 1936 status = "disabled"; 1937 }; 1938 1939 rkvenc0: rkvenc-core@27a00000 { 1940 compatible = "rockchip,rkv-encoder-rk3576-core"; 1941 reg = <0x0 0x27a00000 0x0 0x6000>; 1942 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1943 interrupt-names = "irq_vepu0"; 1944 clocks = <&aclk_vepu0>, <&hclk_vepu0>, <&cru CLK_VEPU0_CORE>; 1945 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1946 rockchip,normal-rates = <400000000>, <0>, <700000000>; 1947 resets = <&cru SRST_A_VEPU0>, <&cru SRST_H_VEPU0>, 1948 <&cru SRST_VEPU0_CORE>; 1949 reset-names = "video_a", "video_h", "video_core"; 1950 assigned-clocks = <&aclk_vepu0>, <&cru CLK_VEPU0_CORE>; 1951 assigned-clock-rates = <400000000>, <700000000>; 1952 iommus = <&rkvenc0_mmu>; 1953 rockchip,srv = <&mpp_srv>; 1954 rockchip,taskqueue-node = <3>; 1955 rockchip,task-capacity = <8>; 1956 rockchip,ccu = <&rkvenc_ccu>; 1957 power-domains = <&power RK3576_PD_VEPU0>; 1958 status = "disabled"; 1959 }; 1960 1961 rkvenc0_mmu: iommu@27a0f000 { 1962 compatible = "rockchip,iommu-v2"; 1963 reg = <0x0 0x27a0f000 0x0 0x40>; 1964 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1965 interrupt-names = "irq_vepu0_mmu"; 1966 clocks = <&aclk_vepu0>, <&hclk_vepu0>; 1967 clock-names = "aclk", "iface"; 1968 #iommu-cells = <0>; 1969 rockchip,shootdown-entire; 1970 rockchip,disable-mmu-reset; 1971 rockchip,enable-cmd-retry; 1972 power-domains = <&power RK3576_PD_VEPU0>; 1973 status = "disabled"; 1974 }; 1975 1976 rkvenc1: rkvenc-core@27a10000 { 1977 compatible = "rockchip,rkv-encoder-rk3576-core"; 1978 reg = <0x0 0x27a10000 0x0 0x6000>; 1979 interrupts = <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>; 1980 interrupt-names = "irq_vepu1"; 1981 clocks = <&cru ACLK_VEPU1>, <&cru HCLK_VEPU1>, <&cru CLK_VEPU1_CORE>; 1982 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1983 rockchip,normal-rates = <400000000>, <0>, <700000000>; 1984 resets = <&cru SRST_A_VEPU1>, <&cru SRST_H_VEPU1>, 1985 <&cru SRST_VEPU1_CORE>; 1986 reset-names = "video_a", "video_h", "video_core"; 1987 assigned-clocks = <&cru ACLK_VEPU1>, <&cru CLK_VEPU1_CORE>; 1988 assigned-clock-rates = <400000000>, <700000000>; 1989 iommus = <&rkvenc1_mmu>; 1990 rockchip,srv = <&mpp_srv>; 1991 rockchip,taskqueue-node = <3>; 1992 rockchip,task-capacity = <8>; 1993 rockchip,ccu = <&rkvenc_ccu>; 1994 power-domains = <&power RK3576_PD_VEPU1>; 1995 status = "disabled"; 1996 }; 1997 1998 rkvenc1_mmu: iommu@27a1f000 { 1999 compatible = "rockchip,iommu-v2"; 2000 reg = <0x0 0x27a1f000 0x0 0x40>; 2001 interrupts = <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>; 2002 interrupt-names = "irq_vepu1_mmu"; 2003 clocks = <&cru ACLK_VEPU1>, <&cru HCLK_VEPU1>; 2004 clock-names = "aclk", "iface"; 2005 #iommu-cells = <0>; 2006 rockchip,disable-mmu-reset; 2007 rockchip,enable-cmd-retry; 2008 rockchip,shootdown-entire; 2009 power-domains = <&power RK3576_PD_VEPU1>; 2010 status = "disabled"; 2011 }; 2012 2013 rkvdec: rkvdec@27b00000 { 2014 compatible = "rockchip,rkv-decoder-v383"; 2015 reg = <0x0 0x27b00100 0x0 0x400>, <0x0 0x27b00000 0x0 0x100>; 2016 reg-names = "regs", "link"; 2017 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 2018 interrupt-names = "irq_rkvdec"; 2019 clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC_ROOT>, 2020 <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>; 2021 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_hevc_ca"; 2022 resets = <&cru SRST_A_RKVDEC_BIU >, <&cru SRST_H_RKVDEC_BIU>, 2023 <&cru SRST_RKVDEC_CORE>, <&cru SRST_RKVDEC_HEVC_CA>; 2024 reset-names = "video_a","video_h", "video_core", "video_hevc_cabac"; 2025 rockchip,normal-rates = <600000000>, <0>, <600000000>, <600000000>; 2026 assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC_ROOT>, 2027 <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>; 2028 assigned-clock-rates = <600000000>,<0>, <600000000>, <600000000>; 2029 iommus = <&rkvdec_mmu>; 2030 rockchip,srv = <&mpp_srv>; 2031 rockchip,task-capacity = <1>; 2032 rockchip,taskqueue-node = <5>; 2033 power-domains = <&power RK3576_PD_VDEC>; 2034 status = "disabled"; 2035 }; 2036 2037 rkvdec_mmu: iommu@27b00800 { 2038 compatible = "rockchip,iommu-v2"; 2039 reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>; 2040 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2041 interrupt-names = "irq_rkvdec_mmu"; 2042 clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>; 2043 clock-names = "aclk", "iface"; 2044 rockchip,disable-mmu-reset; 2045 rockchip,enable-cmd-retry; 2046 rockchip,shootdown-entire; 2047 #iommu-cells = <0>; 2048 power-domains = <&power RK3576_PD_VDEC>; 2049 status = "disabled"; 2050 }; 2051 2052 rkisp: isp@27c00000 { 2053 compatible = "rockchip,rk3576-rkisp"; 2054 reg = <0x0 0x27c00000 0x0 0x7f00>; 2055 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 2058 interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; 2059 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, 2060 <&cru CLK_ISP_CORE>, <&cru CLK_ISP_CORE_MARVIN>, 2061 <&cru CLK_ISP_CORE_VICAP>; 2062 clock-names = "aclk_isp", "hclk_isp", 2063 "clk_isp_core", "clk_isp_core_marvin", 2064 "clk_isp_core_vicap"; 2065 power-domains = <&power RK3576_PD_VI>; 2066 iommus = <&rkisp_mmu>; 2067 status = "disabled"; 2068 }; 2069 2070 rkisp_mmu: iommu@27c07f00 { 2071 compatible = "rockchip,iommu-v2"; 2072 reg = <0x0 0x27c07f00 0x0 0x100>; 2073 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 2074 interrupt-names = "isp_mmu"; 2075 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 2076 clock-names = "aclk", "iface"; 2077 power-domains = <&power RK3576_PD_VI>; 2078 #iommu-cells = <0>; 2079 rockchip,disable-mmu-reset; 2080 status = "disabled"; 2081 }; 2082 2083 rkcif: rkcif@27c10000 { 2084 compatible = "rockchip,rk3576-cif"; 2085 reg = <0x0 0x27c10000 0x0 0x800>; 2086 reg-names = "cif_regs"; 2087 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 2088 interrupt-names = "cif-intr"; 2089 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>, 2090 <&cru CLK_VICAP_I0CLK>, <&cru CLK_VICAP_I1CLK>, 2091 <&cru CLK_VICAP_I2CLK>, <&cru CLK_VICAP_I3CLK>, 2092 <&cru CLK_VICAP_I4CLK>; 2093 clock-names = "aclk_cif", "hclk_cif", "dclk_cif", 2094 "i0clk_cif", "i1clk_cif", 2095 "i2clk_cif", "i3clk_cif", 2096 "i4clk_cif"; 2097 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>, 2098 <&cru SRST_VICAP_I0CLK>, <&cru SRST_VICAP_I1CLK>, 2099 <&cru SRST_VICAP_I2CLK>, <&cru SRST_VICAP_I3CLK>, 2100 <&cru SRST_VICAP_I4CLK>; 2101 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", 2102 "rst_cif_iclk0", "rst_cif_iclk1", "rst_cif_iclk2", 2103 "rst_cif_iclk3", "rst_cif_iclk4"; 2104 assigned-clocks = <&cru DCLK_VICAP>; 2105 assigned-clock-rates = <600000000>; 2106 power-domains = <&power RK3576_PD_VI>; 2107 rockchip,grf = <&sys_grf>; 2108 iommus = <&rkcif_mmu>; 2109 status = "disabled"; 2110 }; 2111 2112 rkcif_mmu: iommu@27c10800 { 2113 compatible = "rockchip,iommu-v2"; 2114 reg = <0x0 0x27c10800 0x0 0x100>; 2115 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 2116 interrupt-names = "cif_mmu"; 2117 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; 2118 clock-names = "aclk", "iface"; 2119 power-domains = <&power RK3576_PD_VI>; 2120 rockchip,disable-mmu-reset; 2121 #iommu-cells = <0>; 2122 status = "disabled"; 2123 }; 2124 2125 rkvpss: vpss@27c30000 { 2126 compatible = "rockchip,rk3576-rkvpss"; 2127 reg = <0x0 0x27c30000 0x0 0x3f00>; 2128 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 2130 interrupt-names = "mi_irq", "vpss_irq"; 2131 clocks = <&cru ACLK_VPSS>, <&cru HCLK_VPSS>, 2132 <&cru CLK_CORE_VPSS>; 2133 clock-names = "aclk_vpss", "hclk_vpss", "clk_vpss"; 2134 power-domains = <&power RK3576_PD_VI>; 2135 iommus = <&rkvpss_mmu>; 2136 status = "disabled"; 2137 }; 2138 2139 rkvpss_mmu: iommu@27c33f00 { 2140 compatible = "rockchip,iommu-v2"; 2141 reg = <0x0 0x27c33f00 0x0 0x100>; 2142 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 2143 interrupt-names = "vpss_mmu"; 2144 clocks = <&cru ACLK_VPSS>, <&cru HCLK_VPSS>; 2145 clock-names = "aclk", "iface"; 2146 power-domains = <&power RK3576_PD_VI>; 2147 #iommu-cells = <0>; 2148 rockchip,disable-mmu-reset; 2149 status = "disabled"; 2150 }; 2151 2152 mipi0_csi2_hw: mipi0-csi2-hw@27c80000 { 2153 compatible = "rockchip,rk3576-mipi-csi2-hw"; 2154 reg = <0x0 0x27c80000 0x0 0x10000>; 2155 reg-names = "csihost_regs"; 2156 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>; 2158 interrupt-names = "csi-intr1", "csi-intr2"; 2159 clocks = <&cru PCLK_CSI_HOST_0>, <&cru ICLK_CSIHOST0>; 2160 clock-names = "pclk_csi2host", "iclk_csi2host"; 2161 resets = <&cru SRST_P_CSI_HOST_0>; 2162 reset-names = "srst_csihost_p"; 2163 status = "okay"; 2164 }; 2165 2166 mipi1_csi2_hw: mipi1-csi2-hw@27c90000 { 2167 compatible = "rockchip,rk3576-mipi-csi2-hw"; 2168 reg = <0x0 0x27c90000 0x0 0x10000>; 2169 reg-names = "csihost_regs"; 2170 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 2172 interrupt-names = "csi-intr1", "csi-intr2"; 2173 clocks = <&cru PCLK_CSI_HOST_1>; 2174 clock-names = "pclk_csi2host"; 2175 resets = <&cru SRST_P_CSI_HOST_1>; 2176 reset-names = "srst_csihost_p"; 2177 status = "okay"; 2178 }; 2179 2180 mipi2_csi2_hw: mipi2-csi2-hw@27ca0000 { 2181 compatible = "rockchip,rk3576-mipi-csi2-hw"; 2182 reg = <0x0 0x27ca0000 0x0 0x10000>; 2183 reg-names = "csihost_regs"; 2184 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 2186 interrupt-names = "csi-intr1", "csi-intr2"; 2187 clocks = <&cru PCLK_CSI_HOST_2>; 2188 clock-names = "pclk_csi2host"; 2189 resets = <&cru SRST_P_CSI_HOST_2>; 2190 reset-names = "srst_csihost_p"; 2191 status = "okay"; 2192 }; 2193 2194 mipi3_csi2_hw: mipi3-csi2-hw@27cb0000 { 2195 compatible = "rockchip,rk3576-mipi-csi2-hw"; 2196 reg = <0x0 0x27cb0000 0x0 0x10000>; 2197 reg-names = "csihost_regs"; 2198 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 2199 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 2200 interrupt-names = "csi-intr1", "csi-intr2"; 2201 clocks = <&cru PCLK_CSI_HOST_3>; 2202 clock-names = "pclk_csi2host"; 2203 resets = <&cru SRST_P_CSI_HOST_3>; 2204 reset-names = "srst_csihost_p"; 2205 status = "okay"; 2206 }; 2207 2208 mipi4_csi2_hw: mipi4-csi2-hw@27cc0000 { 2209 compatible = "rockchip,rk3576-mipi-csi2-hw"; 2210 reg = <0x0 0x27cc0000 0x0 0x10000>; 2211 reg-names = "csihost_regs"; 2212 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>; 2214 interrupt-names = "csi-intr1", "csi-intr2"; 2215 clocks = <&cru PCLK_CSI_HOST_4>; 2216 clock-names = "pclk_csi2host"; 2217 resets = <&cru SRST_P_CSI_HOST_4>; 2218 reset-names = "srst_csihost_p"; 2219 status = "okay"; 2220 }; 2221 2222 vop: vop@27d00000 { 2223 compatible = "rockchip,rk3576-vop"; 2224 reg = <0x0 0x27d00000 0x0 0x3000>, 2225 <0x0 0x27d05000 0x0 0x1000>, 2226 <0x0 0x27d06400 0x0 0x800>, 2227 <0x0 0x27d06c00 0x0 0x300>; 2228 reg-names = "regs", 2229 "gamma_lut", 2230 "acm_regs", 2231 "sharp_regs"; 2232 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 2236 interrupt-names = "vop-sys", 2237 "vop-vp0", 2238 "vop-vp1", 2239 "vop-vp2"; 2240 clocks = <&cru ACLK_VOP>, 2241 <&cru HCLK_VOP>, 2242 <&cru DCLK_VP0_SRC>, 2243 <&cru DCLK_VP1_SRC>, 2244 <&cru DCLK_VP2_SRC>; 2245 clock-names = "aclk_vop", 2246 "hclk_vop", 2247 "dclk_vp0", 2248 "dclk_vp1", 2249 "dclk_vp2"; 2250 iommus = <&vop_mmu>; 2251 power-domains = <&power RK3576_PD_VOP>; 2252 rockchip,grf = <&sys_grf>; 2253 rockchip,ioc-grf = <&ioc_grf>; 2254 rockchip,pmu = <&pmu>; 2255 status = "disabled"; 2256 2257 vop_out: ports { 2258 #address-cells = <1>; 2259 #size-cells = <0>; 2260 2261 vp0: port@0 { 2262 #address-cells = <1>; 2263 #size-cells = <0>; 2264 reg = <0>; 2265 2266 vp0_out_dsi: endpoint@0 { 2267 reg = <0>; 2268 remote-endpoint = <&dsi_in_vp0>; 2269 }; 2270 2271 vp0_out_edp: endpoint@1 { 2272 reg = <1>; 2273 remote-endpoint = <&edp_in_vp0>; 2274 }; 2275 2276 vp0_out_hdmi: endpoint@2 { 2277 reg = <2>; 2278 remote-endpoint = <&hdmi_in_vp0>; 2279 }; 2280 2281 vp0_out_dp0: endpoint@3 { 2282 reg = <3>; 2283 remote-endpoint = <&dp0_in_vp0>; 2284 }; 2285 2286 vp0_out_dp1: endpoint@4 { 2287 reg = <4>; 2288 remote-endpoint = <&dp1_in_vp0>; 2289 }; 2290 2291 vp0_out_dp2: endpoint@5 { 2292 reg = <5>; 2293 remote-endpoint = <&dp2_in_vp0>; 2294 }; 2295 }; 2296 2297 vp1: port@1 { 2298 #address-cells = <1>; 2299 #size-cells = <0>; 2300 reg = <1>; 2301 2302 vp1_out_rgb: endpoint@0 { 2303 reg = <0>; 2304 remote-endpoint = <&rgb_in_vp1>; 2305 }; 2306 2307 vp1_out_dsi: endpoint@1 { 2308 reg = <1>; 2309 remote-endpoint = <&dsi_in_vp1>; 2310 }; 2311 2312 vp1_out_edp: endpoint@2 { 2313 reg = <2>; 2314 remote-endpoint = <&edp_in_vp1>; 2315 }; 2316 2317 vp1_out_hdmi: endpoint@3 { 2318 reg = <3>; 2319 remote-endpoint = <&hdmi_in_vp1>; 2320 }; 2321 2322 vp1_out_dp0: endpoint@4 { 2323 reg = <4>; 2324 remote-endpoint = <&dp0_in_vp1>; 2325 }; 2326 2327 vp1_out_dp1: endpoint@5 { 2328 reg = <5>; 2329 remote-endpoint = <&dp1_in_vp1>; 2330 }; 2331 2332 vp1_out_dp2: endpoint@6 { 2333 reg = <6>; 2334 remote-endpoint = <&dp2_in_vp1>; 2335 }; 2336 }; 2337 2338 vp2: port@2 { 2339 #address-cells = <1>; 2340 #size-cells = <0>; 2341 reg = <2>; 2342 2343 vp2_out_rgb: endpoint@0 { 2344 reg = <0>; 2345 remote-endpoint = <&rgb_in_vp2>; 2346 }; 2347 2348 vp2_out_dsi: endpoint@1 { 2349 reg = <1>; 2350 remote-endpoint = <&dsi_in_vp2>; 2351 }; 2352 2353 vp2_out_edp: endpoint@2 { 2354 reg = <2>; 2355 remote-endpoint = <&edp_in_vp2>; 2356 }; 2357 2358 vp2_out_hdmi: endpoint@3 { 2359 reg = <3>; 2360 remote-endpoint = <&hdmi_in_vp2>; 2361 }; 2362 2363 vp2_out_dp0: endpoint@4 { 2364 reg = <4>; 2365 remote-endpoint = <&dp0_in_vp2>; 2366 }; 2367 2368 vp2_out_dp1: endpoint@5 { 2369 reg = <5>; 2370 remote-endpoint = <&dp1_in_vp2>; 2371 }; 2372 2373 vp2_out_dp2: endpoint@6 { 2374 reg = <6>; 2375 remote-endpoint = <&dp2_in_vp2>; 2376 }; 2377 }; 2378 }; 2379 }; 2380 2381 vop_mmu: iommu@27d07e00 { 2382 compatible = "rockchip,iommu-v2"; 2383 reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; 2384 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 2385 interrupt-names = "vop_mmu"; 2386 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 2387 clock-names = "aclk", "iface"; 2388 #iommu-cells = <0>; 2389 rockchip,disable-device-link-resume; 2390 rockchip,shootdown-entire; 2391 status = "disabled"; 2392 }; 2393 2394 spdif_tx2: spdif-tx@27d20000 { 2395 compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; 2396 reg = <0x0 0x27d20000 0x0 0x1000>; 2397 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 2398 clocks = <&cru MCLK_SPDIF_TX2>, <&cru HCLK_SPDIF_TX2>; 2399 clock-names = "mclk", "hclk"; 2400 dmas = <&dmac2 28>; 2401 dma-names = "tx"; 2402 power-domains = <&power RK3576_PD_VO0>; 2403 #sound-dai-cells = <0>; 2404 status = "disabled"; 2405 }; 2406 2407 spdif_rx2: spdif-rx@27d30000 { 2408 compatible = "rockchip,rk3576-spdifrx", "rockchip,rk3308-spdifrx"; 2409 reg = <0x0 0x27d30000 0x0 0x1000>; 2410 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 2411 clocks = <&cru MCLK_SPDIF_RX2>, <&cru HCLK_SPDIF_RX2>; 2412 clock-names = "mclk", "hclk"; 2413 dmas = <&dmac2 27>; 2414 dma-names = "rx"; 2415 power-domains = <&power RK3576_PD_VO0>; 2416 resets = <&cru SRST_M_SPDIF_RX2>; 2417 reset-names = "spdifrx-m"; 2418 status = "disabled"; 2419 }; 2420 2421 sai5: sai@27d40000 { 2422 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 2423 reg = <0x0 0x27d40000 0x0 0x1000>; 2424 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 2425 clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>; 2426 clock-names = "mclk", "hclk"; 2427 dmas = <&dmac2 3>; 2428 dma-names = "rx"; 2429 power-domains = <&power RK3576_PD_VO0>; 2430 resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>; 2431 reset-names = "m", "h"; 2432 #sound-dai-cells = <0>; 2433 sound-name-prefix = "SAI5"; 2434 status = "disabled"; 2435 }; 2436 2437 sai6: sai@27d50000 { 2438 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 2439 reg = <0x0 0x27d50000 0x0 0x1000>; 2440 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 2441 clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>; 2442 clock-names = "mclk", "hclk"; 2443 dmas = <&dmac2 4>, <&dmac2 5>; 2444 dma-names = "tx", "rx"; 2445 power-domains = <&power RK3576_PD_VO0>; 2446 resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>; 2447 reset-names = "m", "h"; 2448 #sound-dai-cells = <0>; 2449 sound-name-prefix = "SAI6"; 2450 status = "disabled"; 2451 }; 2452 2453 dsi: dsi@27d80000 { 2454 compatible = "rockchip,rk3576-mipi-dsi2"; 2455 reg = <0x0 0x27d80000 0x0 0x10000>; 2456 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 2457 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; 2458 clock-names = "pclk", "sys_clk"; 2459 resets = <&cru SRST_P_DSIHOST0>; 2460 reset-names = "apb"; 2461 power-domains = <&power RK3576_PD_VO0>; 2462 phys = <&mipidcphy0>; 2463 phy-names = "dcphy"; 2464 rockchip,grf = <&vo0_grf>; 2465 #address-cells = <1>; 2466 #size-cells = <0>; 2467 status = "disabled"; 2468 2469 ports { 2470 #address-cells = <1>; 2471 #size-cells = <0>; 2472 2473 dsi_in: port@0 { 2474 reg = <0>; 2475 #address-cells = <1>; 2476 #size-cells = <0>; 2477 2478 dsi_in_vp0: endpoint@0 { 2479 reg = <0>; 2480 remote-endpoint = <&vp0_out_dsi>; 2481 status = "disabled"; 2482 }; 2483 2484 dsi_in_vp1: endpoint@1 { 2485 reg = <1>; 2486 remote-endpoint = <&vp1_out_dsi>; 2487 status = "disabled"; 2488 }; 2489 2490 dsi_in_vp2: endpoint@2 { 2491 reg = <2>; 2492 remote-endpoint = <&vp2_out_dsi>; 2493 status = "disabled"; 2494 }; 2495 2496 dsi_in_vopl: endpoint@3 { 2497 reg = <3>; 2498 remote-endpoint = <&vopl_out_dsi>; 2499 status = "disabled"; 2500 }; 2501 }; 2502 }; 2503 }; 2504 2505 hdcp0: hdcp@27d90000 { 2506 compatible = "rockchip,rk3576-hdcp"; 2507 reg = <0x0 0x27d90000 0x0 0x80>; 2508 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2509 clocks = <&aclk_hdcp0>, <&cru PCLK_HDCP0>, 2510 <&cru HCLK_HDCP0>, <&scmi_clk HCLK_HDCP_KEY0>, 2511 <&scmi_clk PCLK_HDCP0_TRNG>; 2512 clock-names = "aclk", "pclk", "hclk", "hclk_key", "pclk_trng"; 2513 resets = <&cru SRST_HDCP0>, <&cru SRST_H_HDCP0>, 2514 <&cru SRST_A_HDCP0>; 2515 reset-names = "hdcp", "h_hdcp", "a_hdcp"; 2516 power-domains = <&power RK3576_PD_VO0>; 2517 rockchip,vo-grf = <&vo0_grf>; 2518 status = "disabled"; 2519 }; 2520 2521 hdmi: hdmi@27da0000 { 2522 compatible = "rockchip,rk3576-dw-hdmi"; 2523 reg = <0x0 0x27da0000 0x0 0x10000>, <0x0 0x27db0000 0x0 0x10000>; 2524 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2526 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2527 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2528 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 2529 clocks = <&cru PCLK_HDMITX0>, 2530 <&cru CLK_HDMITXHPD>, 2531 <&cru CLK_HDMITX0_EARC>, 2532 <&cru CLK_HDMITX0_REF>, 2533 <&cru MCLK_SAI5_8CH>, 2534 <&cru DCLK_VP0>, 2535 <&cru DCLK_VP1>, 2536 <&cru DCLK_VP2>, 2537 <&cru DCLK_EBC>, 2538 <&hclk_vo1>, 2539 <&hdptxphy_hdmi>; 2540 clock-names = "pclk", 2541 "hpd", 2542 "earc", 2543 "hdmitx_ref", 2544 "aud", 2545 "dclk_vp0", 2546 "dclk_vp1", 2547 "dclk_vp2", 2548 "dclk_ebc", 2549 "hclk_vo1", 2550 "link_clk"; 2551 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHPD>; 2552 reset-names = "ref", "hdp"; 2553 power-domains = <&power RK3576_PD_VO0>; 2554 pinctrl-names = "default"; 2555 pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; 2556 reg-io-width = <4>; 2557 rockchip,grf = <&sys_grf>; 2558 rockchip,vo1_grf = <&vo0_grf>; 2559 phys = <&hdptxphy_hdmi>; 2560 phy-names = "hdmi"; 2561 #sound-dai-cells = <0>; 2562 status = "disabled"; 2563 2564 ports { 2565 #address-cells = <1>; 2566 #size-cells = <0>; 2567 2568 hdmi_in: port@0 { 2569 reg = <0>; 2570 #address-cells = <1>; 2571 #size-cells = <0>; 2572 2573 hdmi_in_vp0: endpoint@0 { 2574 reg = <0>; 2575 remote-endpoint = <&vp0_out_hdmi>; 2576 status = "disabled"; 2577 }; 2578 2579 hdmi_in_vp1: endpoint@1 { 2580 reg = <1>; 2581 remote-endpoint = <&vp1_out_hdmi>; 2582 status = "disabled"; 2583 }; 2584 2585 hdmi_in_vp2: endpoint@2 { 2586 reg = <2>; 2587 remote-endpoint = <&vp2_out_hdmi>; 2588 status = "disabled"; 2589 }; 2590 2591 hdmi_in_vopl: endpoint@3 { 2592 reg = <3>; 2593 remote-endpoint = <&vopl_out_hdmi>; 2594 status = "disabled"; 2595 }; 2596 }; 2597 }; 2598 }; 2599 2600 edp: edp@27dc0000 { 2601 compatible = "rockchip,rk3576-edp"; 2602 reg = <0x0 0x27dc0000 0x0 0x1000>; 2603 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 2604 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, 2605 <&cru CLK_EDP0_200M>, <&hclk_vo0>; 2606 clock-names = "dp", "pclk", "spdif", "hclk"; 2607 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; 2608 reset-names = "dp", "apb"; 2609 phys = <&hdptxphy>; 2610 phy-names = "dp"; 2611 power-domains = <&power RK3576_PD_VO0>; 2612 rockchip,grf = <&vo0_grf>; 2613 status = "disabled"; 2614 2615 ports { 2616 #address-cells = <1>; 2617 #size-cells = <0>; 2618 2619 port@0 { 2620 reg = <0>; 2621 #address-cells = <1>; 2622 #size-cells = <0>; 2623 2624 edp_in_vp0: endpoint@0 { 2625 reg = <0>; 2626 remote-endpoint = <&vp0_out_edp>; 2627 status = "disabled"; 2628 }; 2629 2630 edp_in_vp1: endpoint@1 { 2631 reg = <1>; 2632 remote-endpoint = <&vp1_out_edp>; 2633 status = "disabled"; 2634 }; 2635 2636 edp_in_vp2: endpoint@2 { 2637 reg = <2>; 2638 remote-endpoint = <&vp2_out_edp>; 2639 status = "disabled"; 2640 }; 2641 2642 edp_in_vopl: endpoint@3 { 2643 reg = <3>; 2644 remote-endpoint = <&vopl_out_edp>; 2645 status = "disabled"; 2646 }; 2647 }; 2648 }; 2649 }; 2650 2651 dp: dp@27e40000 { 2652 compatible = "rockchip,rk3576-dp"; 2653 reg = <0x0 0x27e40000 0x0 0x30000>; 2654 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 2655 clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16MHZ_0>, 2656 <&cru ACLK_DP0>; 2657 clock-names = "apb", "aux", "hdcp"; 2658 assigned-clocks = <&cru CLK_AUX16MHZ_0>; 2659 assigned-clock-rates = <16000000>; 2660 resets = <&cru SRST_DP0>; 2661 phys = <&usbdp_phy_dp>; 2662 power-domains = <&power RK3576_PD_VO1>; 2663 status = "disabled"; 2664 2665 dp0: dp0 { 2666 ports { 2667 #address-cells = <1>; 2668 #size-cells = <0>; 2669 2670 port@0 { 2671 reg = <0>; 2672 #address-cells = <1>; 2673 #size-cells = <0>; 2674 2675 dp0_in_vp0: endpoint@0 { 2676 reg = <0>; 2677 remote-endpoint = <&vp0_out_dp0>; 2678 status = "disabled"; 2679 }; 2680 2681 dp0_in_vp1: endpoint@1 { 2682 reg = <1>; 2683 remote-endpoint = <&vp1_out_dp0>; 2684 status = "disabled"; 2685 }; 2686 2687 dp0_in_vp2: endpoint@2 { 2688 reg = <2>; 2689 remote-endpoint = <&vp2_out_dp0>; 2690 status = "disabled"; 2691 }; 2692 }; 2693 }; 2694 }; 2695 2696 dp1: dp1 { 2697 ports { 2698 #address-cells = <1>; 2699 #size-cells = <0>; 2700 2701 port@0 { 2702 reg = <0>; 2703 #address-cells = <1>; 2704 #size-cells = <0>; 2705 2706 dp1_in_vp0: endpoint@0 { 2707 reg = <0>; 2708 remote-endpoint = <&vp0_out_dp1>; 2709 status = "disabled"; 2710 }; 2711 2712 dp1_in_vp1: endpoint@1 { 2713 reg = <1>; 2714 remote-endpoint = <&vp1_out_dp1>; 2715 status = "disabled"; 2716 }; 2717 2718 dp1_in_vp2: endpoint@2 { 2719 reg = <2>; 2720 remote-endpoint = <&vp2_out_dp1>; 2721 status = "disabled"; 2722 }; 2723 }; 2724 }; 2725 }; 2726 2727 dp2: dp2 { 2728 ports { 2729 #address-cells = <1>; 2730 #size-cells = <0>; 2731 port@0 { 2732 reg = <0>; 2733 #address-cells = <1>; 2734 #size-cells = <0>; 2735 2736 dp2_in_vp0: endpoint@0 { 2737 reg = <0>; 2738 remote-endpoint = <&vp0_out_dp2>; 2739 status = "disabled"; 2740 }; 2741 2742 dp2_in_vp1: endpoint@1 { 2743 reg = <1>; 2744 remote-endpoint = <&vp1_out_dp2>; 2745 status = "disabled"; 2746 }; 2747 2748 dp2_in_vp2: endpoint@2 { 2749 reg = <2>; 2750 remote-endpoint = <&vp2_out_dp2>; 2751 status = "disabled"; 2752 }; 2753 }; 2754 }; 2755 }; 2756 }; 2757 2758 hdcp1: hdcp@27e70000 { 2759 compatible = "rockchip,rk3576-hdcp"; 2760 reg = <0x0 0x27e70000 0x0 0x80>; 2761 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 2762 clocks = <&aclk_hdcp1>, <&cru PCLK_HDCP1>, 2763 <&cru HCLK_HDCP1>, <&scmi_clk HCLK_HDCP_KEY1>, 2764 <&scmi_clk PCLK_HDCP1_TRNG>; 2765 clock-names = "aclk", "pclk", "hclk", "hclk_key", "pclk_trng"; 2766 resets = <&cru SRST_HDCP1>, <&cru SRST_H_HDCP1>, 2767 <&cru SRST_A_HDCP1>; 2768 reset-names = "hdcp", "h_hdcp", "a_hdcp"; 2769 power-domains = <&power RK3576_PD_VO1>; 2770 rockchip,vo-grf = <&vo1_grf>; 2771 status = "disabled"; 2772 }; 2773 2774 spdif_tx3: spdif-tx@27ea0000 { 2775 compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; 2776 reg = <0x0 0x27ea0000 0x0 0x1000>; 2777 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 2778 clocks = <&cru MCLK_SPDIF_TX3>, <&cru HCLK_SPDIF_TX3>; 2779 clock-names = "mclk", "hclk"; 2780 dmas = <&dmac2 29>; 2781 dma-names = "tx"; 2782 power-domains = <&power RK3576_PD_VO1>; 2783 #sound-dai-cells = <0>; 2784 status = "disabled"; 2785 }; 2786 2787 spdif_tx4: spdif-tx@27eb0000 { 2788 compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; 2789 reg = <0x0 0x27eb0000 0x0 0x1000>; 2790 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 2791 clocks = <&cru MCLK_SPDIF_TX4>, <&cru HCLK_SPDIF_TX4>; 2792 clock-names = "mclk", "hclk"; 2793 dmas = <&dmac1 6>; 2794 dma-names = "tx"; 2795 power-domains = <&power RK3576_PD_VO1>; 2796 #sound-dai-cells = <0>; 2797 status = "disabled"; 2798 }; 2799 2800 spdif_tx5: spdif-tx@27ec0000 { 2801 compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; 2802 reg = <0x0 0x27ec0000 0x0 0x1000>; 2803 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 2804 clocks = <&cru MCLK_SPDIF_TX5>, <&cru HCLK_SPDIF_TX5>; 2805 clock-names = "mclk", "hclk"; 2806 dmas = <&dmac0 25>; 2807 dma-names = "tx"; 2808 power-domains = <&power RK3576_PD_VO1>; 2809 #sound-dai-cells = <0>; 2810 status = "disabled"; 2811 }; 2812 2813 sai7: sai@27ed0000 { 2814 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 2815 reg = <0x0 0x27ed0000 0x0 0x1000>; 2816 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 2817 clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>; 2818 clock-names = "mclk", "hclk"; 2819 dmas = <&dmac2 19>; 2820 dma-names = "tx"; 2821 power-domains = <&power RK3576_PD_VO1>; 2822 resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>; 2823 reset-names = "m", "h"; 2824 #sound-dai-cells = <0>; 2825 sound-name-prefix = "SAI7"; 2826 status = "disabled"; 2827 }; 2828 2829 sai8: sai@27ee0000 { 2830 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 2831 reg = <0x0 0x27ee0000 0x0 0x1000>; 2832 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 2833 clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>; 2834 clock-names = "mclk", "hclk"; 2835 dmas = <&dmac1 7>; 2836 dma-names = "tx"; 2837 power-domains = <&power RK3576_PD_VO1>; 2838 resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>; 2839 reset-names = "m", "h"; 2840 #sound-dai-cells = <0>; 2841 sound-name-prefix = "SAI8"; 2842 status = "disabled"; 2843 }; 2844 2845 sai9: sai@27ef0000 { 2846 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 2847 reg = <0x0 0x27ef0000 0x0 0x1000>; 2848 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2849 clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>; 2850 clock-names = "mclk", "hclk"; 2851 dmas = <&dmac0 26>; 2852 dma-names = "tx"; 2853 power-domains = <&power RK3576_PD_VO1>; 2854 resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>; 2855 reset-names = "m", "h"; 2856 #sound-dai-cells = <0>; 2857 sound-name-prefix = "SAI9"; 2858 status = "disabled"; 2859 }; 2860 2861 pcie0: pcie@2a200000 { 2862 compatible = "rockchip,rk3576-pcie", "snps,dw-pcie"; 2863 #address-cells = <3>; 2864 #size-cells = <2>; 2865 bus-range = <0x0 0xf>; 2866 clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, 2867 <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, 2868 <&cru CLK_PCIE0_AUX>; 2869 clock-names = "aclk_mst", "aclk_slv", 2870 "aclk_dbi", "pclk", 2871 "aux"; 2872 device_type = "pci"; 2873 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 2874 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 2875 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 2876 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 2877 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 2878 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 2879 #interrupt-cells = <1>; 2880 interrupt-map-mask = <0 0 0 7>; 2881 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 2882 <0 0 0 2 &pcie0_intc 1>, 2883 <0 0 0 3 &pcie0_intc 2>, 2884 <0 0 0 4 &pcie0_intc 3>; 2885 linux,pci-domain = <0>; 2886 num-ib-windows = <8>; 2887 num-viewport = <8>; 2888 num-ob-windows = <2>; 2889 max-link-speed = <2>; 2890 num-lanes = <1>; 2891 phys = <&combphy0_ps PHY_TYPE_PCIE>; 2892 phy-names = "pcie-phy"; 2893 power-domains = <&power RK3576_PD_PHP>; 2894 ranges = <0x81000000 0x0 0x20000000 0x0 0x20000000 0x0 0x00100000 2895 0x82000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00f00000 2896 0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; 2897 reg = <0x0 0x2a200000 0x0 0x00010000>, 2898 <0x0 0x22000000 0x0 0x00400000>, 2899 <0x0 0x20000000 0x0 0x00100000>; 2900 reg-names = "pcie-apb", "pcie-dbi", "config"; 2901 resets = <&cru SRST_PCIE0_POWER_UP>; 2902 reset-names = "pipe"; 2903 status = "disabled"; 2904 2905 pcie0_intc: legacy-interrupt-controller { 2906 interrupt-controller; 2907 #address-cells = <0>; 2908 #interrupt-cells = <1>; 2909 interrupt-parent = <&gic>; 2910 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; 2911 }; 2912 }; 2913 2914 pcie1: pcie@2a210000 { 2915 compatible = "rockchip,rk3576-pcie", "snps,dw-pcie"; 2916 #address-cells = <3>; 2917 #size-cells = <2>; 2918 bus-range = <0x20 0x2f>; 2919 clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, 2920 <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, 2921 <&cru CLK_PCIE1_AUX>; 2922 clock-names = "aclk_mst", "aclk_slv", 2923 "aclk_dbi", "pclk", 2924 "aux"; 2925 device_type = "pci"; 2926 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2927 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2928 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 2929 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2930 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 2931 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 2932 #interrupt-cells = <1>; 2933 interrupt-map-mask = <0 0 0 7>; 2934 interrupt-map = <0 0 0 1 &pcie1_intc 0>, 2935 <0 0 0 2 &pcie1_intc 1>, 2936 <0 0 0 3 &pcie1_intc 2>, 2937 <0 0 0 4 &pcie1_intc 3>; 2938 linux,pci-domain = <0>; 2939 num-ib-windows = <8>; 2940 num-viewport = <8>; 2941 num-ob-windows = <2>; 2942 max-link-speed = <2>; 2943 num-lanes = <1>; 2944 phys = <&combphy1_psu PHY_TYPE_PCIE>; 2945 phy-names = "pcie-phy"; 2946 power-domains = <&power RK3576_PD_SUBPHP>; 2947 ranges = <0x81000000 0x0 0x21000000 0x0 0x21000000 0x0 0x00100000 2948 0x82000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00f00000 2949 0x83000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; 2950 reg = <0x0 0x2a210000 0x0 0x00010000>, 2951 <0x0 0x22400000 0x0 0x00400000>, 2952 <0x0 0x21000000 0x0 0x00100000>; 2953 reg-names = "pcie-apb", "pcie-dbi", "config"; 2954 resets = <&cru SRST_PCIE1_POWER_UP>; 2955 reset-names = "pipe"; 2956 status = "disabled"; 2957 2958 pcie1_intc: legacy-interrupt-controller { 2959 interrupt-controller; 2960 #address-cells = <0>; 2961 #interrupt-cells = <1>; 2962 interrupt-parent = <&gic>; 2963 interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>; 2964 }; 2965 }; 2966 2967 gmac0: ethernet@2a220000 { 2968 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 2969 reg = <0x0 0x2a220000 0x0 0x10000>; 2970 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 2971 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2972 interrupt-names = "macirq", "eth_wake_irq"; 2973 rockchip,grf = <&sdgmac_grf>; 2974 rockchip,php_grf = <&ioc_grf>; 2975 clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>, 2976 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 2977 <&cru CLK_GMAC0_PTP_REF>; 2978 clock-names = "stmmaceth", "clk_mac_ref", 2979 "pclk_mac", "aclk_mac", 2980 "ptp_ref"; 2981 resets = <&cru SRST_A_GMAC0>; 2982 reset-names = "stmmaceth"; 2983 power-domains = <&power RK3576_PD_SDGMAC>; 2984 2985 snps,mixed-burst; 2986 snps,tso; 2987 2988 snps,axi-config = <&gmac0_stmmac_axi_setup>; 2989 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 2990 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 2991 status = "disabled"; 2992 2993 mdio0: mdio { 2994 compatible = "snps,dwmac-mdio"; 2995 #address-cells = <0x1>; 2996 #size-cells = <0x0>; 2997 }; 2998 2999 gmac0_stmmac_axi_setup: stmmac-axi-config { 3000 snps,wr_osr_lmt = <4>; 3001 snps,rd_osr_lmt = <8>; 3002 snps,blen = <0 0 0 0 16 8 4>; 3003 }; 3004 3005 gmac0_mtl_rx_setup: rx-queues-config { 3006 snps,rx-queues-to-use = <1>; 3007 queue0 {}; 3008 }; 3009 3010 gmac0_mtl_tx_setup: tx-queues-config { 3011 snps,tx-queues-to-use = <1>; 3012 queue0 {}; 3013 }; 3014 }; 3015 3016 gmac1: ethernet@2a230000 { 3017 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 3018 reg = <0x0 0x2a230000 0x0 0x10000>; 3019 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 3020 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 3021 interrupt-names = "macirq", "eth_wake_irq"; 3022 rockchip,grf = <&sdgmac_grf>; 3023 rockchip,php_grf = <&ioc_grf>; 3024 clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>, 3025 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 3026 <&cru CLK_GMAC1_PTP_REF>; 3027 clock-names = "stmmaceth", "clk_mac_ref", 3028 "pclk_mac", "aclk_mac", 3029 "ptp_ref"; 3030 resets = <&cru SRST_A_GMAC1>; 3031 reset-names = "stmmaceth"; 3032 power-domains = <&power RK3576_PD_SDGMAC>; 3033 3034 snps,mixed-burst; 3035 snps,tso; 3036 3037 snps,axi-config = <&gmac1_stmmac_axi_setup>; 3038 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 3039 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 3040 status = "disabled"; 3041 3042 mdio1: mdio { 3043 compatible = "snps,dwmac-mdio"; 3044 #address-cells = <0x1>; 3045 #size-cells = <0x0>; 3046 }; 3047 3048 gmac1_stmmac_axi_setup: stmmac-axi-config { 3049 snps,wr_osr_lmt = <4>; 3050 snps,rd_osr_lmt = <8>; 3051 snps,blen = <0 0 0 0 16 8 4>; 3052 }; 3053 3054 gmac1_mtl_rx_setup: rx-queues-config { 3055 snps,rx-queues-to-use = <1>; 3056 queue0 {}; 3057 }; 3058 3059 gmac1_mtl_tx_setup: tx-queues-config { 3060 snps,tx-queues-to-use = <1>; 3061 queue0 {}; 3062 }; 3063 }; 3064 3065 sata0: sata@2a240000 { 3066 compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; 3067 reg = <0 0x2a240000 0 0x1000>; 3068 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 3069 <&cru CLK_RXOOB0>; 3070 clock-names = "sata", "pmalive", "rxoob"; 3071 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 3072 interrupt-names = "hostc"; 3073 power-domains = <&power RK3576_PD_SUBPHP>; 3074 phys = <&combphy0_ps PHY_TYPE_SATA>; 3075 phy-names = "sata-phy"; 3076 ports-implemented = <0x1>; 3077 status = "disabled"; 3078 }; 3079 3080 sata1: sata@2a250000 { 3081 compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; 3082 reg = <0 0x2a250000 0 0x1000>; 3083 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 3084 <&cru CLK_RXOOB1>; 3085 clock-names = "sata", "pmalive", "rxoob"; 3086 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 3087 interrupt-names = "hostc"; 3088 power-domains = <&power RK3576_PD_SUBPHP>; 3089 phys = <&combphy1_psu PHY_TYPE_SATA>; 3090 phy-names = "sata-phy"; 3091 ports-implemented = <0x1>; 3092 status = "disabled"; 3093 }; 3094 3095 mmu0: iommu@2a260000 { 3096 compatible = "rockchip,iommu-v2"; 3097 reg = <0x0 0x2a260000 0x0 0x100>; 3098 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 3099 interrupt-names = "mmu0"; 3100 clocks = <&cru ACLK_MMU0>, <&cru ACLK_SLV_MMU0>, <&cru PCLK_PHP_ROOT>; 3101 clock-names = "aclk", "iface", "root"; 3102 power-domains = <&power RK3576_PD_PHP>; 3103 #iommu-cells = <0>; 3104 status = "disabled"; 3105 }; 3106 3107 mmu1: iommu@2a270000 { 3108 compatible = "rockchip,iommu-v2"; 3109 reg = <0x0 0x2a270000 0x0 0x100>; 3110 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 3111 interrupt-names = "mmu1"; 3112 clocks = <&cru ACLK_MMU1>, <&cru ACLK_SLV_MMU1>, <&cru PCLK_PHP_ROOT>; 3113 clock-names = "aclk", "iface", "root"; 3114 power-domains = <&power RK3576_PD_PHP>; 3115 #iommu-cells = <0>; 3116 status = "disabled"; 3117 }; 3118 3119 mmu2: iommu@2a2c0000 { 3120 compatible = "rockchip,iommu-v2"; 3121 reg = <0x0 0x2a2c0000 0x0 0x100>; 3122 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 3123 interrupt-names = "mmu2"; 3124 clocks = <&cru ACLK_MMU2>, <&cru ACLK_SLV_MMU2>, <&cru PCLK_USB_ROOT>; 3125 clock-names = "aclk", "iface", "root"; 3126 power-domains = <&power RK3576_PD_USB>; 3127 #iommu-cells = <0>; 3128 status = "disabled"; 3129 }; 3130 3131 ufs: ufs@2a2d0000 { 3132 compatible = "rockchip,rk3576-ufs"; 3133 reg = <0x0 0x2a2d0000 0 0x10000>, /* 0: HCI standard */ 3134 <0x0 0x2b040000 0 0x10000>, /* 1: Mphy */ 3135 <0x0 0x2601f000 0 0x1000>, /* 2: HCI Vendor specified */ 3136 <0x0 0x2603c000 0 0x1000>, /* 3: Mphy Vendor specified */ 3137 <0x0 0x2a2e0000 0 0x10000>; /* 4: HCI apb */ 3138 reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; 3139 clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, 3140 <&cru CLK_REF_UFS_CLKOUT>; 3141 clock-names = "core", "pclk", "pclk_mphy", 3142 "ref_out"; 3143 assigned-clocks = <&cru CLK_REF_OSC_MPHY>; 3144 assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; 3145 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 3146 power-domains = <&power RK3576_PD_USB>; 3147 pinctrl-0 = <&ufs_rst &ufs_refclk>; 3148 pinctrl-names = "default"; 3149 resets = <&cru SRST_A_UFS_BIU>; 3150 reset-names = "rst"; 3151 status = "disabled"; 3152 }; 3153 3154 sfc1: spi@2a300000 { 3155 compatible = "rockchip,sfc"; 3156 reg = <0x0 0x2a300000 0x0 0x4000>; 3157 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 3158 clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; 3159 clock-names = "clk_sfc", "hclk_sfc"; 3160 assigned-clocks = <&cru SCLK_FSPI1_X2>; 3161 assigned-clock-rates = <80000000>; 3162 #address-cells = <1>; 3163 #size-cells = <0>; 3164 status = "disabled"; 3165 }; 3166 3167 sdmmc: mmc@2a310000 { 3168 compatible = "rockchip,rk3576-dw-mshc", 3169 "rockchip,rk3288-dw-mshc"; 3170 reg = <0x0 0x2a310000 0x0 0x4000>; 3171 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 3172 max-frequency = <200000000>; 3173 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; 3174 clock-names = "biu", "ciu"; 3175 fifo-depth = <0x100>; 3176 pinctrl-names = "default"; 3177 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>; 3178 resets = <&cru SRST_H_SDMMC0>; 3179 reset-names = "reset"; 3180 rockchip,use-v2-tuning; 3181 status = "disabled"; 3182 }; 3183 3184 sdio: mmc@2a320000 { 3185 compatible = "rockchip,rk3576-dw-mshc", 3186 "rockchip,rk3288-dw-mshc"; 3187 reg = <0x0 0x2a320000 0x0 0x4000>; 3188 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 3189 max-frequency = <200000000>; 3190 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>; 3191 clock-names = "biu", "ciu"; 3192 fifo-depth = <0x100>; 3193 pinctrl-names = "default"; 3194 pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>; 3195 resets = <&cru SRST_H_SDIO>; 3196 reset-names = "reset"; 3197 rockchip,use-v2-tuning; 3198 status = "disabled"; 3199 }; 3200 3201 sdhci: mmc@2a330000 { 3202 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; 3203 reg = <0x0 0x2a330000 0x0 0x10000>; 3204 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 3205 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; 3206 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 3207 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 3208 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 3209 <&cru TCLK_EMMC>; 3210 clock-names = "core", "bus", "axi", "block", "timer"; 3211 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 3212 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 3213 <&cru SRST_T_EMMC>; 3214 reset-names = "core", "bus", "axi", "block", "timer"; 3215 max-frequency = <200000000>; 3216 status = "disabled"; 3217 }; 3218 3219 sfc0: spi@2a340000 { 3220 compatible = "rockchip,sfc"; 3221 reg = <0x0 0x2a340000 0x0 0x4000>; 3222 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 3223 clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; 3224 clock-names = "clk_sfc", "hclk_sfc"; 3225 assigned-clocks = <&cru SCLK_FSPI_X2>; 3226 assigned-clock-rates = <80000000>; 3227 #address-cells = <1>; 3228 #size-cells = <0>; 3229 status = "disabled"; 3230 }; 3231 3232 crypto: crypto@2a400000 { 3233 compatible = "rockchip,crypto-v4"; 3234 reg = <0x0 0x2a400000 0x0 0x2000>; 3235 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 3236 clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, 3237 <&cru CLK_PKA_CRYPTO_NS>; 3238 clock-names = "aclk", "hclk", "pka"; 3239 assigned-clocks = <&cru ACLK_CRYPTO_NS>, <&cru CLK_PKA_CRYPTO_NS>; 3240 assigned-clock-rates = <300000000>, <300000000>; 3241 resets = <&cru SRST_H_CRYPTO_NS>; 3242 reset-names = "crypto-rst"; 3243 status = "disabled"; 3244 }; 3245 3246 rng: rng@2a410000 { 3247 compatible = "rockchip,rkrng"; 3248 reg = <0x0 0x2a410000 0x0 0x200>; 3249 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 3250 clocks = <&cru HCLK_TRNG_NS>; 3251 clock-names = "hclk_trng"; 3252 resets = <&cru SRST_H_TRNG_NS>; 3253 reset-names = "reset"; 3254 status = "disabled"; 3255 }; 3256 3257 otp: otp@2a580000 { 3258 compatible = "rockchip,rk3576-otp"; 3259 reg = <0x0 0x2a580000 0x0 0x400>; 3260 #address-cells = <1>; 3261 #size-cells = <1>; 3262 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>; 3263 clock-names = "otpc", "apb"; 3264 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; 3265 reset-names = "otpc", "apb"; 3266 3267 /* Data cells */ 3268 cpu_code: cpu-code@2 { 3269 reg = <0x02 0x2>; 3270 }; 3271 otp_cpu_version: cpu-version@5 { 3272 reg = <0x05 0x1>; 3273 bits = <3 3>; 3274 }; 3275 otp_id: id@a { 3276 reg = <0x0a 0x10>; 3277 }; 3278 cpub_leakage: cpub-leakage@1e { 3279 reg = <0x1e 0x1>; 3280 }; 3281 cpul_leakage: cpul-leakage@1f { 3282 reg = <0x1f 0x1>; 3283 }; 3284 npu_leakage: npu-leakage@20 { 3285 reg = <0x20 0x1>; 3286 }; 3287 gpu_leakage: gpu-leakage@21 { 3288 reg = <0x21 0x1>; 3289 }; 3290 log_leakage: log-leakage@22 { 3291 reg = <0x22 0x1>; 3292 }; 3293 }; 3294 3295 sai0: sai@2a600000 { 3296 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 3297 reg = <0x0 0x2a600000 0x0 0x1000>; 3298 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 3299 clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>; 3300 clock-names = "mclk", "hclk"; 3301 dmas = <&dmac0 0>, <&dmac0 1>; 3302 dma-names = "tx", "rx"; 3303 power-domains = <&power RK3576_PD_AUDIO>; 3304 resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; 3305 reset-names = "m", "h"; 3306 pinctrl-names = "default"; 3307 pinctrl-0 = <&sai0m0_lrck 3308 &sai0m0_sclk 3309 &sai0m0_sdi0 3310 &sai0m0_sdi1 3311 &sai0m0_sdi2 3312 &sai0m0_sdi3 3313 &sai0m0_sdo0 3314 &sai0m0_sdo1 3315 &sai0m0_sdo2 3316 &sai0m0_sdo3>; 3317 #sound-dai-cells = <0>; 3318 sound-name-prefix = "SAI0"; 3319 status = "disabled"; 3320 }; 3321 3322 sai1: sai@2a610000 { 3323 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 3324 reg = <0x0 0x2a610000 0x0 0x1000>; 3325 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 3326 clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>; 3327 clock-names = "mclk", "hclk"; 3328 dmas = <&dmac0 2>, <&dmac0 3>; 3329 dma-names = "tx", "rx"; 3330 power-domains = <&power RK3576_PD_AUDIO>; 3331 resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; 3332 reset-names = "m", "h"; 3333 pinctrl-names = "default"; 3334 pinctrl-0 = <&sai1m0_lrck 3335 &sai1m0_sclk 3336 &sai1m0_sdi0 3337 &sai1m0_sdo0 3338 &sai1m0_sdo1 3339 &sai1m0_sdo2 3340 &sai1m0_sdo3>; 3341 #sound-dai-cells = <0>; 3342 sound-name-prefix = "SAI1"; 3343 status = "disabled"; 3344 }; 3345 3346 sai2: sai@2a620000 { 3347 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 3348 reg = <0x0 0x2a620000 0x0 0x1000>; 3349 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 3350 clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>; 3351 clock-names = "mclk", "hclk"; 3352 dmas = <&dmac1 0>, <&dmac1 1>; 3353 dma-names = "tx", "rx"; 3354 power-domains = <&power RK3576_PD_AUDIO>; 3355 resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; 3356 reset-names = "m", "h"; 3357 pinctrl-names = "default"; 3358 pinctrl-0 = <&sai2m0_lrck 3359 &sai2m0_sclk 3360 &sai2m0_sdi 3361 &sai2m0_sdo>; 3362 #sound-dai-cells = <0>; 3363 sound-name-prefix = "SAI2"; 3364 status = "disabled"; 3365 }; 3366 3367 sai3: sai@2a630000 { 3368 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 3369 reg = <0x0 0x2a630000 0x0 0x1000>; 3370 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 3371 clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>; 3372 clock-names = "mclk", "hclk"; 3373 dmas = <&dmac1 2>, <&dmac1 3>; 3374 dma-names = "tx", "rx"; 3375 power-domains = <&power RK3576_PD_AUDIO>; 3376 resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>; 3377 reset-names = "m", "h"; 3378 pinctrl-names = "default"; 3379 pinctrl-0 = <&sai3m0_lrck 3380 &sai3m0_sclk 3381 &sai3m0_sdi 3382 &sai3m0_sdo>; 3383 #sound-dai-cells = <0>; 3384 sound-name-prefix = "SAI3"; 3385 status = "disabled"; 3386 }; 3387 3388 sai4: sai@2a640000 { 3389 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 3390 reg = <0x0 0x2a640000 0x0 0x1000>; 3391 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 3392 clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>; 3393 clock-names = "mclk", "hclk"; 3394 dmas = <&dmac2 0>, <&dmac2 1>; 3395 dma-names = "tx", "rx"; 3396 power-domains = <&power RK3576_PD_AUDIO>; 3397 resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>; 3398 reset-names = "m", "h"; 3399 pinctrl-names = "default"; 3400 pinctrl-0 = <&sai4m0_lrck 3401 &sai4m0_sclk 3402 &sai4m0_sdi 3403 &sai4m0_sdo>; 3404 #sound-dai-cells = <0>; 3405 sound-name-prefix = "SAI4"; 3406 status = "disabled"; 3407 }; 3408 3409 spdif_rx0: spdif-rx@2a650000 { 3410 compatible = "rockchip,rk3576-spdifrx", "rockchip,rk3308-spdifrx"; 3411 reg = <0x0 0x2a650000 0x0 0x1000>; 3412 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 3413 clocks = <&cru MCLK_SPDIF_RX0>, <&cru HCLK_SPDIF_RX0>; 3414 clock-names = "mclk", "hclk"; 3415 dmas = <&dmac1 8>; 3416 dma-names = "rx"; 3417 power-domains = <&power RK3576_PD_AUDIO>; 3418 resets = <&cru SRST_M_SPDIF_RX0>; 3419 reset-names = "spdifrx-m"; 3420 pinctrl-names = "default"; 3421 pinctrl-0 = <&spdifm0_rx0>; 3422 status = "disabled"; 3423 }; 3424 3425 spdif_rx1: spdif-rx@2a660000 { 3426 compatible = "rockchip,rk3576-spdifrx", "rockchip,rk3308-spdifrx"; 3427 reg = <0x0 0x2a660000 0x0 0x1000>; 3428 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 3429 clocks = <&cru MCLK_SPDIF_RX1>, <&cru HCLK_SPDIF_RX1>; 3430 clock-names = "mclk", "hclk"; 3431 dmas = <&dmac2 16>; 3432 dma-names = "rx"; 3433 power-domains = <&power RK3576_PD_AUDIO>; 3434 resets = <&cru SRST_M_SPDIF_RX1>; 3435 reset-names = "spdifrx-m"; 3436 pinctrl-names = "default"; 3437 pinctrl-0 = <&spdifm0_rx1>; 3438 status = "disabled"; 3439 }; 3440 3441 spdif_tx0: spdif-tx@2a670000 { 3442 compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; 3443 reg = <0x0 0x2a670000 0x0 0x1000>; 3444 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 3445 clocks = <&cru MCLK_SPDIF_TX0>, <&cru HCLK_SPDIF_TX0>; 3446 clock-names = "mclk", "hclk"; 3447 dmas = <&dmac0 5>; 3448 dma-names = "tx"; 3449 power-domains = <&power RK3576_PD_AUDIO>; 3450 pinctrl-names = "default"; 3451 pinctrl-0 = <&spdifm0_tx0>; 3452 #sound-dai-cells = <0>; 3453 status = "disabled"; 3454 }; 3455 3456 spdif_tx1: spdif-tx@2a680000 { 3457 compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; 3458 reg = <0x0 0x2a680000 0x0 0x1000>; 3459 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 3460 clocks = <&cru MCLK_SPDIF_TX1>, <&cru HCLK_SPDIF_TX1>; 3461 clock-names = "mclk", "hclk"; 3462 dmas = <&dmac1 5>; 3463 dma-names = "tx"; 3464 power-domains = <&power RK3576_PD_AUDIO>; 3465 pinctrl-names = "default"; 3466 pinctrl-0 = <&spdifm0_tx1>; 3467 #sound-dai-cells = <0>; 3468 status = "disabled"; 3469 }; 3470 3471 acdcdig_dsm: acdcdig-dsm@2a6d0000 { 3472 compatible = "rockchip,rk3576-dsm"; 3473 reg = <0x0 0x2a6d0000 0x0 0x1000>; 3474 clocks = <&cru MCLK_ACDCDIG_DSM>, <&cru HCLK_ACDCDIG_DSM>; 3475 clock-names = "dac", "pclk"; 3476 resets = <&cru SRST_M_ACDCDIG_DSM>; 3477 reset-names = "reset" ; 3478 rockchip,grf = <&sys_grf>; 3479 power-domains = <&power RK3576_PD_AUDIO>; 3480 pinctrl-names = "default"; 3481 pinctrl-0 = <&dsm_audm0_ln 3482 &dsm_audm0_lp 3483 &dsm_audm0_rn 3484 &dsm_audm0_rp>; 3485 #sound-dai-cells = <0>; 3486 status = "disabled"; 3487 }; 3488 3489 pdm1: pdm@2a6e0000 { 3490 compatible = "rockchip,rk3576-pdm"; 3491 reg = <0x0 0x2a6e0000 0x0 0x1000>; 3492 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 3493 clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>, <&cru CLK_PDM1_OUT>; 3494 clock-names = "pdm_clk", "pdm_hclk", "pdm_clk_out"; 3495 assigned-clocks = <&cru MCLK_PDM1>; 3496 assigned-clock-parents = <&cru PLL_AUPLL>; 3497 dmas = <&dmac1 4>; 3498 dma-names = "rx"; 3499 pinctrl-names = "default"; 3500 pinctrl-0 = <&pdm1m0_clk0 3501 &pdm1m0_clk1 3502 &pdm1m0_sdi0 3503 &pdm1m0_sdi1 3504 &pdm1m0_sdi2 3505 &pdm1m0_sdi3>; 3506 power-domains = <&power RK3576_PD_AUDIO>; 3507 #sound-dai-cells = <0>; 3508 sound-name-prefix = "PDM1"; 3509 status = "disabled"; 3510 }; 3511 3512 gic: interrupt-controller@2a701000 { 3513 compatible = "arm,gic-400"; 3514 #interrupt-cells = <3>; 3515 #address-cells = <2>; 3516 #size-cells = <2>; 3517 ranges; 3518 interrupt-controller; 3519 3520 reg = <0x0 0x2a701000 0 0x10000>, 3521 <0x0 0x2a702000 0 0x10000>, 3522 <0x0 0x2a704000 0 0x10000>, 3523 <0x0 0x2a706000 0 0x10000>; 3524 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3525 }; 3526 3527 hwlock: hwspinlock@2ab00000 { 3528 compatible = "rockchip,hwspinlock"; 3529 reg = <0x0 0x2ab00000 0x0 0x100>; 3530 #hwlock-cells = <1>; 3531 status = "disabled"; 3532 }; 3533 3534 dmac0: dma-controller@2ab90000 { 3535 compatible = "arm,pl330", "arm,primecell"; 3536 reg = <0x0 0x2ab90000 0x0 0x4000>; 3537 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3539 clocks = <&cru ACLK_DMAC0>; 3540 clock-names = "apb_pclk"; 3541 #dma-cells = <1>; 3542 arm,pl330-periph-burst; 3543 }; 3544 3545 dmac1: dma-controller@2abb0000 { 3546 compatible = "arm,pl330", "arm,primecell"; 3547 reg = <0x0 0x2abb0000 0x0 0x4000>; 3548 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 3549 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3550 clocks = <&cru ACLK_DMAC1>; 3551 clock-names = "apb_pclk"; 3552 #dma-cells = <1>; 3553 arm,pl330-periph-burst; 3554 }; 3555 3556 dmac2: dma-controller@2abd0000 { 3557 compatible = "arm,pl330", "arm,primecell"; 3558 reg = <0x0 0x2abd0000 0x0 0x4000>; 3559 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 3560 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3561 clocks = <&cru ACLK_DMAC2>; 3562 clock-names = "apb_pclk"; 3563 #dma-cells = <1>; 3564 arm,pl330-periph-burst; 3565 }; 3566 3567 i3c0: i3c-master@2abe0000 { 3568 compatible = "rockchip,i3c-master"; 3569 reg = <0x0 0x2abe0000 0x0 0x1000>; 3570 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 3571 #address-cells = <3>; 3572 #size-cells = <0>; 3573 clocks = <&cru HCLK_I3C0>, <&cru CLK_I3C0>; 3574 clock-names = "hclk", "i3c"; 3575 dmas = <&dmac0 22>, <&dmac0 23>; 3576 dma-names = "rx", "tx"; 3577 pinctrl-names = "default"; 3578 pinctrl-0 = <&i3c0m0_xfer &i3c0_sdam0_pu>; 3579 status = "disabled"; 3580 }; 3581 3582 i3c1: i3c-master@2abf0000 { 3583 compatible = "rockchip,i3c-master"; 3584 reg = <0x0 0x2abf0000 0x0 0x1000>; 3585 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 3586 #address-cells = <3>; 3587 #size-cells = <0>; 3588 clocks = <&cru HCLK_I3C1>, <&cru CLK_I3C1>; 3589 clock-names = "hclk", "i3c"; 3590 dmas = <&dmac1 22>, <&dmac1 23>; 3591 dma-names = "rx", "tx"; 3592 pinctrl-names = "default"; 3593 pinctrl-0 = <&i3c1m0_xfer &i3c1_sdam0_pu>; 3594 status = "disabled"; 3595 }; 3596 3597 can0: can@2ac00000 { 3598 compatible = "rockchip,rk3576-canfd"; 3599 reg = <0x0 0x2ac00000 0x0 0x1000>; 3600 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 3601 clocks = <&cru CLK_CAN0>, <&cru HCLK_CAN0>; 3602 clock-names = "baudclk", "apb_pclk"; 3603 resets = <&cru SRST_CAN0>, <&cru SRST_H_CAN0>; 3604 reset-names = "can", "can-apb"; 3605 dmas = <&dmac0 20>; 3606 dma-names = "rx"; 3607 status = "disabled"; 3608 }; 3609 3610 can1: can@2ac10000 { 3611 compatible = "rockchip,rk3576-canfd"; 3612 reg = <0x0 0x2ac10000 0x0 0x1000>; 3613 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 3614 clocks = <&cru CLK_CAN1>, <&cru HCLK_CAN1>; 3615 clock-names = "baudclk", "apb_pclk"; 3616 resets = <&cru SRST_CAN1>, <&cru SRST_H_CAN1>; 3617 reset-names = "can", "can-apb"; 3618 dmas = <&dmac1 21>; 3619 dma-names = "rx"; 3620 status = "disabled"; 3621 }; 3622 3623 hw_decompress: decompress@2ac30000 { 3624 compatible = "rockchip,hw-decompress"; 3625 reg = <0x0 0x2ac30000 0x0 0x1000>; 3626 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 3627 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 3628 clock-names = "aclk", "dclk", "pclk"; 3629 resets = <&cru SRST_D_DECOM>; 3630 reset-names = "dresetn"; 3631 status = "disabled"; 3632 }; 3633 3634 i2c1: i2c@2ac40000 { 3635 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3636 reg = <0x0 0x2ac40000 0x0 0x1000>; 3637 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 3638 clock-names = "i2c", "pclk"; 3639 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 3640 pinctrl-names = "default"; 3641 pinctrl-0 = <&i2c1m0_xfer>; 3642 resets = <&cru SRST_I2C1>, <&cru SRST_P_I2C1>; 3643 reset-names = "i2c", "apb"; 3644 #address-cells = <1>; 3645 #size-cells = <0>; 3646 status = "disabled"; 3647 }; 3648 3649 i2c2: i2c@2ac50000 { 3650 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3651 reg = <0x0 0x2ac50000 0x0 0x1000>; 3652 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 3653 clock-names = "i2c", "pclk"; 3654 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 3655 pinctrl-names = "default"; 3656 pinctrl-0 = <&i2c2m0_xfer>; 3657 resets = <&cru SRST_I2C2>, <&cru SRST_P_I2C2>; 3658 reset-names = "i2c", "apb"; 3659 #address-cells = <1>; 3660 #size-cells = <0>; 3661 status = "disabled"; 3662 }; 3663 3664 i2c3: i2c@2ac60000 { 3665 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3666 reg = <0x0 0x2ac60000 0x0 0x1000>; 3667 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 3668 clock-names = "i2c", "pclk"; 3669 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 3670 pinctrl-names = "default"; 3671 pinctrl-0 = <&i2c3m0_xfer>; 3672 resets = <&cru SRST_I2C3>, <&cru SRST_P_I2C3>; 3673 reset-names = "i2c", "apb"; 3674 #address-cells = <1>; 3675 #size-cells = <0>; 3676 status = "disabled"; 3677 }; 3678 3679 i2c4: i2c@2ac70000 { 3680 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3681 reg = <0x0 0x2ac70000 0x0 0x1000>; 3682 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 3683 clock-names = "i2c", "pclk"; 3684 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 3685 pinctrl-names = "default"; 3686 pinctrl-0 = <&i2c4m0_xfer>; 3687 resets = <&cru SRST_I2C4>, <&cru SRST_P_I2C4>; 3688 reset-names = "i2c", "apb"; 3689 #address-cells = <1>; 3690 #size-cells = <0>; 3691 status = "disabled"; 3692 }; 3693 3694 i2c5: i2c@2ac80000 { 3695 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3696 reg = <0x0 0x2ac80000 0x0 0x1000>; 3697 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 3698 clock-names = "i2c", "pclk"; 3699 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 3700 pinctrl-names = "default"; 3701 pinctrl-0 = <&i2c5m0_xfer>; 3702 resets = <&cru SRST_I2C5>, <&cru SRST_P_I2C5>; 3703 reset-names = "i2c", "apb"; 3704 #address-cells = <1>; 3705 #size-cells = <0>; 3706 status = "disabled"; 3707 }; 3708 3709 3710 i2c6: i2c@2ac90000 { 3711 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3712 reg = <0x0 0x2ac90000 0x0 0x1000>; 3713 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 3714 clock-names = "i2c", "pclk"; 3715 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 3716 pinctrl-names = "default"; 3717 pinctrl-0 = <&i2c6m0_xfer>; 3718 resets = <&cru SRST_I2C6>, <&cru SRST_P_I2C6>; 3719 reset-names = "i2c", "apb"; 3720 #address-cells = <1>; 3721 #size-cells = <0>; 3722 status = "disabled"; 3723 }; 3724 3725 i2c7: i2c@2aca0000 { 3726 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3727 reg = <0x0 0x2aca0000 0x0 0x1000>; 3728 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 3729 clock-names = "i2c", "pclk"; 3730 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3731 pinctrl-names = "default"; 3732 pinctrl-0 = <&i2c7m0_xfer>; 3733 resets = <&cru SRST_I2C7>, <&cru SRST_P_I2C7>; 3734 reset-names = "i2c", "apb"; 3735 #address-cells = <1>; 3736 #size-cells = <0>; 3737 status = "disabled"; 3738 }; 3739 3740 i2c8: i2c@2acb0000 { 3741 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3742 reg = <0x0 0x2acb0000 0x0 0x1000>; 3743 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 3744 clock-names = "i2c", "pclk"; 3745 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 3746 pinctrl-names = "default"; 3747 pinctrl-0 = <&i2c8m0_xfer>; 3748 resets = <&cru SRST_I2C8>, <&cru SRST_P_I2C8>; 3749 reset-names = "i2c", "apb"; 3750 #address-cells = <1>; 3751 #size-cells = <0>; 3752 status = "disabled"; 3753 }; 3754 3755 rktimer: timer@2acc0000 { 3756 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer"; 3757 reg = <0x0 0x2acc0000 0x0 0x20>; 3758 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 3759 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>; 3760 clock-names = "pclk", "timer"; 3761 }; 3762 3763 wdt: watchdog@2ace0000 { 3764 compatible = "snps,dw-wdt"; 3765 reg = <0x0 0x2ace0000 0x0 0x100>; 3766 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 3767 clock-names = "tclk", "pclk"; 3768 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 3769 status = "disabled"; 3770 }; 3771 3772 spi0: spi@2acf0000 { 3773 compatible = "rockchip,rk3066-spi"; 3774 reg = <0x0 0x2acf0000 0x0 0x1000>; 3775 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 3776 #address-cells = <1>; 3777 #size-cells = <0>; 3778 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 3779 clock-names = "spiclk", "apb_pclk"; 3780 dmas = <&dmac0 14>, <&dmac0 15>; 3781 dma-names = "tx", "rx"; 3782 pinctrl-names = "default"; 3783 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 3784 num-cs = <2>; 3785 status = "disabled"; 3786 }; 3787 3788 spi1: spi@2ad00000 { 3789 compatible = "rockchip,rk3066-spi"; 3790 reg = <0x0 0x2ad00000 0x0 0x1000>; 3791 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 3792 #address-cells = <1>; 3793 #size-cells = <0>; 3794 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 3795 clock-names = "spiclk", "apb_pclk"; 3796 dmas = <&dmac0 16>, <&dmac0 17>; 3797 dma-names = "tx", "rx"; 3798 pinctrl-names = "default"; 3799 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 3800 num-cs = <2>; 3801 status = "disabled"; 3802 }; 3803 3804 spi2: spi@2ad10000 { 3805 compatible = "rockchip,rk3066-spi"; 3806 reg = <0x0 0x2ad10000 0x0 0x1000>; 3807 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 3808 #address-cells = <1>; 3809 #size-cells = <0>; 3810 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 3811 clock-names = "spiclk", "apb_pclk"; 3812 dmas = <&dmac1 15>, <&dmac1 16>; 3813 dma-names = "tx", "rx"; 3814 pinctrl-names = "default"; 3815 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 3816 num-cs = <2>; 3817 status = "disabled"; 3818 }; 3819 3820 spi3: spi@2ad20000 { 3821 compatible = "rockchip,rk3066-spi"; 3822 reg = <0x0 0x2ad20000 0x0 0x1000>; 3823 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 3824 #address-cells = <1>; 3825 #size-cells = <0>; 3826 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 3827 clock-names = "spiclk", "apb_pclk"; 3828 dmas = <&dmac1 17>, <&dmac1 18>; 3829 dma-names = "tx", "rx"; 3830 pinctrl-names = "default"; 3831 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>; 3832 num-cs = <2>; 3833 status = "disabled"; 3834 }; 3835 3836 spi4: spi@2ad30000 { 3837 compatible = "rockchip,rk3066-spi"; 3838 reg = <0x0 0x2ad30000 0x0 0x1000>; 3839 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 3840 #address-cells = <1>; 3841 #size-cells = <0>; 3842 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 3843 clock-names = "spiclk", "apb_pclk"; 3844 dmas = <&dmac2 12>, <&dmac2 13>; 3845 dma-names = "tx", "rx"; 3846 pinctrl-names = "default"; 3847 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>; 3848 num-cs = <2>; 3849 status = "disabled"; 3850 }; 3851 3852 uart0: serial@2ad40000 { 3853 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3854 reg = <0x0 0x2ad40000 0x0 0x100>; 3855 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 3856 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 3857 clock-names = "baudclk", "apb_pclk"; 3858 reg-shift = <2>; 3859 reg-io-width = <4>; 3860 dmas = <&dmac0 6>, <&dmac0 7>; 3861 pinctrl-names = "default"; 3862 pinctrl-0 = <&uart0m0_xfer>; 3863 status = "disabled"; 3864 }; 3865 3866 uart2: serial@2ad50000 { 3867 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3868 reg = <0x0 0x2ad50000 0x0 0x100>; 3869 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 3870 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 3871 clock-names = "baudclk", "apb_pclk"; 3872 reg-shift = <2>; 3873 reg-io-width = <4>; 3874 dmas = <&dmac0 10>, <&dmac0 11>; 3875 pinctrl-names = "default"; 3876 pinctrl-0 = <&uart2m0_xfer>; 3877 status = "disabled"; 3878 }; 3879 3880 uart3: serial@2ad60000 { 3881 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3882 reg = <0x0 0x2ad60000 0x0 0x100>; 3883 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 3884 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 3885 clock-names = "baudclk", "apb_pclk"; 3886 reg-shift = <2>; 3887 reg-io-width = <4>; 3888 dmas = <&dmac0 12>, <&dmac0 13>; 3889 pinctrl-names = "default"; 3890 pinctrl-0 = <&uart3m0_xfer>; 3891 status = "disabled"; 3892 }; 3893 3894 uart4: serial@2ad70000 { 3895 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3896 reg = <0x0 0x2ad70000 0x0 0x100>; 3897 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 3898 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 3899 clock-names = "baudclk", "apb_pclk"; 3900 reg-shift = <2>; 3901 reg-io-width = <4>; 3902 dmas = <&dmac1 9>, <&dmac1 10>; 3903 pinctrl-names = "default"; 3904 pinctrl-0 = <&uart4m0_xfer>; 3905 status = "disabled"; 3906 }; 3907 3908 uart5: serial@2ad80000 { 3909 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3910 reg = <0x0 0x2ad80000 0x0 0x100>; 3911 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3912 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 3913 clock-names = "baudclk", "apb_pclk"; 3914 reg-shift = <2>; 3915 reg-io-width = <4>; 3916 dmas = <&dmac1 11>, <&dmac1 12>; 3917 pinctrl-names = "default"; 3918 pinctrl-0 = <&uart5m0_xfer>; 3919 status = "disabled"; 3920 }; 3921 3922 uart6: serial@2ad90000 { 3923 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3924 reg = <0x0 0x2ad90000 0x0 0x100>; 3925 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3926 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 3927 clock-names = "baudclk", "apb_pclk"; 3928 reg-shift = <2>; 3929 reg-io-width = <4>; 3930 dmas = <&dmac1 13>, <&dmac1 14>; 3931 pinctrl-names = "default"; 3932 pinctrl-0 = <&uart6m0_xfer>; 3933 status = "disabled"; 3934 }; 3935 3936 uart7: serial@2ada0000 { 3937 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3938 reg = <0x0 0x2ada0000 0x0 0x100>; 3939 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3940 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 3941 clock-names = "baudclk", "apb_pclk"; 3942 reg-shift = <2>; 3943 reg-io-width = <4>; 3944 dmas = <&dmac2 6>, <&dmac2 7>; 3945 pinctrl-names = "default"; 3946 pinctrl-0 = <&uart7m0_xfer>; 3947 status = "disabled"; 3948 }; 3949 3950 uart8: serial@2adb0000 { 3951 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3952 reg = <0x0 0x2adb0000 0x0 0x100>; 3953 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 3954 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 3955 clock-names = "baudclk", "apb_pclk"; 3956 reg-shift = <2>; 3957 reg-io-width = <4>; 3958 dmas = <&dmac2 8>, <&dmac2 9>; 3959 pinctrl-names = "default"; 3960 pinctrl-0 = <&uart8m0_xfer>; 3961 status = "disabled"; 3962 }; 3963 3964 uart9: serial@2adc0000 { 3965 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3966 reg = <0x0 0x2adc0000 0x0 0x100>; 3967 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 3968 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 3969 clock-names = "baudclk", "apb_pclk"; 3970 reg-shift = <2>; 3971 reg-io-width = <4>; 3972 dmas = <&dmac2 10>, <&dmac2 11>; 3973 pinctrl-names = "default"; 3974 pinctrl-0 = <&uart9m0_xfer>; 3975 status = "disabled"; 3976 }; 3977 3978 pwm1_6ch_0: pwm@2add0000 { 3979 compatible = "rockchip,rk3576-pwm"; 3980 reg = <0x0 0x2add0000 0x0 0x1000>; 3981 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3982 #pwm-cells = <3>; 3983 pinctrl-names = "active"; 3984 pinctrl-0 = <&pwm1m0_ch0>; 3985 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 3986 clock-names = "pwm", "pclk"; 3987 status = "disabled"; 3988 }; 3989 3990 pwm1_6ch_1: pwm@2add1000 { 3991 compatible = "rockchip,rk3576-pwm"; 3992 reg = <0x0 0x2add1000 0x0 0x1000>; 3993 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3994 #pwm-cells = <3>; 3995 pinctrl-names = "active"; 3996 pinctrl-0 = <&pwm1m0_ch1>; 3997 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 3998 clock-names = "pwm", "pclk"; 3999 status = "disabled"; 4000 }; 4001 4002 pwm1_6ch_2: pwm@2add2000 { 4003 compatible = "rockchip,rk3576-pwm"; 4004 reg = <0x0 0x2add2000 0x0 0x1000>; 4005 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 4006 #pwm-cells = <3>; 4007 pinctrl-names = "active"; 4008 pinctrl-0 = <&pwm1m0_ch2>; 4009 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 4010 clock-names = "pwm", "pclk"; 4011 status = "disabled"; 4012 }; 4013 4014 pwm1_6ch_3: pwm@2add3000 { 4015 compatible = "rockchip,rk3576-pwm"; 4016 reg = <0x0 0x2add3000 0x0 0x1000>; 4017 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 4018 #pwm-cells = <3>; 4019 pinctrl-names = "active"; 4020 pinctrl-0 = <&pwm1m0_ch3>; 4021 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 4022 clock-names = "pwm", "pclk"; 4023 status = "disabled"; 4024 }; 4025 4026 pwm1_6ch_4: pwm@2add4000 { 4027 compatible = "rockchip,rk3576-pwm"; 4028 reg = <0x0 0x2add4000 0x0 0x1000>; 4029 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 4030 #pwm-cells = <3>; 4031 pinctrl-names = "active"; 4032 pinctrl-0 = <&pwm1m0_ch4>; 4033 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 4034 clock-names = "pwm", "pclk"; 4035 status = "disabled"; 4036 }; 4037 4038 pwm1_6ch_5: pwm@2add5000 { 4039 compatible = "rockchip,rk3576-pwm"; 4040 reg = <0x0 0x2add5000 0x0 0x1000>; 4041 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 4042 #pwm-cells = <3>; 4043 pinctrl-names = "active"; 4044 pinctrl-0 = <&pwm1m0_ch5>; 4045 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 4046 clock-names = "pwm", "pclk"; 4047 status = "disabled"; 4048 }; 4049 4050 pwm2_8ch_0: pwm@2ade0000 { 4051 compatible = "rockchip,rk3576-pwm"; 4052 reg = <0x0 0x2ade0000 0x0 0x1000>; 4053 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 4054 #pwm-cells = <3>; 4055 pinctrl-names = "active"; 4056 pinctrl-0 = <&pwm2m0_ch0>; 4057 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4058 clock-names = "pwm", "pclk"; 4059 status = "disabled"; 4060 }; 4061 4062 pwm2_8ch_1: pwm@2ade1000 { 4063 compatible = "rockchip,rk3576-pwm"; 4064 reg = <0x0 0x2ade1000 0x0 0x1000>; 4065 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 4066 #pwm-cells = <3>; 4067 pinctrl-names = "active"; 4068 pinctrl-0 = <&pwm2m0_ch1>; 4069 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4070 clock-names = "pwm", "pclk"; 4071 status = "disabled"; 4072 }; 4073 4074 pwm2_8ch_2: pwm@2ade2000 { 4075 compatible = "rockchip,rk3576-pwm"; 4076 reg = <0x0 0x2ade2000 0x0 0x1000>; 4077 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 4078 #pwm-cells = <3>; 4079 pinctrl-names = "active"; 4080 pinctrl-0 = <&pwm2m0_ch2>; 4081 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4082 clock-names = "pwm", "pclk"; 4083 status = "disabled"; 4084 }; 4085 4086 pwm2_8ch_3: pwm@2ade3000 { 4087 compatible = "rockchip,rk3576-pwm"; 4088 reg = <0x0 0x2ade3000 0x0 0x1000>; 4089 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 4090 #pwm-cells = <3>; 4091 pinctrl-names = "active"; 4092 pinctrl-0 = <&pwm2m0_ch3>; 4093 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4094 clock-names = "pwm", "pclk"; 4095 status = "disabled"; 4096 }; 4097 4098 pwm2_8ch_4: pwm@2ade4000 { 4099 compatible = "rockchip,rk3576-pwm"; 4100 reg = <0x0 0x2ade4000 0x0 0x1000>; 4101 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 4102 #pwm-cells = <3>; 4103 pinctrl-names = "active"; 4104 pinctrl-0 = <&pwm2m0_ch4>; 4105 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4106 clock-names = "pwm", "pclk"; 4107 status = "disabled"; 4108 }; 4109 4110 pwm2_8ch_5: pwm@2ade5000 { 4111 compatible = "rockchip,rk3576-pwm"; 4112 reg = <0x0 0x2ade5000 0x0 0x1000>; 4113 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 4114 #pwm-cells = <3>; 4115 pinctrl-names = "active"; 4116 pinctrl-0 = <&pwm2m0_ch5>; 4117 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4118 clock-names = "pwm", "pclk"; 4119 status = "disabled"; 4120 }; 4121 4122 pwm2_8ch_6: pwm@2ade6000 { 4123 compatible = "rockchip,rk3576-pwm"; 4124 reg = <0x0 0x2ade6000 0x0 0x1000>; 4125 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 4126 #pwm-cells = <3>; 4127 pinctrl-names = "active"; 4128 pinctrl-0 = <&pwm2m0_ch6>; 4129 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4130 clock-names = "pwm", "pclk"; 4131 status = "disabled"; 4132 }; 4133 4134 pwm2_8ch_7: pwm@2ade7000 { 4135 compatible = "rockchip,rk3576-pwm"; 4136 reg = <0x0 0x2ade7000 0x0 0x1000>; 4137 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 4138 #pwm-cells = <3>; 4139 pinctrl-names = "active"; 4140 pinctrl-0 = <&pwm2m0_ch7>; 4141 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4142 clock-names = "pwm", "pclk"; 4143 status = "disabled"; 4144 }; 4145 4146 saradc: adc@2ae00000 { 4147 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc"; 4148 reg = <0x0 0x2ae00000 0x0 0x10000>; 4149 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 4150 #io-channel-cells = <1>; 4151 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 4152 clock-names = "saradc", "apb_pclk"; 4153 resets = <&cru SRST_P_SARADC>; 4154 reset-names = "saradc-apb"; 4155 status = "disabled"; 4156 }; 4157 4158 mailbox0: mailbox@2ae50000 { 4159 compatible = "rockchip,rk3576-mailbox"; 4160 reg = <0x0 0x2ae50000 0x0 0x20>; 4161 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 4162 clocks = <&cru PCLK_MAILBOX0>; 4163 clock-names = "pclk_mailbox"; 4164 #mbox-cells = <1>; 4165 status = "disabled"; 4166 }; 4167 4168 mailbox1: mailbox@2ae51000 { 4169 compatible = "rockchip,rk3576-mailbox"; 4170 reg = <0x0 0x2ae51000 0x0 0x20>; 4171 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 4172 clocks = <&cru PCLK_MAILBOX0>; 4173 clock-names = "pclk_mailbox"; 4174 #mbox-cells = <1>; 4175 status = "disabled"; 4176 }; 4177 4178 mailbox2: mailbox@2ae52000 { 4179 compatible = "rockchip,rk3576-mailbox"; 4180 reg = <0x0 0x2ae52000 0x0 0x20>; 4181 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 4182 clocks = <&cru PCLK_MAILBOX0>; 4183 clock-names = "pclk_mailbox"; 4184 #mbox-cells = <1>; 4185 status = "disabled"; 4186 }; 4187 4188 mailbox3: mailbox@2ae53000 { 4189 compatible = "rockchip,rk3576-mailbox"; 4190 reg = <0x0 0x2ae53000 0x0 0x20>; 4191 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 4192 clocks = <&cru PCLK_MAILBOX0>; 4193 clock-names = "pclk_mailbox"; 4194 #mbox-cells = <1>; 4195 status = "disabled"; 4196 }; 4197 4198 mailbox4: mailbox@2ae54000 { 4199 compatible = "rockchip,rk3576-mailbox"; 4200 reg = <0x0 0x2ae54000 0x0 0x20>; 4201 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 4202 clocks = <&cru PCLK_MAILBOX0>; 4203 clock-names = "pclk_mailbox"; 4204 #mbox-cells = <1>; 4205 status = "disabled"; 4206 }; 4207 4208 mailbox5: mailbox@2ae55000 { 4209 compatible = "rockchip,rk3576-mailbox"; 4210 reg = <0x0 0x2ae55000 0x0 0x20>; 4211 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 4212 clocks = <&cru PCLK_MAILBOX0>; 4213 clock-names = "pclk_mailbox"; 4214 #mbox-cells = <1>; 4215 status = "disabled"; 4216 }; 4217 4218 mailbox6: mailbox@2ae56000 { 4219 compatible = "rockchip,rk3576-mailbox"; 4220 reg = <0x0 0x2ae56000 0x0 0x20>; 4221 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 4222 clocks = <&cru PCLK_MAILBOX0>; 4223 clock-names = "pclk_mailbox"; 4224 #mbox-cells = <1>; 4225 status = "disabled"; 4226 }; 4227 4228 mailbox7: mailbox@2ae57000 { 4229 compatible = "rockchip,rk3576-mailbox"; 4230 reg = <0x0 0x2ae57000 0x0 0x20>; 4231 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 4232 clocks = <&cru PCLK_MAILBOX0>; 4233 clock-names = "pclk_mailbox"; 4234 #mbox-cells = <1>; 4235 status = "disabled"; 4236 }; 4237 4238 mailbox8: mailbox@2ae58000 { 4239 compatible = "rockchip,rk3576-mailbox"; 4240 reg = <0x0 0x2ae58000 0x0 0x20>; 4241 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4242 clocks = <&cru PCLK_MAILBOX0>; 4243 clock-names = "pclk_mailbox"; 4244 #mbox-cells = <1>; 4245 status = "disabled"; 4246 }; 4247 4248 mailbox9: mailbox@2ae59000 { 4249 compatible = "rockchip,rk3576-mailbox"; 4250 reg = <0x0 0x2ae59000 0x0 0x20>; 4251 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 4252 clocks = <&cru PCLK_MAILBOX0>; 4253 clock-names = "pclk_mailbox"; 4254 #mbox-cells = <1>; 4255 status = "disabled"; 4256 }; 4257 4258 mailbox10: mailbox@2ae5a000 { 4259 compatible = "rockchip,rk3576-mailbox"; 4260 reg = <0x0 0x2ae5a000 0x0 0x20>; 4261 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 4262 clocks = <&cru PCLK_MAILBOX0>; 4263 clock-names = "pclk_mailbox"; 4264 #mbox-cells = <1>; 4265 status = "disabled"; 4266 }; 4267 4268 mailbox11: mailbox@2ae5b000 { 4269 compatible = "rockchip,rk3576-mailbox"; 4270 reg = <0x0 0x2ae5b000 0x0 0x20>; 4271 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 4272 clocks = <&cru PCLK_MAILBOX0>; 4273 clock-names = "pclk_mailbox"; 4274 #mbox-cells = <1>; 4275 status = "disabled"; 4276 }; 4277 4278 mailbox12: mailbox@2ae5c000 { 4279 compatible = "rockchip,rk3576-mailbox"; 4280 reg = <0x0 0x2ae5c000 0x0 0x20>; 4281 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 4282 clocks = <&cru PCLK_MAILBOX0>; 4283 clock-names = "pclk_mailbox"; 4284 #mbox-cells = <1>; 4285 status = "disabled"; 4286 }; 4287 4288 mailbox13: mailbox@2ae5d000 { 4289 compatible = "rockchip,rk3576-mailbox"; 4290 reg = <0x0 0x2ae5d000 0x0 0x20>; 4291 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4292 clocks = <&cru PCLK_MAILBOX0>; 4293 clock-names = "pclk_mailbox"; 4294 #mbox-cells = <1>; 4295 status = "disabled"; 4296 }; 4297 4298 tsadc: tsadc@2ae70000 { 4299 compatible = "rockchip,rk3576-tsadc"; 4300 reg = <0x0 0x2ae70000 0x0 0x400>; 4301 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 4302 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 4303 clock-names = "tsadc", "apb_pclk"; 4304 assigned-clocks = <&cru CLK_TSADC>; 4305 assigned-clock-rates = <2000000>; 4306 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; 4307 reset-names = "tsadc", "tsadc-apb"; 4308 #thermal-sensor-cells = <1>; 4309 rockchip,hw-tshut-temp = <120000>; 4310 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 4311 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 4312 status = "disabled"; 4313 }; 4314 4315 i2c9: i2c@2ae80000 { 4316 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 4317 reg = <0x0 0x2ae80000 0x0 0x1000>; 4318 clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>; 4319 clock-names = "i2c", "pclk"; 4320 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 4321 pinctrl-names = "default"; 4322 pinctrl-0 = <&i2c9m0_xfer>; 4323 resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>; 4324 reset-names = "i2c", "apb"; 4325 #address-cells = <1>; 4326 #size-cells = <0>; 4327 status = "disabled"; 4328 }; 4329 4330 uart10: serial@2afc0000 { 4331 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 4332 reg = <0x0 0x2afc0000 0x0 0x100>; 4333 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 4334 clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>; 4335 clock-names = "baudclk", "apb_pclk"; 4336 reg-shift = <2>; 4337 reg-io-width = <4>; 4338 dmas = <&dmac2 21>, <&dmac2 22>; 4339 pinctrl-names = "default"; 4340 pinctrl-0 = <&uart10m0_xfer>; 4341 status = "disabled"; 4342 }; 4343 4344 uart11: serial@2afd0000 { 4345 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 4346 reg = <0x0 0x2afd0000 0x0 0x100>; 4347 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 4348 clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>; 4349 clock-names = "baudclk", "apb_pclk"; 4350 reg-shift = <2>; 4351 reg-io-width = <4>; 4352 dmas = <&dmac2 23>, <&dmac2 24>; 4353 pinctrl-names = "default"; 4354 pinctrl-0 = <&uart11m0_xfer>; 4355 status = "disabled"; 4356 }; 4357 4358 hdptxphy: phy@2b000000 { 4359 compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; 4360 reg = <0x0 0x2b000000 0x0 0x2000>; 4361 clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_PMUPHY_ROOT>; 4362 clock-names = "ref", "apb"; 4363 resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, 4364 <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; 4365 reset-names = "apb", "init", "cmn", "lane"; 4366 rockchip,grf = <&hdptxphy_grf>; 4367 #phy-cells = <0>; 4368 status = "disabled"; 4369 }; 4370 4371 hdptxphy_hdmi: hdmiphy@2b000000 { 4372 compatible = "rockchip,rk3576-hdptx-phy-hdmi", "rockchip,rk3588-hdptx-phy-hdmi"; 4373 reg = <0x0 0x2b000000 0x0 0x2000>; 4374 clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_PMUPHY_ROOT>; 4375 clock-names = "ref", "apb"; 4376 clock-output-names = "clk_hdmiphy_pixel0"; 4377 #clock-cells = <0>; 4378 resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, 4379 <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; 4380 reset-names = "apb", "init", "cmn", "lane"; 4381 rockchip,grf = <&hdptxphy_grf>; 4382 #phy-cells = <0>; 4383 status = "disabled"; 4384 }; 4385 4386 usbdp_phy: phy@2b010000 { 4387 compatible = "rockchip,rk3576-usbdp-phy"; 4388 reg = <0x0 0x2b010000 0x0 0x10000>; 4389 rockchip,u2phy-grf = <&usb2phy_grf>; 4390 rockchip,usb-grf = <&usb_grf>; 4391 rockchip,usbdpphy-grf = <&usbdpphy_grf>; 4392 rockchip,vo-grf = <&vo1_grf>; 4393 clocks = <&cru CLK_PHY_REF_SRC >, 4394 <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>, 4395 <&cru PCLK_USBDPPHY>; 4396 clock-names = "refclk", "immortal", "pclk"; 4397 resets = <&cru SRST_USBDP_COMBO_PHY_INIT>, 4398 <&cru SRST_USBDP_COMBO_PHY_CMN>, 4399 <&cru SRST_USBDP_COMBO_PHY_LANE>, 4400 <&cru SRST_USBDP_COMBO_PHY_PCS>, 4401 <&cru SRST_P_USBDPPHY>; 4402 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 4403 status = "disabled"; 4404 4405 usbdp_phy_dp: dp-port { 4406 #phy-cells = <0>; 4407 status = "disabled"; 4408 }; 4409 4410 usbdp_phy_u3: u3-port { 4411 #phy-cells = <0>; 4412 status = "disabled"; 4413 }; 4414 }; 4415 4416 mipidcphy0: phy@2b020000 { 4417 compatible = "rockchip,rk3588-mipi-dcphy"; 4418 reg = <0x0 0x2b020000 0x0 0x10000>; 4419 rockchip,grf = <&mipidcphy0_grf>; 4420 clocks = <&cru PCLK_MIPI_DCPHY>; 4421 clock-names = "pclk"; 4422 resets = <&cru SRST_M_MIPI_DCPHY>, 4423 <&cru SRST_P_MIPI_DCPHY>, 4424 <&cru SRST_P_DCPHY_GRF>, 4425 <&cru SRST_S_MIPI_DCPHY>; 4426 reset-names = "m_phy", "apb", "grf", "s_phy"; 4427 #phy-cells = <0>; 4428 status = "okay"; 4429 }; 4430 4431 csi2_dphy0_hw: csi2-dphy0-hw@2b030000 { 4432 compatible = "rockchip,rk3588-csi2-dphy-hw"; 4433 reg = <0x0 0x2b030000 0x0 0x8000>; 4434 clocks = <&cru PCLK_CSIDPHY>; 4435 clock-names = "pclk"; 4436 resets = <&cru SRST_P_CSIPHY>; 4437 reset-names = "srst_p_csiphy"; 4438 rockchip,grf = <&mipidphy0_grf>; 4439 rockchip,sys_grf = <&sys_grf>; 4440 status = "okay"; 4441 }; 4442 4443 combphy0_ps: phy@2b050000 { 4444 compatible = "rockchip,rk3576-naneng-combphy"; 4445 reg = <0x0 0x2b050000 0x0 0x100>; 4446 #phy-cells = <1>; 4447 clocks = <&cru CLK_REF_PCIE0_PHY>, 4448 <&cru PCLK_PCIE2_COMBOPHY0>, 4449 <&cru PCLK_PCIE0>; 4450 clock-names = "refclk", "apbclk", "pipe_clk"; 4451 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>; 4452 assigned-clock-rates = <100000000>; 4453 resets = <&cru SRST_P_PCIE2_COMBOPHY0>, 4454 <&cru SRST_PCIE0_PIPE_PHY>; 4455 reset-names = "combphy-apb", "combphy"; 4456 rockchip,pipe-grf = <&php_grf>; 4457 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 4458 status = "disabled"; 4459 }; 4460 4461 combphy1_psu: phy@2b060000 { 4462 compatible = "rockchip,rk3576-naneng-combphy"; 4463 reg = <0x0 0x2b060000 0x0 0x100>; 4464 #phy-cells = <1>; 4465 clocks = <&cru CLK_REF_PCIE1_PHY>, 4466 <&cru PCLK_PCIE2_COMBOPHY1>, 4467 <&cru PCLK_PCIE1>; 4468 clock-names = "refclk", "apbclk", "pipe_clk"; 4469 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>; 4470 assigned-clock-rates = <100000000>; 4471 resets = <&cru SRST_P_PCIE2_COMBOPHY1>, 4472 <&cru SRST_PCIE1_PIPE_PHY>; 4473 reset-names = "combphy-apb", "combphy"; 4474 rockchip,pipe-grf = <&php_grf>; 4475 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 4476 status = "disabled"; 4477 }; 4478 4479 csi2_dphy1_hw: csi2-dphy1-hw@2b070000 { 4480 compatible = "rockchip,rk3588-csi2-dphy-hw"; 4481 reg = <0x0 0x2b070000 0x0 0x8000>; 4482 clocks = <&cru PCLK_CSIDPHY1>; 4483 clock-names = "pclk"; 4484 resets = <&cru SRST_P_CSIDPHY1>; 4485 reset-names = "srst_p_csiphy1"; 4486 rockchip,grf = <&mipidphy1_grf>; 4487 rockchip,sys_grf = <&sys_grf>; 4488 status = "okay"; 4489 }; 4490 4491 scmi_shmem: scmi-shmem@4010f000 { 4492 compatible = "arm,scmi-shmem"; 4493 reg = <0x0 0x4010f000 0x0 0x100>; 4494 }; 4495 4496 pinctrl: pinctrl { 4497 compatible = "rockchip,rk3576-pinctrl"; 4498 rockchip,grf = <&ioc_grf>; 4499 #address-cells = <2>; 4500 #size-cells = <2>; 4501 ranges; 4502 4503 gpio0: gpio@27320000 { 4504 compatible = "rockchip,gpio-bank"; 4505 reg = <0x0 0x27320000 0x0 0x200>; 4506 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 4507 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 4508 4509 gpio-controller; 4510 #gpio-cells = <2>; 4511 gpio-ranges = <&pinctrl 0 0 32>; 4512 interrupt-controller; 4513 #interrupt-cells = <2>; 4514 }; 4515 4516 gpio1: gpio@2ae10000 { 4517 compatible = "rockchip,gpio-bank"; 4518 reg = <0x0 0x2ae10000 0x0 0x200>; 4519 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 4520 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 4521 4522 gpio-controller; 4523 #gpio-cells = <2>; 4524 gpio-ranges = <&pinctrl 0 32 32>; 4525 interrupt-controller; 4526 #interrupt-cells = <2>; 4527 }; 4528 4529 gpio2: gpio@2ae20000 { 4530 compatible = "rockchip,gpio-bank"; 4531 reg = <0x0 0x2ae20000 0x0 0x200>; 4532 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 4533 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 4534 4535 gpio-controller; 4536 #gpio-cells = <2>; 4537 gpio-ranges = <&pinctrl 0 64 32>; 4538 interrupt-controller; 4539 #interrupt-cells = <2>; 4540 }; 4541 4542 gpio3: gpio@2ae30000 { 4543 compatible = "rockchip,gpio-bank"; 4544 reg = <0x0 0x2ae30000 0x0 0x200>; 4545 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 4546 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 4547 4548 gpio-controller; 4549 #gpio-cells = <2>; 4550 gpio-ranges = <&pinctrl 0 96 32>; 4551 interrupt-controller; 4552 #interrupt-cells = <2>; 4553 }; 4554 4555 gpio4: gpio@2ae40000 { 4556 compatible = "rockchip,gpio-bank"; 4557 reg = <0x0 0x2ae40000 0x0 0x200>; 4558 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 4559 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 4560 4561 gpio-controller; 4562 #gpio-cells = <2>; 4563 gpio-ranges = <&pinctrl 0 128 32>; 4564 interrupt-controller; 4565 #interrupt-cells = <2>; 4566 }; 4567 }; 4568}; 4569 4570#include "rk3576-pinctrl.dtsi" 4571
