1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3576-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rk3576-power.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/soc/rockchip-system-status.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 compatible = "rockchip,rk3576"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 csi2dcphy0 = &csi2_dcphy0; 25 csi2dphy0 = &csi2_dphy0; 26 csi2dphy1 = &csi2_dphy1; 27 csi2dphy2 = &csi2_dphy2; 28 csi2dphy3 = &csi2_dphy3; 29 csi2dphy4 = &csi2_dphy4; 30 csi2dphy5 = &csi2_dphy5; 31 ethernet0 = &gmac0; 32 ethernet1 = &gmac1; 33 gpio0 = &gpio0; 34 gpio1 = &gpio1; 35 gpio2 = &gpio2; 36 gpio3 = &gpio3; 37 gpio4 = &gpio4; 38 hdcp0 = &hdcp0; 39 hdcp1 = &hdcp1; 40 i2c0 = &i2c0; 41 i2c1 = &i2c1; 42 i2c2 = &i2c2; 43 i2c3 = &i2c3; 44 i2c4 = &i2c4; 45 i2c5 = &i2c5; 46 i2c6 = &i2c6; 47 i2c7 = &i2c7; 48 i2c8 = &i2c8; 49 i2c9 = &i2c9; 50 i3c0 = &i3c0; 51 i3c1 = &i3c1; 52 rkcif_mipi_lvds0 = &rkcif_mipi_lvds; 53 rkcif_mipi_lvds1 = &rkcif_mipi_lvds1; 54 rkcif_mipi_lvds2 = &rkcif_mipi_lvds2; 55 rkcif_mipi_lvds3 = &rkcif_mipi_lvds3; 56 rkcif_mipi_lvds4 = &rkcif_mipi_lvds4; 57 serial0 = &uart0; 58 serial1 = &uart1; 59 serial2 = &uart2; 60 serial3 = &uart3; 61 serial4 = &uart4; 62 serial5 = &uart5; 63 serial6 = &uart6; 64 serial7 = &uart7; 65 serial8 = &uart8; 66 serial9 = &uart9; 67 serial10 = &uart10; 68 serial11 = &uart11; 69 spi0 = &spi0; 70 spi1 = &spi1; 71 spi2 = &spi2; 72 spi3 = &spi3; 73 spi4 = &spi4; 74 spi5 = &sfc0; 75 spi6 = &sfc1; 76 }; 77 78 clocks { 79 compatible = "simple-bus"; 80 #address-cells = <2>; 81 #size-cells = <2>; 82 ranges; 83 84 xin32k: xin32k { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <32768>; 88 clock-output-names = "xin32k"; 89 }; 90 91 xin24m: xin24m { 92 compatible = "fixed-clock"; 93 #clock-cells = <0>; 94 clock-frequency = <24000000>; 95 clock-output-names = "xin24m"; 96 }; 97 98 spll: spll { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <702000000>; 102 clock-output-names = "spll"; 103 }; 104 105 mclkin_sai0: mclkin-sai0 { 106 compatible = "fixed-clock"; 107 #clock-cells = <0>; 108 clock-frequency = <0>; 109 clock-output-names = "sai0_mclkin"; 110 }; 111 112 mclkin_sai1: mclkin-sai1 { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <0>; 116 clock-output-names = "sai1_mclkin"; 117 }; 118 119 mclkin_sai2: mclkin-sai2 { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 clock-frequency = <0>; 123 clock-output-names = "sai2_mclkin"; 124 }; 125 126 mclkin_sai3: mclkin-sai3 { 127 compatible = "fixed-clock"; 128 #clock-cells = <0>; 129 clock-frequency = <0>; 130 clock-output-names = "sai3_mclkin"; 131 }; 132 133 mclkin_sai4: mclkin-sai4 { 134 compatible = "fixed-clock"; 135 #clock-cells = <0>; 136 clock-frequency = <0>; 137 clock-output-names = "sai4_mclkin"; 138 }; 139 140 mclkout_sai0: mclkout-sai0@26046400 { 141 compatible = "rockchip,clk-out"; 142 reg = <0 0x26046400 0 0x4>; 143 clocks = <&cru CLK_SAI0_MCLKOUT>; 144 #clock-cells = <0>; 145 clock-output-names = "mclk_sai0_to_io"; 146 rockchip,bit-shift = <0>; 147 rockchip,bit-set-to-disable; 148 }; 149 150 mclkout_sai1: mclkout-sai1@26046400 { 151 compatible = "rockchip,clk-out"; 152 reg = <0 0x26046400 0 0x4>; 153 clocks = <&cru CLK_SAI1_MCLKOUT>; 154 #clock-cells = <0>; 155 clock-output-names = "mclk_sai1_to_io"; 156 rockchip,bit-shift = <1>; 157 rockchip,bit-set-to-disable; 158 }; 159 160 mclkout_sai2: mclkout-sai2@26046400 { 161 compatible = "rockchip,clk-out"; 162 reg = <0 0x26046400 0 0x4>; 163 clocks = <&cru CLK_SAI2_MCLKOUT>; 164 #clock-cells = <0>; 165 clock-output-names = "mclk_sai2_to_io"; 166 rockchip,bit-shift = <2>; 167 rockchip,bit-set-to-disable; 168 }; 169 170 mclkout_sai3: mclkout-sai3@26046400 { 171 compatible = "rockchip,clk-out"; 172 reg = <0 0x26046400 0 0x4>; 173 clocks = <&cru CLK_SAI3_MCLKOUT>; 174 #clock-cells = <0>; 175 clock-output-names = "mclk_sai3_to_io"; 176 rockchip,bit-shift = <3>; 177 rockchip,bit-set-to-disable; 178 }; 179 180 mclkout_sai4: mclkout-sai4@26046400 { 181 compatible = "rockchip,clk-out"; 182 reg = <0 0x26046400 0 0x4>; 183 clocks = <&cru CLK_SAI4_MCLKOUT>; 184 #clock-cells = <0>; 185 clock-output-names = "mclk_sai4_to_io"; 186 rockchip,bit-shift = <4>; 187 rockchip,bit-set-to-disable; 188 }; 189 190 mclkout_sai4m2: mclkout-sai4m2@2604a400 { 191 compatible = "rockchip,clk-out"; 192 reg = <0 0x2604a400 0 0x4>; 193 clocks = <&cru CLK_SAI4_MCLKOUT>; 194 #clock-cells = <0>; 195 clock-output-names = "mclk_sai4_to_io"; 196 rockchip,bit-shift = <0>; 197 rockchip,bit-set-to-disable; 198 }; 199 200 sclkin_sai0: sclkin-sai0 { 201 compatible = "fixed-clock"; 202 #clock-cells = <0>; 203 clock-frequency = <0>; 204 clock-output-names = "sai0_sclk_in"; 205 }; 206 207 sclkin_sai1: sclkin-sai1 { 208 compatible = "fixed-clock"; 209 #clock-cells = <0>; 210 clock-frequency = <0>; 211 clock-output-names = "sai1_sclk_in"; 212 }; 213 214 sclkin_sai2: sclkin-sai2 { 215 compatible = "fixed-clock"; 216 #clock-cells = <0>; 217 clock-frequency = <0>; 218 clock-output-names = "sai2_sclk_in"; 219 }; 220 221 sclkin_sai3: sclkin-sai3 { 222 compatible = "fixed-clock"; 223 #clock-cells = <0>; 224 clock-frequency = <0>; 225 clock-output-names = "sai3_sclk_in"; 226 }; 227 228 sclkin_sai4: sclkin-sai4 { 229 compatible = "fixed-clock"; 230 #clock-cells = <0>; 231 clock-frequency = <0>; 232 clock-output-names = "sai4_sclk_in"; 233 }; 234 235 clk_pvtm_clkout: clk_pvtm_clkout { 236 compatible = "fixed-clock"; 237 #clock-cells = <0>; 238 clock-frequency = <32768>; 239 clock-output-names = "clk_pvtm_clkout"; 240 }; 241 242 aclk_usb: aclk_usb@272008bc { 243 compatible = "rockchip,rk3576-clock-gate-link"; 244 reg = <0 0x272008bc 0 0x10>; 245 clock-names = "link"; 246 clocks = <&cru ACLK_VOP_ROOT>; 247 #power-domain-cells = <1>; 248 #clock-cells = <0>; 249 }; 250 251 aclk_ufs: aclk_ufs@272008bc { 252 compatible = "rockchip,rk3576-clock-gate-link"; 253 reg = <0 0x272008bc 0 0x10>; 254 clock-names = "link"; 255 clocks = <&aclk_usb>; 256 #power-domain-cells = <1>; 257 #clock-cells = <0>; 258 }; 259 260 pclk_usbufs: pclk_usbufs@272008bc { 261 compatible = "rockchip,rk3576-clock-gate-link"; 262 reg = <0 0x272008bc 0 0x10>; 263 clock-names = "link"; 264 clocks = <&cru HCLK_VOP_ROOT>; 265 #power-domain-cells = <1>; 266 #clock-cells = <0>; 267 }; 268 269 aclk_hdcp1: aclk_hdcp1@27200910 { 270 compatible = "rockchip,rk3576-clock-gate-link"; 271 reg = <0 0x27200910 0 0x10>; 272 clock-names = "link"; 273 clocks = <&cru ACLK_VOP_ROOT>; 274 #power-domain-cells = <1>; 275 #clock-cells = <0>; 276 }; 277 278 aclk_hdcp0: aclk_hdcp0@272008fc { 279 compatible = "rockchip,rk3576-clock-gate-link"; 280 reg = <0 0x272008fc 0 0x10>; 281 clock-names = "link"; 282 clocks = <&cru ACLK_VOP_ROOT>; 283 #power-domain-cells = <1>; 284 #clock-cells = <0>; 285 }; 286 287 aclk_sdgmac: aclk_sdgmac@272008a8 { 288 compatible = "rockchip,rk3576-clock-gate-link"; 289 reg = <0 0x272008a8 0 0x10>; 290 clock-names = "link"; 291 clocks = <&cru ACLK_NVM_ROOT>; 292 #power-domain-cells = <1>; 293 #clock-cells = <0>; 294 }; 295 296 hclk_sdgmac: hclk_sdgmac@272008a8 { 297 compatible = "rockchip,rk3576-clock-gate-link"; 298 reg = <0 0x272008a8 0 0x10>; 299 clock-names = "link"; 300 clocks = <&aclk_sdgmac>; 301 #power-domain-cells = <1>; 302 #clock-cells = <0>; 303 }; 304 305 aclk_vdpp: aclk_vdpp@272008c8 { 306 compatible = "rockchip,rk3576-clock-gate-link"; 307 reg = <0 0x272008c8 0 0x10>; 308 clock-names = "link"; 309 clocks = <&cru ACLK_VPU_ROOT>; 310 #power-domain-cells = <1>; 311 #clock-cells = <0>; 312 }; 313 314 aclk_ebc: aclk_ebc@272008c8 { 315 compatible = "rockchip,rk3576-clock-gate-link"; 316 reg = <0 0x272008c8 0 0x10>; 317 clock-names = "link"; 318 clocks = <&cru ACLK_VPU_ROOT>; 319 #power-domain-cells = <1>; 320 #clock-cells = <0>; 321 }; 322 323 aclk_jpeg: aclk_jpeg@272008c8 { 324 compatible = "rockchip,rk3576-clock-gate-link"; 325 reg = <0 0x272008c8 0 0x10>; 326 clock-names = "link"; 327 clocks = <&cru ACLK_VPU_ROOT>; 328 #power-domain-cells = <1>; 329 #clock-cells = <0>; 330 }; 331 332 aclk_vepu0: aclk_vepu0@272008cc { 333 compatible = "rockchip,rk3576-clock-gate-link"; 334 reg = <0 0x272008cc 0 0x10>; 335 clock-names = "link"; 336 clocks = <&cru ACLK_VI_ROOT>; 337 #power-domain-cells = <1>; 338 #clock-cells = <0>; 339 }; 340 341 hclk_vo1: hclk_vo1@2720090c { 342 compatible = "rockchip,rk3576-clock-gate-link"; 343 reg = <0 0x2720090c 0 0x10>; 344 clock-names = "link"; 345 clocks = <&cru HCLK_VOP_ROOT>; 346 #power-domain-cells = <1>; 347 #clock-cells = <0>; 348 }; 349 350 hclk_vo0: hclk_vo0@272008fc { 351 compatible = "rockchip,rk3576-clock-gate-link"; 352 reg = <0 0x272008fc 0 0x10>; 353 clock-names = "link"; 354 clocks = <&cru HCLK_VOP_ROOT>; 355 #power-domain-cells = <1>; 356 #clock-cells = <0>; 357 }; 358 359 aclk_dsmc: aclk_dsmc@272008ac { 360 compatible = "rockchip,rk3576-clock-gate-link"; 361 reg = <0 0x272008ac 0 0x10>; 362 clock-names = "link"; 363 clocks = <&cru HCLK_NVM_ROOT>; 364 #power-domain-cells = <1>; 365 #clock-cells = <0>; 366 }; 367 368 pclk_sdgmac: pclk_sdgmac@272008a8 { 369 compatible = "rockchip,rk3576-clock-gate-link"; 370 reg = <0 0x272008a8 0 0x10>; 371 clock-names = "link"; 372 clocks = <&aclk_dsmc>; 373 #power-domain-cells = <1>; 374 #clock-cells = <0>; 375 }; 376 377 hclk_vepu0: hclk_vepu0@272008cc { 378 compatible = "rockchip,rk3576-clock-gate-link"; 379 reg = <0 0x272008cc 0 0x10>; 380 clock-names = "link"; 381 clocks = <&cru HCLK_VI_ROOT>; 382 #power-domain-cells = <1>; 383 #clock-cells = <0>; 384 }; 385 }; 386 387 cpus { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 391 cpu-map { 392 cluster0 { 393 core0 { 394 cpu = <&cpu_l0>; 395 }; 396 core1 { 397 cpu = <&cpu_l1>; 398 }; 399 core2 { 400 cpu = <&cpu_l2>; 401 }; 402 core3 { 403 cpu = <&cpu_l3>; 404 }; 405 }; 406 cluster1 { 407 core0 { 408 cpu = <&cpu_b0>; 409 }; 410 core1 { 411 cpu = <&cpu_b1>; 412 }; 413 core2 { 414 cpu = <&cpu_b2>; 415 }; 416 core3 { 417 cpu = <&cpu_b3>; 418 }; 419 }; 420 }; 421 422 cpu_l0: cpu@0 { 423 device_type = "cpu"; 424 compatible = "arm,cortex-a53"; 425 reg = <0x0>; 426 enable-method = "psci"; 427 capacity-dmips-mhz = <485>; 428 clocks = <&cru ARMCLK_L>; 429 operating-points-v2 = <&cluster0_opp_table>; 430 }; 431 432 cpu_l1: cpu@1 { 433 device_type = "cpu"; 434 compatible = "arm,cortex-a53"; 435 reg = <0x1>; 436 enable-method = "psci"; 437 capacity-dmips-mhz = <485>; 438 clocks = <&cru ARMCLK_L>; 439 operating-points-v2 = <&cluster0_opp_table>; 440 }; 441 442 cpu_l2: cpu@2 { 443 device_type = "cpu"; 444 compatible = "arm,cortex-a53"; 445 reg = <0x2>; 446 enable-method = "psci"; 447 capacity-dmips-mhz = <485>; 448 clocks = <&cru ARMCLK_L>; 449 operating-points-v2 = <&cluster0_opp_table>; 450 }; 451 452 cpu_l3: cpu@3 { 453 device_type = "cpu"; 454 compatible = "arm,cortex-a53"; 455 reg = <0x3>; 456 enable-method = "psci"; 457 capacity-dmips-mhz = <485>; 458 clocks = <&cru ARMCLK_L>; 459 operating-points-v2 = <&cluster0_opp_table>; 460 }; 461 462 cpu_b0: cpu@100 { 463 device_type = "cpu"; 464 compatible = "arm,cortex-a72"; 465 reg = <0x100>; 466 enable-method = "psci"; 467 capacity-dmips-mhz = <1024>; 468 clocks = <&cru ARMCLK_B>; 469 operating-points-v2 = <&cluster1_opp_table>; 470 }; 471 472 cpu_b1: cpu@101 { 473 device_type = "cpu"; 474 compatible = "arm,cortex-a72"; 475 reg = <0x101>; 476 enable-method = "psci"; 477 capacity-dmips-mhz = <1024>; 478 clocks = <&cru ARMCLK_B>; 479 operating-points-v2 = <&cluster1_opp_table>; 480 }; 481 482 cpu_b2: cpu@102 { 483 device_type = "cpu"; 484 compatible = "arm,cortex-a72"; 485 reg = <0x102>; 486 enable-method = "psci"; 487 capacity-dmips-mhz = <1024>; 488 clocks = <&cru ARMCLK_B>; 489 operating-points-v2 = <&cluster1_opp_table>; 490 }; 491 492 cpu_b3: cpu@103 { 493 device_type = "cpu"; 494 compatible = "arm,cortex-a72"; 495 reg = <0x103>; 496 enable-method = "psci"; 497 capacity-dmips-mhz = <1024>; 498 clocks = <&cru ARMCLK_B>; 499 operating-points-v2 = <&cluster1_opp_table>; 500 }; 501 }; 502 503 cluster0_opp_table: cluster0-opp-table { 504 compatible = "operating-points-v2"; 505 opp-shared; 506 507 opp-408000000 { 508 opp-hz = /bits/ 64 <408000000>; 509 opp-microvolt = <950000 950000 950000>; 510 clock-latency-ns = <40000>; 511 }; 512 opp-600000000 { 513 opp-hz = /bits/ 64 <600000000>; 514 opp-microvolt = <950000 950000 950000>; 515 clock-latency-ns = <40000>; 516 }; 517 opp-816000000 { 518 opp-hz = /bits/ 64 <816000000>; 519 opp-microvolt = <950000 950000 950000>; 520 clock-latency-ns = <40000>; 521 }; 522 opp-1008000000 { 523 opp-hz = /bits/ 64 <1008000000>; 524 opp-microvolt = <950000 950000 950000>; 525 clock-latency-ns = <40000>; 526 }; 527 opp-1200000000 { 528 opp-hz = /bits/ 64 <1200000000>; 529 opp-microvolt = <950000 950000 950000>; 530 clock-latency-ns = <40000>; 531 }; 532 opp-1416000000 { 533 opp-hz = /bits/ 64 <1416000000>; 534 opp-microvolt = <950000 950000 950000>; 535 clock-latency-ns = <40000>; 536 }; 537 }; 538 539 cluster1_opp_table: cluster1-opp-table { 540 compatible = "operating-points-v2"; 541 opp-shared; 542 543 opp-408000000 { 544 opp-hz = /bits/ 64 <408000000>; 545 opp-microvolt = <950000 950000 950000>; 546 clock-latency-ns = <40000>; 547 }; 548 opp-600000000 { 549 opp-hz = /bits/ 64 <600000000>; 550 opp-microvolt = <950000 950000 950000>; 551 clock-latency-ns = <40000>; 552 }; 553 opp-816000000 { 554 opp-hz = /bits/ 64 <816000000>; 555 opp-microvolt = <950000 950000 950000>; 556 clock-latency-ns = <40000>; 557 }; 558 opp-1008000000 { 559 opp-hz = /bits/ 64 <1008000000>; 560 opp-microvolt = <950000 950000 950000>; 561 clock-latency-ns = <40000>; 562 }; 563 opp-1200000000 { 564 opp-hz = /bits/ 64 <1200000000>; 565 opp-microvolt = <950000 950000 950000>; 566 clock-latency-ns = <40000>; 567 }; 568 opp-1416000000 { 569 opp-hz = /bits/ 64 <1416000000>; 570 opp-microvolt = <950000 950000 950000>; 571 clock-latency-ns = <40000>; 572 }; 573 opp-1608000000 { 574 opp-hz = /bits/ 64 <1608000000>; 575 opp-microvolt = <950000 950000 950000>; 576 clock-latency-ns = <40000>; 577 }; 578 }; 579 580 cpuinfo { 581 compatible = "rockchip,cpuinfo"; 582 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 583 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 584 }; 585 586 csi2_dcphy0: csi2-dcphy0 { 587 compatible = "rockchip,rk3576-csi2-dphy"; 588 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 589 phys = <&mipidcphy0>; 590 phy-names = "dcphy0"; 591 status = "disabled"; 592 }; 593 594 csi2_dphy0: csi2-dphy0 { 595 compatible = "rockchip,rk3576-csi2-dphy"; 596 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 597 phys = <&mipidcphy0>; 598 phy-names = "dcphy0"; 599 status = "disabled"; 600 }; 601 602 csi2_dphy1: csi2-dphy1 { 603 compatible = "rockchip,rk3576-csi2-dphy"; 604 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 605 phys = <&mipidcphy0>; 606 phy-names = "dcphy0"; 607 status = "disabled"; 608 }; 609 610 csi2_dphy2: csi2-dphy2 { 611 compatible = "rockchip,rk3576-csi2-dphy"; 612 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 613 phys = <&mipidcphy0>; 614 phy-names = "dcphy0"; 615 status = "disabled"; 616 }; 617 618 csi2_dphy3: csi2-dphy3 { 619 compatible = "rockchip,rk3576-csi2-dphy"; 620 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 621 phys = <&mipidcphy0>; 622 phy-names = "dcphy0"; 623 status = "disabled"; 624 }; 625 626 csi2_dphy4: csi2-dphy4 { 627 compatible = "rockchip,rk3576-csi2-dphy"; 628 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 629 phys = <&mipidcphy0>; 630 phy-names = "dcphy0"; 631 status = "disabled"; 632 }; 633 634 csi2_dphy5: csi2-dphy5 { 635 compatible = "rockchip,rk3576-csi2-dphy"; 636 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 637 phys = <&mipidcphy0>; 638 phy-names = "dcphy0"; 639 status = "disabled"; 640 }; 641 642 display_subsystem: display-subsystem { 643 compatible = "rockchip,display-subsystem"; 644 ports = <&vop_out>, <&vopl_out>; 645 646 route { 647 route_dsi: route-dsi { 648 status = "disabled"; 649 logo,uboot = "logo.bmp"; 650 logo,kernel = "logo_kernel.bmp"; 651 logo,mode = "center"; 652 charge_logo,mode = "center"; 653 connect = <&vp2_out_dsi>; 654 }; 655 656 route_edp: route-edp { 657 status = "disabled"; 658 logo,uboot = "logo.bmp"; 659 logo,kernel = "logo_kernel.bmp"; 660 logo,mode = "center"; 661 charge_logo,mode = "center"; 662 connect = <&vp1_out_edp>; 663 }; 664 665 route_hdmi: route-hdmi { 666 status = "disabled"; 667 logo,uboot = "logo.bmp"; 668 logo,kernel = "logo_kernel.bmp"; 669 logo,mode = "center"; 670 charge_logo,mode = "center"; 671 connect = <&vp0_out_hdmi>; 672 }; 673 674 route_dp0: route-dp0 { 675 status = "disabled"; 676 logo,uboot = "logo.bmp"; 677 logo,kernel = "logo_kernel.bmp"; 678 logo,mode = "center"; 679 charge_logo,mode = "center"; 680 connect = <&vp0_out_dp0>; 681 }; 682 683 route_rgb: route-rgb { 684 status = "disabled"; 685 logo,uboot = "logo.bmp"; 686 logo,kernel = "logo_kernel.bmp"; 687 logo,mode = "center"; 688 charge_logo,mode = "center"; 689 connect = <&vp2_out_rgb>; 690 }; 691 }; 692 }; 693 694 firmware { 695 scmi: scmi { 696 compatible = "arm,scmi-smc"; 697 arm,smc-id = <0x82000010>; 698 shmem = <&scmi_shmem>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 702 scmi_clk: protocol@14 { 703 reg = <0x14>; 704 #clock-cells = <1>; 705 }; 706 }; 707 }; 708 709 mipi0_csi2: mipi0-csi2 { 710 compatible = "rockchip,rk3576-mipi-csi2"; 711 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 712 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 713 <&mipi4_csi2_hw>; 714 status = "disabled"; 715 }; 716 717 mipi1_csi2: mipi1-csi2 { 718 compatible = "rockchip,rk3576-mipi-csi2"; 719 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 720 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 721 <&mipi4_csi2_hw>; 722 status = "disabled"; 723 }; 724 725 mipi2_csi2: mipi2-csi2 { 726 compatible = "rockchip,rk3576-mipi-csi2"; 727 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 728 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 729 <&mipi4_csi2_hw>; 730 status = "disabled"; 731 }; 732 733 mipi3_csi2: mipi3-csi2 { 734 compatible = "rockchip,rk3576-mipi-csi2"; 735 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 736 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 737 <&mipi4_csi2_hw>; 738 status = "disabled"; 739 }; 740 741 mipi4_csi2: mipi4-csi2 { 742 compatible = "rockchip,rk3576-mipi-csi2"; 743 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 744 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 745 <&mipi4_csi2_hw>; 746 status = "disabled"; 747 }; 748 749 mpp_srv: mpp-srv { 750 compatible = "rockchip,mpp-service"; 751 rockchip,taskqueue-count = <6>; 752 rockchip,resetgroup-count = <1>; 753 status = "disabled"; 754 }; 755 756 pmu_a53: pmu-a53 { 757 compatible = "arm,cortex-a53-pmu"; 758 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 762 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>; 763 }; 764 765 pmu_a72: pmu-a72 { 766 compatible = "arm,cortex-a72-pmu"; 767 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 771 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 772 }; 773 774 psci: psci { 775 compatible = "arm,psci-1.0"; 776 method = "smc"; 777 }; 778 779 rkcif_dvp: rkcif-dvp { 780 compatible = "rockchip,rkcif-dvp"; 781 rockchip,hw = <&rkcif>; 782 iommus = <&rkcif_mmu>; 783 status = "disabled"; 784 }; 785 786 rkcif_dvp_sditf: rkcif-dvp-sditf { 787 compatible = "rockchip,rkcif-sditf"; 788 rockchip,cif = <&rkcif_dvp>; 789 status = "disabled"; 790 }; 791 792 rkcif_mipi_lvds: rkcif-mipi-lvds { 793 compatible = "rockchip,rkcif-mipi-lvds"; 794 rockchip,hw = <&rkcif>; 795 iommus = <&rkcif_mmu>; 796 status = "disabled"; 797 }; 798 799 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { 800 compatible = "rockchip,rkcif-sditf"; 801 rockchip,cif = <&rkcif_mipi_lvds>; 802 status = "disabled"; 803 }; 804 805 rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 { 806 compatible = "rockchip,rkcif-sditf"; 807 rockchip,cif = <&rkcif_mipi_lvds>; 808 status = "disabled"; 809 }; 810 811 rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 { 812 compatible = "rockchip,rkcif-sditf"; 813 rockchip,cif = <&rkcif_mipi_lvds>; 814 status = "disabled"; 815 }; 816 817 rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 { 818 compatible = "rockchip,rkcif-sditf"; 819 rockchip,cif = <&rkcif_mipi_lvds>; 820 status = "disabled"; 821 }; 822 823 rkcif_mipi_lvds1: rkcif-mipi-lvds1 { 824 compatible = "rockchip,rkcif-mipi-lvds"; 825 rockchip,hw = <&rkcif>; 826 iommus = <&rkcif_mmu>; 827 status = "disabled"; 828 }; 829 830 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { 831 compatible = "rockchip,rkcif-sditf"; 832 rockchip,cif = <&rkcif_mipi_lvds1>; 833 status = "disabled"; 834 }; 835 836 rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 { 837 compatible = "rockchip,rkcif-sditf"; 838 rockchip,cif = <&rkcif_mipi_lvds1>; 839 status = "disabled"; 840 }; 841 842 rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 { 843 compatible = "rockchip,rkcif-sditf"; 844 rockchip,cif = <&rkcif_mipi_lvds1>; 845 status = "disabled"; 846 }; 847 848 rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 { 849 compatible = "rockchip,rkcif-sditf"; 850 rockchip,cif = <&rkcif_mipi_lvds1>; 851 status = "disabled"; 852 }; 853 854 rkcif_mipi_lvds2: rkcif-mipi-lvds2 { 855 compatible = "rockchip,rkcif-mipi-lvds"; 856 rockchip,hw = <&rkcif>; 857 iommus = <&rkcif_mmu>; 858 status = "disabled"; 859 }; 860 861 rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf { 862 compatible = "rockchip,rkcif-sditf"; 863 rockchip,cif = <&rkcif_mipi_lvds2>; 864 status = "disabled"; 865 }; 866 867 rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 { 868 compatible = "rockchip,rkcif-sditf"; 869 rockchip,cif = <&rkcif_mipi_lvds2>; 870 status = "disabled"; 871 }; 872 873 rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 { 874 compatible = "rockchip,rkcif-sditf"; 875 rockchip,cif = <&rkcif_mipi_lvds2>; 876 status = "disabled"; 877 }; 878 879 rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 { 880 compatible = "rockchip,rkcif-sditf"; 881 rockchip,cif = <&rkcif_mipi_lvds2>; 882 status = "disabled"; 883 }; 884 885 rkcif_mipi_lvds3: rkcif-mipi-lvds3 { 886 compatible = "rockchip,rkcif-mipi-lvds"; 887 rockchip,hw = <&rkcif>; 888 iommus = <&rkcif_mmu>; 889 status = "disabled"; 890 }; 891 892 rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf { 893 compatible = "rockchip,rkcif-sditf"; 894 rockchip,cif = <&rkcif_mipi_lvds3>; 895 status = "disabled"; 896 }; 897 898 rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 { 899 compatible = "rockchip,rkcif-sditf"; 900 rockchip,cif = <&rkcif_mipi_lvds3>; 901 status = "disabled"; 902 }; 903 904 rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 { 905 compatible = "rockchip,rkcif-sditf"; 906 rockchip,cif = <&rkcif_mipi_lvds3>; 907 status = "disabled"; 908 }; 909 910 rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 { 911 compatible = "rockchip,rkcif-sditf"; 912 rockchip,cif = <&rkcif_mipi_lvds3>; 913 status = "disabled"; 914 }; 915 916 rkcif_mipi_lvds4: rkcif-mipi-lvds4 { 917 compatible = "rockchip,rkcif-mipi-lvds"; 918 rockchip,hw = <&rkcif>; 919 iommus = <&rkcif_mmu>; 920 status = "disabled"; 921 }; 922 923 rkcif_mipi_lvds4_sditf: rkcif-mipi-lvds4-sditf { 924 compatible = "rockchip,rkcif-sditf"; 925 rockchip,cif = <&rkcif_mipi_lvds4>; 926 status = "disabled"; 927 }; 928 929 rkcif_mipi_lvds4_sditf_vir1: rkcif-mipi-lvds4-sditf-vir1 { 930 compatible = "rockchip,rkcif-sditf"; 931 rockchip,cif = <&rkcif_mipi_lvds4>; 932 status = "disabled"; 933 }; 934 935 rkcif_mipi_lvds4_sditf_vir2: rkcif-mipi-lvds4-sditf-vir2 { 936 compatible = "rockchip,rkcif-sditf"; 937 rockchip,cif = <&rkcif_mipi_lvds4>; 938 status = "disabled"; 939 }; 940 941 rkcif_mipi_lvds4_sditf_vir3: rkcif-mipi-lvds4-sditf-vir3 { 942 compatible = "rockchip,rkcif-sditf"; 943 rockchip,cif = <&rkcif_mipi_lvds4>; 944 status = "disabled"; 945 }; 946 947 rkisp_vir0: rkisp-vir0 { 948 compatible = "rockchip,rkisp-vir"; 949 rockchip,hw = <&rkisp>; 950 status = "disabled"; 951 }; 952 953 rkisp_vir1: rkisp-vir1 { 954 compatible = "rockchip,rkisp-vir"; 955 rockchip,hw = <&rkisp>; 956 status = "disabled"; 957 }; 958 959 rkisp_vir2: rkisp-vir2 { 960 compatible = "rockchip,rkisp-vir"; 961 rockchip,hw = <&rkisp>; 962 status = "disabled"; 963 }; 964 965 rkisp_vir3: rkisp-vir3 { 966 compatible = "rockchip,rkisp-vir"; 967 rockchip,hw = <&rkisp>; 968 status = "disabled"; 969 }; 970 971 rkisp_vir4: rkisp-vir4 { 972 compatible = "rockchip,rkisp-vir"; 973 rockchip,hw = <&rkisp>; 974 status = "disabled"; 975 }; 976 977 rkisp_vir5: rkisp-vir5 { 978 compatible = "rockchip,rkisp-vir"; 979 rockchip,hw = <&rkisp>; 980 status = "disabled"; 981 }; 982 983 rkisp_vir0_sditf: rkisp-vir0-sditf { 984 compatible = "rockchip,rkisp-sditf"; 985 rockchip,isp = <&rkisp_vir0>; 986 status = "disabled"; 987 988 port { 989 isp_sditf0: endpoint { 990 remote-endpoint = <&vpss0_in>; 991 }; 992 }; 993 }; 994 995 rkisp_vir1_sditf: rkisp-vir1-sditf { 996 compatible = "rockchip,rkisp-sditf"; 997 rockchip,isp = <&rkisp_vir1>; 998 status = "disabled"; 999 1000 port { 1001 isp_sditf1: endpoint { 1002 remote-endpoint = <&vpss1_in>; 1003 }; 1004 }; 1005 }; 1006 1007 rkisp_vir2_sditf: rkisp-vir2-sditf { 1008 compatible = "rockchip,rkisp-sditf"; 1009 rockchip,isp = <&rkisp_vir2>; 1010 status = "disabled"; 1011 1012 port { 1013 isp_sditf2: endpoint { 1014 remote-endpoint = <&vpss2_in>; 1015 }; 1016 }; 1017 }; 1018 1019 rkisp_vir3_sditf: rkisp-vir3-sditf { 1020 compatible = "rockchip,rkisp-sditf"; 1021 rockchip,isp = <&rkisp_vir3>; 1022 status = "disabled"; 1023 1024 port { 1025 isp_sditf3: endpoint { 1026 remote-endpoint = <&vpss3_in>; 1027 }; 1028 }; 1029 }; 1030 1031 rkisp_vir4_sditf: rkisp-vir4-sditf { 1032 compatible = "rockchip,rkisp-sditf"; 1033 rockchip,isp = <&rkisp_vir4>; 1034 status = "disabled"; 1035 1036 port { 1037 isp_sditf4: endpoint { 1038 remote-endpoint = <&vpss4_in>; 1039 }; 1040 }; 1041 }; 1042 1043 rkisp_vir5_sditf: rkisp-vir5-sditf { 1044 compatible = "rockchip,rkisp-sditf"; 1045 rockchip,isp = <&rkisp_vir5>; 1046 status = "disabled"; 1047 1048 port { 1049 isp_sditf5: endpoint { 1050 remote-endpoint = <&vpss5_in>; 1051 }; 1052 }; 1053 }; 1054 1055 rkvenc_ccu: rkvenc-ccu { 1056 compatible = "rockchip,rkv-encoder-rk3576-ccu", "rockchip,rkv-encoder-v2-ccu"; 1057 status = "disabled"; 1058 }; 1059 1060 rkvpss_vir0: rkvpss-vir0 { 1061 compatible = "rockchip,rkvpss-vir"; 1062 rockchip,hw = <&rkvpss>; 1063 status = "disabled"; 1064 1065 port { 1066 vpss0_in: endpoint { 1067 remote-endpoint = <&isp_sditf0>; 1068 }; 1069 }; 1070 }; 1071 1072 rkvpss_vir1: rkvpss-vir1 { 1073 compatible = "rockchip,rkvpss-vir"; 1074 rockchip,hw = <&rkvpss>; 1075 status = "disabled"; 1076 1077 port { 1078 vpss1_in: endpoint { 1079 remote-endpoint = <&isp_sditf1>; 1080 }; 1081 }; 1082 }; 1083 1084 rkvpss_vir2: rkvpss-vir2 { 1085 compatible = "rockchip,rkvpss-vir"; 1086 rockchip,hw = <&rkvpss>; 1087 status = "disabled"; 1088 1089 port { 1090 vpss2_in: endpoint { 1091 remote-endpoint = <&isp_sditf2>; 1092 }; 1093 }; 1094 }; 1095 1096 rkvpss_vir3: rkvpss-vir3 { 1097 compatible = "rockchip,rkvpss-vir"; 1098 rockchip,hw = <&rkvpss>; 1099 status = "disabled"; 1100 1101 port { 1102 vpss3_in: endpoint { 1103 remote-endpoint = <&isp_sditf3>; 1104 }; 1105 }; 1106 }; 1107 1108 rkvpss_vir4: rkvpss-vir4 { 1109 compatible = "rockchip,rkvpss-vir"; 1110 rockchip,hw = <&rkvpss>; 1111 status = "disabled"; 1112 1113 port { 1114 vpss4_in: endpoint { 1115 remote-endpoint = <&isp_sditf4>; 1116 }; 1117 }; 1118 }; 1119 1120 rkvpss_vir5: rkvpss-vir5 { 1121 compatible = "rockchip,rkvpss-vir"; 1122 rockchip,hw = <&rkvpss>; 1123 status = "disabled"; 1124 1125 port { 1126 vpss5_in: endpoint { 1127 remote-endpoint = <&isp_sditf5>; 1128 }; 1129 }; 1130 }; 1131 1132 thermal_zones: thermal-zones { 1133 soc_thermal: soc-thermal { 1134 polling-delay-passive = <20>; /* milliseconds */ 1135 polling-delay = <1000>; /* milliseconds */ 1136 thermal-sensors = <&tsadc 0>; 1137 trips { 1138 soc_crit: soc-crit { 1139 /* millicelsius */ 1140 temperature = <115000>; 1141 /* millicelsius */ 1142 hysteresis = <2000>; 1143 type = "critical"; 1144 }; 1145 }; 1146 }; 1147 bigcore_thermal: bigcore-thermal { 1148 polling-delay-passive = <20>; /* milliseconds */ 1149 polling-delay = <1000>; /* milliseconds */ 1150 thermal-sensors = <&tsadc 1>; 1151 trips { 1152 bigcore_crit: bigcore-crit { 1153 /* millicelsius */ 1154 temperature = <115000>; 1155 /* millicelsius */ 1156 hysteresis = <2000>; 1157 type = "critical"; 1158 }; 1159 }; 1160 }; 1161 little_core_thermal: little-core-thermal { 1162 polling-delay-passive = <20>; /* milliseconds */ 1163 polling-delay = <1000>; /* milliseconds */ 1164 thermal-sensors = <&tsadc 2>; 1165 trips { 1166 little_core_crit: little-core-crit { 1167 /* millicelsius */ 1168 temperature = <115000>; 1169 /* millicelsius */ 1170 hysteresis = <2000>; 1171 type = "critical"; 1172 }; 1173 }; 1174 }; 1175 ddr_thermal: ddr-thermal { 1176 polling-delay-passive = <20>; /* milliseconds */ 1177 polling-delay = <1000>; /* milliseconds */ 1178 thermal-sensors = <&tsadc 3>; 1179 trips { 1180 ddr_crit: ddr-crit { 1181 /* millicelsius */ 1182 temperature = <115000>; 1183 /* millicelsius */ 1184 hysteresis = <2000>; 1185 type = "critical"; 1186 }; 1187 }; 1188 }; 1189 npu_thermal: npu-thermal { 1190 polling-delay-passive = <20>; /* milliseconds */ 1191 polling-delay = <1000>; /* milliseconds */ 1192 thermal-sensors = <&tsadc 4>; 1193 trips { 1194 npu_crit: npu-crit { 1195 /* millicelsius */ 1196 temperature = <115000>; 1197 /* millicelsius */ 1198 hysteresis = <2000>; 1199 type = "critical"; 1200 }; 1201 }; 1202 }; 1203 gpu_thermal: gpu-thermal { 1204 polling-delay-passive = <20>; /* milliseconds */ 1205 polling-delay = <1000>; /* milliseconds */ 1206 thermal-sensors = <&tsadc 5>; 1207 trips { 1208 gpu_crit: gpu-crit { 1209 /* millicelsius */ 1210 temperature = <115000>; 1211 /* millicelsius */ 1212 hysteresis = <2000>; 1213 type = "critical"; 1214 }; 1215 }; 1216 }; 1217 }; 1218 1219 timer { 1220 compatible = "arm,armv8-timer"; 1221 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1222 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1223 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1224 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 1225 }; 1226 1227 usb_drd0_dwc3: usb@23000000 { 1228 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 1229 reg = <0x0 0x23000000 0x0 0x400000>; 1230 clocks = <&cru CLK_REF_USB3OTG0>, 1231 <&cru CLK_SUSPEND_USB3OTG0>, 1232 <&cru ACLK_USB3OTG0>; 1233 clock-names = "ref", "suspend", "bus_clk"; 1234 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1235 power-domains = <&power RK3576_PD_USB>; 1236 resets = <&cru SRST_A_USB3OTG0>; 1237 reset-names = "usb3-otg"; 1238 dr_mode = "otg"; 1239 phys = <&u2phy0_otg>, <&usbdp_phy_u3>; 1240 phy-names = "usb2-phy", "usb3-phy"; 1241 phy_type = "utmi_wide"; 1242 snps,dis_enblslpm_quirk; 1243 snps,dis-u1-entry-quirk; 1244 snps,dis-u2-entry-quirk; 1245 snps,dis-u2-freeclk-exists-quirk; 1246 snps,dis-del-phy-power-chg-quirk; 1247 snps,dis-tx-ipgap-linecheck-quirk; 1248 snps,parkmode-disable-hs-quirk; 1249 snps,parkmode-disable-ss-quirk; 1250 status = "disabled"; 1251 }; 1252 1253 usb_drd1_dwc3: usb@23400000 { 1254 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 1255 reg = <0x0 0x23400000 0x0 0x400000>; 1256 clocks = <&cru CLK_REF_USB3OTG1>, 1257 <&cru CLK_SUSPEND_USB3OTG1>, 1258 <&cru ACLK_USB3OTG1>; 1259 clock-names = "ref", "suspend", "bus_clk"; 1260 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 1261 power-domains = <&power RK3576_PD_PHP>; 1262 resets = <&cru SRST_A_USB3OTG1>; 1263 reset-names = "usb3-otg"; 1264 dr_mode = "otg"; 1265 phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>; 1266 phy-names = "usb2-phy", "usb3-phy"; 1267 phy_type = "utmi_wide"; 1268 snps,dis_enblslpm_quirk; 1269 snps,dis-u1-entry-quirk; 1270 snps,dis-u2-entry-quirk; 1271 snps,dis-u2-freeclk-exists-quirk; 1272 snps,dis-del-phy-power-chg-quirk; 1273 snps,dis-tx-ipgap-linecheck-quirk; 1274 snps,dis_rxdet_inp3_quirk; 1275 snps,parkmode-disable-hs-quirk; 1276 snps,parkmode-disable-ss-quirk; 1277 status = "disabled"; 1278 }; 1279 1280 sys_grf: syscon@2600a000 { 1281 compatible = "rockchip,rk3576-sys-grf", "syscon", "simple-mfd"; 1282 reg = <0x0 0x2600a000 0x0 0x10000>; 1283 }; 1284 1285 vo0_grf: syscon@2601a000 { 1286 compatible = "rockchip,rk3576-vo0-grf", "syscon"; 1287 reg = <0x0 0x2601a000 0x0 0x2000>; 1288 clocks = <&cru PCLK_VO0_ROOT>; 1289 }; 1290 1291 usb_grf: syscon@2601e000 { 1292 compatible = "rockchip,rk3576-usb-grf", "syscon"; 1293 reg = <0x0 0x2601e000 0x0 0x1000>; 1294 clocks = <&cru PCLK_USB_ROOT>; 1295 }; 1296 1297 php_grf: syscon@26020000 { 1298 compatible = "rockchip,rk3576-php-grf", "syscon"; 1299 reg = <0x0 0x26020000 0x0 0x2000>; 1300 clocks = <&cru PCLK_PHP_ROOT>; 1301 }; 1302 1303 pmu0_grf: syscon@26024000 { 1304 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd"; 1305 reg = <0x0 0x26024000 0x0 0x1000>; 1306 1307 reboot_mode: reboot-mode { 1308 compatible = "syscon-reboot-mode"; 1309 offset = <0x40>; 1310 mode-bootloader = <BOOT_BL_DOWNLOAD>; 1311 mode-charge = <BOOT_CHARGING>; 1312 mode-fastboot = <BOOT_FASTBOOT>; 1313 mode-loader = <BOOT_BL_DOWNLOAD>; 1314 mode-normal = <BOOT_NORMAL>; 1315 mode-recovery = <BOOT_RECOVERY>; 1316 mode-ums = <BOOT_UMS>; 1317 mode-panic = <BOOT_PANIC>; 1318 mode-watchdog = <BOOT_WATCHDOG>; 1319 mode-quiescent = <BOOT_QUIESCENT>; 1320 /* add a mode to capture the ramdump through usb */ 1321 mode-winusb = <BOOT_WINUSB>; 1322 }; 1323 }; 1324 1325 pipe_phy0_grf: syscon@26028000 { 1326 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 1327 reg = <0x0 0x26028000 0x0 0x2000>; 1328 clocks = <&cru PCLK_PCIE2_COMBOPHY0>; 1329 }; 1330 1331 pipe_phy1_grf: syscon@2602a000 { 1332 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 1333 reg = <0x0 0x2602a000 0x0 0x2000>; 1334 clocks = <&cru PCLK_PCIE2_COMBOPHY1>; 1335 }; 1336 1337 usbdpphy_grf: syscon@2602c000 { 1338 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon"; 1339 reg = <0x0 0x2602c000 0x0 0x2000>; 1340 clocks = <&cru PCLK_PMUPHY_ROOT>; 1341 }; 1342 1343 usb2phy_grf: syscon@2602e000 { 1344 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd"; 1345 reg = <0x0 0x2602e000 0x0 0x4000>; 1346 #address-cells = <1>; 1347 #size-cells = <1>; 1348 clocks = <&cru PCLK_PMUPHY_ROOT>; 1349 1350 u2phy0: usb2-phy@0 { 1351 compatible = "rockchip,rk3576-usb2phy"; 1352 reg = <0x0 0x10>; 1353 resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>; 1354 reset-names = "phy", "apb"; 1355 clocks = <&cru CLK_PHY_REF_SRC>; 1356 clock-names = "phyclk"; 1357 clock-output-names = "usb480m_phy0"; 1358 #clock-cells = <0>; 1359 rockchip,usbctrl-grf = <&usb_grf>; 1360 status = "disabled"; 1361 1362 u2phy0_otg: otg-port { 1363 #phy-cells = <0>; 1364 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1367 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 1368 status = "disabled"; 1369 }; 1370 }; 1371 1372 u2phy1: usb2-phy@2000 { 1373 compatible = "rockchip,rk3576-usb2phy"; 1374 reg = <0x2000 0x10>; 1375 resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>; 1376 reset-names = "phy", "apb"; 1377 clocks = <&cru CLK_PHY_REF_SRC>; 1378 clock-names = "phyclk"; 1379 clock-output-names = "usb480m_phy1"; 1380 #clock-cells = <0>; 1381 rockchip,usbctrl-grf = <&php_grf>; 1382 status = "disabled"; 1383 1384 u2phy1_otg: otg-port { 1385 #phy-cells = <0>; 1386 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1389 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 1390 status = "disabled"; 1391 }; 1392 }; 1393 }; 1394 1395 hdptxphy_grf: syscon@26032000 { 1396 compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; 1397 reg = <0x0 0x26032000 0x0 0x100>; 1398 clocks = <&cru PCLK_PMUPHY_ROOT>; 1399 }; 1400 1401 mipidcphy0_grf: syscon@26034000 { 1402 compatible = "rockchip,rk3576-mipi-dcphy-grf", "syscon"; 1403 reg = <0x0 0x26034000 0x0 0x2000>; 1404 clocks = <&cru PCLK_PMUPHY_ROOT>; 1405 }; 1406 1407 vo1_grf: syscon@26036000 { 1408 compatible = "rockchip,rk3576-vo-grf", "syscon"; 1409 reg = <0x0 0x26036000 0x0 0x100>; 1410 clocks = <&cru PCLK_VO1_ROOT>; 1411 }; 1412 1413 sdgmac_grf: syscon@26038000 { 1414 compatible = "rockchip,rk3576-sdgmac-grf", "syscon"; 1415 reg = <0x0 0x26038000 0x0 0x1000>; 1416 clocks = <&cru PCLK_SDGMAC_ROOT>; 1417 }; 1418 1419 mipidphy0_grf: syscon@2603a000 { 1420 compatible = "rockchip,rk3576-mipi-dphy-grf", "syscon"; 1421 reg = <0x0 0x2603a000 0x0 0x2000>; 1422 clocks = <&cru PCLK_PMUPHY_ROOT>; 1423 }; 1424 1425 ioc_grf: syscon@26040000 { 1426 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd"; 1427 reg = <0x0 0x26040000 0x0 0xc000>; 1428 1429 rgb: rgb { 1430 compatible = "rockchip,rk3576-rgb"; 1431 pinctrl-names = "default"; 1432 status = "disabled"; 1433 1434 ports { 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 1438 port@0 { 1439 reg = <0>; 1440 #address-cells = <1>; 1441 #size-cells = <0>; 1442 1443 rgb_in_vopl: endpoint@0 { 1444 reg = <0>; 1445 remote-endpoint = <&vopl_out_rgb>; 1446 status = "disabled"; 1447 }; 1448 1449 rgb_in_vp1: endpoint@1 { 1450 reg = <1>; 1451 remote-endpoint = <&vp1_out_rgb>; 1452 status = "disabled"; 1453 }; 1454 1455 rgb_in_vp2: endpoint@2 { 1456 reg = <2>; 1457 remote-endpoint = <&vp2_out_rgb>; 1458 status = "disabled"; 1459 }; 1460 }; 1461 }; 1462 }; 1463 }; 1464 1465 mipidphy1_grf: syscon@2604c000 { 1466 compatible = "rockchip,rk3576-mipi-dphy-grf", "syscon"; 1467 reg = <0x0 0x2604c000 0x0 0x2000>; 1468 }; 1469 1470 cru: clock-controller@27200000 { 1471 compatible = "rockchip,rk3576-cru"; 1472 reg = <0x0 0x27200000 0x0 0x50000>; 1473 rockchip,grf = <&pmu0_grf>; 1474 #clock-cells = <1>; 1475 #reset-cells = <1>; 1476 1477 assigned-clocks = 1478 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1479 <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>, 1480 <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>; 1481 assigned-clock-rates = 1482 <1188000000>, <1000000000>, 1483 <786432000>, <18432000>, 1484 <48000000>, <64000000>; 1485 }; 1486 1487 i2c0: i2c@27300000 { 1488 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1489 reg = <0x0 0x27300000 0x0 0x1000>; 1490 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 1491 clock-names = "i2c", "pclk"; 1492 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1493 pinctrl-names = "default"; 1494 pinctrl-0 = <&i2c0m0_xfer>; 1495 resets = <&cru SRST_I2C0>, <&cru SRST_P_I2C0>; 1496 reset-names = "i2c", "apb"; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 status = "disabled"; 1500 }; 1501 1502 uart1: serial@27310000 { 1503 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1504 reg = <0x0 0x27310000 0x0 0x100>; 1505 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1506 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1507 clock-names = "baudclk", "apb_pclk"; 1508 reg-shift = <2>; 1509 reg-io-width = <4>; 1510 dmas = <&dmac0 8>, <&dmac0 9>; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&uart1m0_xfer>; 1513 status = "disabled"; 1514 }; 1515 1516 pwm0_2ch_0: pwm@27330000 { 1517 compatible = "rockchip,rk3576-pwm"; 1518 reg = <0x0 0x27330000 0x0 0x1000>; 1519 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1520 #pwm-cells = <3>; 1521 pinctrl-names = "active"; 1522 pinctrl-0 = <&pwm0m0_ch0>; 1523 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 1524 clock-names = "pwm", "pclk"; 1525 status = "disabled"; 1526 }; 1527 1528 pwm0_2ch_1: pwm@27331000 { 1529 compatible = "rockchip,rk3576-pwm"; 1530 reg = <0x0 0x27331000 0x0 0x1000>; 1531 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1532 #pwm-cells = <3>; 1533 pinctrl-names = "active"; 1534 pinctrl-0 = <&pwm0m0_ch1>; 1535 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 1536 clock-names = "pwm", "pclk"; 1537 status = "disabled"; 1538 }; 1539 1540 pmu: power-management@27380000 { 1541 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd"; 1542 reg = <0x0 0x27380000 0x0 0x800>; 1543 1544 power: power-controller { 1545 compatible = "rockchip,rk3576-power-controller"; 1546 #power-domain-cells = <1>; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 status = "okay"; 1550 1551 /* These power domains are grouped by VD_NPU */ 1552 power-domain@RK3576_PD_NPU { 1553 reg = <RK3576_PD_NPU>; 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 1557 power-domain@RK3576_PD_NPUTOP { 1558 reg = <RK3576_PD_NPUTOP>; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 1562 power-domain@RK3576_PD_NPU0 { 1563 reg = <RK3576_PD_NPU0>; 1564 }; 1565 power-domain@RK3576_PD_NPU1 { 1566 reg = <RK3576_PD_NPU1>; 1567 }; 1568 }; 1569 }; 1570 /* These power domains are grouped by VD_GPU */ 1571 power-domain@RK3576_PD_GPU { 1572 reg = <RK3576_PD_GPU>; 1573 }; 1574 /* These power domains are grouped by VD_LOGIC */ 1575 power-domain@RK3576_PD_NVM { 1576 reg = <RK3576_PD_NVM>; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 1580 power-domain@RK3576_PD_SDGMAC { 1581 reg = <RK3576_PD_SDGMAC>; 1582 }; 1583 }; 1584 power-domain@RK3576_PD_PHP { 1585 reg = <RK3576_PD_PHP>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 1589 power-domain@RK3576_PD_SUBPHP { 1590 reg = <RK3576_PD_SUBPHP>; 1591 }; 1592 }; 1593 power-domain@RK3576_PD_AUDIO { 1594 reg = <RK3576_PD_AUDIO>; 1595 }; 1596 power-domain@RK3576_PD_VEPU1 { 1597 reg = <RK3576_PD_VEPU1>; 1598 }; 1599 power-domain@RK3576_PD_VPU { 1600 reg = <RK3576_PD_VPU>; 1601 }; 1602 power-domain@RK3576_PD_VDEC { 1603 reg = <RK3576_PD_VDEC>; 1604 }; 1605 power-domain@RK3576_PD_VI { 1606 reg = <RK3576_PD_VI>; 1607 #address-cells = <1>; 1608 #size-cells = <0>; 1609 1610 power-domain@RK3576_PD_VEPU0 { 1611 reg = <RK3576_PD_VEPU0>; 1612 }; 1613 }; 1614 power-domain@RK3576_PD_VOP { 1615 reg = <RK3576_PD_VOP>; 1616 #address-cells = <1>; 1617 #size-cells = <0>; 1618 1619 power-domain@RK3576_PD_USB { 1620 reg = <RK3576_PD_USB>; 1621 }; 1622 power-domain@RK3576_PD_VO0 { 1623 reg = <RK3576_PD_VO0>; 1624 }; 1625 power-domain@RK3576_PD_VO1 { 1626 reg = <RK3576_PD_VO1>; 1627 }; 1628 }; 1629 }; 1630 }; 1631 1632 pdm0: pdm@273b0000 { 1633 compatible = "rockchip,rk3576-pdm"; 1634 reg = <0x0 0x273b0000 0x0 0x1000>; 1635 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1636 clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>, <&cru CLK_PDM0_OUT>; 1637 clock-names = "pdm_clk", "pdm_hclk", "pdm_clk_out"; 1638 dmas = <&dmac0 4>; 1639 dma-names = "rx"; 1640 pinctrl-names = "default"; 1641 pinctrl-0 = <&pdm0m0_clk0 1642 &pdm0m0_clk1 1643 &pdm0m0_sdi0 1644 &pdm0m0_sdi1 1645 &pdm0m0_sdi2 1646 &pdm0m0_sdi3>; 1647 power-domains = <&power RK3576_PD_PMU1>; 1648 #sound-dai-cells = <0>; 1649 sound-name-prefix = "PDM0"; 1650 status = "disabled"; 1651 }; 1652 1653 rknpu: npu@27700000 { 1654 compatible = "rockchip,rk3576-rknpu"; 1655 reg = <0x0 0x27700000 0x0 0x8000>, 1656 <0x0 0x27708000 0x0 0x8000>; 1657 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 1659 interrupt-names = "npu0_irq", "npu1_irq"; 1660 clocks = <&cru ACLK_RKNN0>, <&cru ACLK_RKNN1>, <&cru HCLK_RKNN_ROOT>, 1661 <&cru ACLK_RKNN_CBUF>, <&cru HCLK_RKNN_CBUF>; 1662 clock-names = "aclk0", "aclk1", "hclk_root", 1663 "aclk_cbuf", "hclk_cbuf"; 1664 resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, 1665 <&cru SRST_A_RKNN_CBUF>, <&cru SRST_A_RKNN_CBUF>; 1666 reset-names = "srst_a0", "srst_a1", 1667 "srst_a_cbuf", "srst_h_cbuf"; 1668 power-domains = <&power RK3576_PD_NPU0>, <&power RK3576_PD_NPU1>; 1669 power-domain-names = "npu0", "npu1"; 1670 iommus = <&rknpu_mmu>; 1671 status = "disabled"; 1672 }; 1673 1674 rknpu_mmu: iommu@27702000 { 1675 compatible = "rockchip,iommu-v2"; 1676 reg = <0x0 0x27702000 0x0 0x100>, 1677 <0x0 0x27702100 0x0 0x100>, 1678 <0x0 0x2770a000 0x0 0x100>, 1679 <0x0 0x2770a100 0x0 0x100>; 1680 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 1682 interrupt-names = "npu0_mmu", "npu1_mmu"; 1683 clocks = <&cru ACLK_RKNN0>, <&cru ACLK_RKNN1>, <&cru HCLK_RKNN_ROOT>; 1684 clock-names = "aclk0", "aclk1", "iface"; 1685 #iommu-cells = <0>; 1686 status = "disabled"; 1687 }; 1688 1689 gpu: gpu@27800000 { 1690 compatible = "arm,mali-bifrost"; 1691 reg = <0x0 0x27800000 0x0 0x20000>; 1692 1693 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 1696 interrupt-names = "GPU", "MMU", "JOB"; 1697 1698 upthreshold = <40>; 1699 downdifferential = <10>; 1700 1701 clocks = <&cru CLK_GPU>; 1702 clock-names = "clk_mali"; 1703 power-domains = <&power RK3576_PD_GPU>; 1704 operating-points-v2 = <&gpu_opp_table>; 1705 #cooling-cells = <2>; 1706 1707 status = "disabled"; 1708 }; 1709 1710 gpu_opp_table: gpu-opp-table { 1711 compatible = "operating-points-v2"; 1712 1713 opp-300000000 { 1714 opp-hz = /bits/ 64 <300000000>; 1715 opp-microvolt = <850000 850000 850000>; 1716 }; 1717 opp-400000000 { 1718 opp-hz = /bits/ 64 <400000000>; 1719 opp-microvolt = <850000 850000 850000>; 1720 }; 1721 opp-500000000 { 1722 opp-hz = /bits/ 64 <500000000>; 1723 opp-microvolt = <850000 850000 850000>; 1724 }; 1725 opp-600000000 { 1726 opp-hz = /bits/ 64 <600000000>; 1727 opp-microvolt = <850000 850000 850000>; 1728 }; 1729 }; 1730 1731 ebc: ebc@27900000 { 1732 compatible = "rockchip,rk3576-ebc-tcon"; 1733 reg = <0x0 0x27900000 0x0 0x5000>; 1734 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 1735 clocks = <&cru HCLK_EBC>, <&cru ACLK_EBC>, <&cru DCLK_EBC>; 1736 clock-names = "hclk", "aclk", "dclk"; 1737 pinctrl-names = "default"; 1738 pinctrl-0 = <&vo_ebc_pins>; 1739 power-domains = <&power RK3576_PD_VPU>; 1740 rockchip,grf = <&sys_grf>; 1741 status = "disabled"; 1742 }; 1743 1744 vopl: vop@27900000 { 1745 compatible = "rockchip,rk3576-vop-lit"; 1746 reg = <0x0 0x27900000 0x0 0x200>; 1747 reg-names = "regs"; 1748 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 1749 clocks = <&cru ACLK_EBC>, <&cru DCLK_EBC>, <&cru HCLK_EBC>; 1750 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1751 power-domains = <&power RK3576_PD_VPU>; 1752 rockchip,grf = <&ioc_grf>; 1753 rockchip,vo0_grf = <&vo0_grf>; 1754 status = "disabled"; 1755 1756 vopl_out: port { 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 1760 vopl_out_rgb: endpoint@0 { 1761 reg = <0>; 1762 remote-endpoint = <&rgb_in_vopl>; 1763 }; 1764 1765 vopl_out_dsi: endpoint@1 { 1766 reg = <1>; 1767 remote-endpoint = <&dsi_in_vopl>; 1768 }; 1769 1770 vopl_out_edp: endpoint@2 { 1771 reg = <2>; 1772 remote-endpoint = <&edp_in_vopl>; 1773 }; 1774 1775 vopl_out_hdmi: endpoint@3 { 1776 reg = <3>; 1777 remote-endpoint = <&hdmi_in_vopl>; 1778 }; 1779 }; 1780 }; 1781 1782 jpegd: jpegd@27910000 { 1783 compatible = "rockchip,rkv-jpeg-decoder-v1"; 1784 reg = <0x0 0x27910000 0x0 0x330>; 1785 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1786 interrupt-names = "irq_jpegd"; 1787 clocks = <&aclk_jpeg>, <&cru HCLK_JPEG>; 1788 clock-names = "aclk_vcodec", "hclk_vcodec"; 1789 rockchip,normal-rates = <700000000>, <0>; 1790 assigned-clocks = <&aclk_jpeg>; 1791 assigned-clock-rates = <700000000>; 1792 resets = <&cru SRST_A_JPEG>, <&cru SRST_H_JPEG>; 1793 reset-names = "shared_video_a", "shared_video_h"; 1794 rockchip,skip-pmu-idle-request; 1795 iommus = <&jpeg_mmu>; 1796 rockchip,srv = <&mpp_srv>; 1797 rockchip,taskqueue-node = <0>; 1798 rockchip,resetgroup-node = <0>; 1799 power-domains = <&power RK3576_PD_VPU>; 1800 status = "disabled"; 1801 }; 1802 1803 jpege: jpege@27910800 { 1804 compatible = "rockchip,rkv-jpeg-encoder-v1"; 1805 reg = <0x0 0x27910800 0x0 0x13c>; 1806 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1807 interrupt-names = "irq_jpege"; 1808 clocks = <&aclk_jpeg>, <&cru HCLK_JPEG>; 1809 clock-names = "aclk_vcodec", "hclk_vcodec"; 1810 rockchip,normal-rates = <700000000>, <0>; 1811 assigned-clocks = <&aclk_jpeg>; 1812 assigned-clock-rates = <700000000>; 1813 resets = <&cru SRST_A_JPEG>, <&cru SRST_H_JPEG>; 1814 reset-names = "shared_video_a", "shared_video_h"; 1815 rockchip,skip-pmu-idle-request; 1816 iommus = <&jpeg_mmu>; 1817 rockchip,srv = <&mpp_srv>; 1818 rockchip,taskqueue-node = <0>; 1819 rockchip,resetgroup-node = <0>; 1820 power-domains = <&power RK3576_PD_VPU>; 1821 status = "disabled"; 1822 }; 1823 1824 jpeg_mmu: iommu@27910f00 { 1825 compatible = "rockchip,iommu-v2"; 1826 reg = <0x0 0x27910f00 0x0 0x28>; 1827 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1828 interrupt-names = "irq_jpeg_mmu"; 1829 clocks = <&aclk_jpeg>, <&cru HCLK_JPEG>; 1830 clock-name = "aclk", "iface"; 1831 #iommu-cells = <0>; 1832 rockchip,shootdown-entire; 1833 power-domains = <&power RK3576_PD_VPU>; 1834 status = "disabled"; 1835 }; 1836 1837 rga2_core0: rga@27920000 { 1838 compatible = "rockchip,rga2_core0"; 1839 reg = <0x0 0x27920000 0x0 0x1000>; 1840 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1841 interrupt-names = "rga2_core0_irq"; 1842 clocks = <&cru ACLK_RGA2E_0>, <&cru HCLK_RGA2E_0>, <&cru CLK_CORE_RGA2E_0>; 1843 clock-names = "aclk_rga2e_0", "hclk_rga2e_0", "clk_rga2e_0"; 1844 power-domains = <&power RK3576_PD_VPU>; 1845 iommus = <&rga2_core0_mmu>; 1846 status = "disabled"; 1847 }; 1848 1849 rga2_core0_mmu: iommu@27920f00 { 1850 compatible = "rockchip,iommu-v2"; 1851 reg = <0x0 0x27920f00 0x0 0x100>; 1852 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1853 interrupt-names = "rga2_0_mmu"; 1854 clocks = <&cru ACLK_RGA2E_0>, <&cru HCLK_RGA2E_0>; 1855 clock-names = "aclk", "iface"; 1856 power-domains = <&power RK3576_PD_VPU>; 1857 #iommu-cells = <0>; 1858 status = "disabled"; 1859 }; 1860 1861 rga2_core1: rga@27930000 { 1862 compatible = "rockchip,rga2_core1"; 1863 reg = <0x0 0x27930000 0x0 0x1000>; 1864 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1865 interrupt-names = "rga2_core1_irq"; 1866 clocks = <&cru ACLK_RGA2E_1>, <&cru HCLK_RGA2E_1>, <&cru CLK_CORE_RGA2E_1>; 1867 clock-names = "aclk_rga2e_1", "hclk_rga2e_1", "clk_rga2e_1"; 1868 power-domains = <&power RK3576_PD_VPU>; 1869 iommus = <&rga2_core1_mmu>; 1870 status = "disabled"; 1871 }; 1872 1873 rga2_core1_mmu: iommu@27930f00 { 1874 compatible = "rockchip,iommu-v2"; 1875 reg = <0x0 0x27930f00 0x0 0x100>; 1876 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1877 interrupt-names = "rga2_1_mmu"; 1878 clocks = <&cru ACLK_RGA2E_1>, <&cru HCLK_RGA2E_1>; 1879 clock-names = "aclk", "iface"; 1880 power-domains = <&power RK3576_PD_VPU>; 1881 #iommu-cells = <0>; 1882 status = "disabled"; 1883 }; 1884 1885 iep: iep@27960000 { 1886 compatible = "rockchip,iep-v2"; 1887 reg = <0x0 0x27960000 0x0 0x500>; 1888 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 1889 interrupt-names = "irq_vdpp"; 1890 clocks = <&aclk_vdpp>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>; 1891 clock-names = "aclk", "hclk", "sclk"; 1892 rockchip,normal-rates = <340000000>, <0>, <340000000>; 1893 assigned-clocks = <&aclk_vdpp>, <&cru CLK_CORE_VDPP>; 1894 assigned-clock-rates = <340000000>, <340000000>; 1895 resets = <&cru SRST_A_VDPP>, <&cru SRST_H_VDPP>, <&cru SRST_CORE_VDPP>; 1896 reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s"; 1897 rockchip,skip-pmu-idle-request; 1898 rockchip,srv = <&mpp_srv>; 1899 rockchip,taskqueue-node = <2>; 1900 iommus = <&iep_mmu>; 1901 power-domains = <&power RK3576_PD_VPU>; 1902 status = "disabled"; 1903 }; 1904 1905 iep_mmu: iommu@27960800 { 1906 compatible = "rockchip,iommu-v2"; 1907 reg = <0x0 0x27960800 0x0 0x100>; 1908 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 1909 interrupt-names = "iep_mmu"; 1910 clocks = <&aclk_vdpp>, <&cru HCLK_VDPP>; 1911 clock-names = "aclk", "iface"; 1912 #iommu-cells = <0>; 1913 rockchip,shootdown-entire; 1914 power-domains = <&power RK3576_PD_VPU>; 1915 status = "disabled"; 1916 }; 1917 1918 vdpp: vdpp@27961000 { 1919 compatible = "rockchip,vdpp-rk3576"; 1920 reg = <0x0 0x27961000 0x0 0x500>, <0x0 0x27962000 0x0 0x900>; 1921 reg-names = "vdpp_regs", "zme_regs"; 1922 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 1923 interrupt-names = "irq_vdpp"; 1924 clocks = <&aclk_vdpp>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>; 1925 clock-names = "aclk", "hclk", "sclk"; 1926 rockchip,normal-rates = <340000000>, <0>, <340000000>; 1927 assigned-clocks = <&aclk_vdpp>, <&cru CLK_CORE_VDPP>; 1928 assigned-clock-rates = <340000000>, <340000000>; 1929 resets = <&cru SRST_A_VDPP>, <&cru SRST_H_VDPP>, <&cru SRST_CORE_VDPP>; 1930 reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s"; 1931 rockchip,skip-pmu-idle-request; 1932 rockchip,srv = <&mpp_srv>; 1933 rockchip,taskqueue-node = <2>; 1934 rockchip,disable-auto-freq; 1935 iommus = <&iep_mmu>; 1936 power-domains = <&power RK3576_PD_VPU>; 1937 status = "disabled"; 1938 }; 1939 1940 rkvenc0: rkvenc-core@27a00000 { 1941 compatible = "rockchip,rkv-encoder-rk3576-core"; 1942 reg = <0x0 0x27a00000 0x0 0x6000>; 1943 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1944 interrupt-names = "irq_vepu0"; 1945 clocks = <&aclk_vepu0>, <&hclk_vepu0>, <&cru CLK_VEPU0_CORE>; 1946 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1947 rockchip,normal-rates = <400000000>, <0>, <700000000>; 1948 resets = <&cru SRST_A_VEPU0>, <&cru SRST_H_VEPU0>, 1949 <&cru SRST_VEPU0_CORE>; 1950 reset-names = "video_a", "video_h", "video_core"; 1951 assigned-clocks = <&aclk_vepu0>, <&cru CLK_VEPU0_CORE>; 1952 assigned-clock-rates = <400000000>, <700000000>; 1953 iommus = <&rkvenc0_mmu>; 1954 rockchip,srv = <&mpp_srv>; 1955 rockchip,taskqueue-node = <3>; 1956 rockchip,task-capacity = <8>; 1957 rockchip,ccu = <&rkvenc_ccu>; 1958 power-domains = <&power RK3576_PD_VEPU0>; 1959 status = "disabled"; 1960 }; 1961 1962 rkvenc0_mmu: iommu@27a0f000 { 1963 compatible = "rockchip,iommu-v2"; 1964 reg = <0x0 0x27a0f000 0x0 0x40>; 1965 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1966 interrupt-names = "irq_vepu0_mmu"; 1967 clocks = <&aclk_vepu0>, <&hclk_vepu0>; 1968 clock-names = "aclk", "iface"; 1969 #iommu-cells = <0>; 1970 rockchip,shootdown-entire; 1971 rockchip,disable-mmu-reset; 1972 rockchip,enable-cmd-retry; 1973 power-domains = <&power RK3576_PD_VEPU0>; 1974 status = "disabled"; 1975 }; 1976 1977 rkvenc1: rkvenc-core@27a10000 { 1978 compatible = "rockchip,rkv-encoder-rk3576-core"; 1979 reg = <0x0 0x27a10000 0x0 0x6000>; 1980 interrupts = <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>; 1981 interrupt-names = "irq_vepu1"; 1982 clocks = <&cru ACLK_VEPU1>, <&cru HCLK_VEPU1>, <&cru CLK_VEPU1_CORE>; 1983 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1984 rockchip,normal-rates = <400000000>, <0>, <700000000>; 1985 resets = <&cru SRST_A_VEPU1>, <&cru SRST_H_VEPU1>, 1986 <&cru SRST_VEPU1_CORE>; 1987 reset-names = "video_a", "video_h", "video_core"; 1988 assigned-clocks = <&cru ACLK_VEPU1>, <&cru CLK_VEPU1_CORE>; 1989 assigned-clock-rates = <400000000>, <700000000>; 1990 iommus = <&rkvenc1_mmu>; 1991 rockchip,srv = <&mpp_srv>; 1992 rockchip,taskqueue-node = <3>; 1993 rockchip,task-capacity = <8>; 1994 rockchip,ccu = <&rkvenc_ccu>; 1995 power-domains = <&power RK3576_PD_VEPU1>; 1996 status = "disabled"; 1997 }; 1998 1999 rkvenc1_mmu: iommu@27a1f000 { 2000 compatible = "rockchip,iommu-v2"; 2001 reg = <0x0 0x27a1f000 0x0 0x40>; 2002 interrupts = <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>; 2003 interrupt-names = "irq_vepu1_mmu"; 2004 clocks = <&cru ACLK_VEPU1>, <&cru HCLK_VEPU1>; 2005 clock-names = "aclk", "iface"; 2006 #iommu-cells = <0>; 2007 rockchip,disable-mmu-reset; 2008 rockchip,enable-cmd-retry; 2009 rockchip,shootdown-entire; 2010 power-domains = <&power RK3576_PD_VEPU1>; 2011 status = "disabled"; 2012 }; 2013 2014 rkvdec: rkvdec@27b00000 { 2015 compatible = "rockchip,rkv-decoder-v383"; 2016 reg = <0x0 0x27b00100 0x0 0x400>, <0x0 0x27b00000 0x0 0x100>; 2017 reg-names = "regs", "link"; 2018 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 2019 interrupt-names = "irq_rkvdec"; 2020 clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC_ROOT>, 2021 <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>; 2022 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_hevc_ca"; 2023 resets = <&cru SRST_A_RKVDEC_BIU >, <&cru SRST_H_RKVDEC_BIU>, 2024 <&cru SRST_RKVDEC_CORE>, <&cru SRST_RKVDEC_HEVC_CA>; 2025 reset-names = "video_a","video_h", "video_core", "video_hevc_cabac"; 2026 rockchip,normal-rates = <600000000>, <0>, <600000000>, <600000000>; 2027 assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC_ROOT>, 2028 <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>; 2029 assigned-clock-rates = <600000000>,<0>, <600000000>, <600000000>; 2030 iommus = <&rkvdec_mmu>; 2031 rockchip,srv = <&mpp_srv>; 2032 rockchip,task-capacity = <1>; 2033 rockchip,taskqueue-node = <5>; 2034 power-domains = <&power RK3576_PD_VDEC>; 2035 status = "disabled"; 2036 }; 2037 2038 rkvdec_mmu: iommu@27b00800 { 2039 compatible = "rockchip,iommu-v2"; 2040 reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>; 2041 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2042 interrupt-names = "irq_rkvdec_mmu"; 2043 clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>; 2044 clock-names = "aclk", "iface"; 2045 rockchip,disable-mmu-reset; 2046 rockchip,enable-cmd-retry; 2047 rockchip,shootdown-entire; 2048 #iommu-cells = <0>; 2049 power-domains = <&power RK3576_PD_VDEC>; 2050 status = "disabled"; 2051 }; 2052 2053 rkisp: isp@27c00000 { 2054 compatible = "rockchip,rk3576-rkisp"; 2055 reg = <0x0 0x27c00000 0x0 0x7f00>; 2056 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 2059 interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; 2060 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, 2061 <&cru CLK_ISP_CORE>, <&cru CLK_ISP_CORE_MARVIN>, 2062 <&cru CLK_ISP_CORE_VICAP>; 2063 clock-names = "aclk_isp", "hclk_isp", 2064 "clk_isp_core", "clk_isp_core_marvin", 2065 "clk_isp_core_vicap"; 2066 power-domains = <&power RK3576_PD_VI>; 2067 iommus = <&rkisp_mmu>; 2068 status = "disabled"; 2069 }; 2070 2071 rkisp_mmu: iommu@27c07f00 { 2072 compatible = "rockchip,iommu-v2"; 2073 reg = <0x0 0x27c07f00 0x0 0x100>; 2074 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 2075 interrupt-names = "isp_mmu"; 2076 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 2077 clock-names = "aclk", "iface"; 2078 power-domains = <&power RK3576_PD_VI>; 2079 #iommu-cells = <0>; 2080 rockchip,disable-mmu-reset; 2081 status = "disabled"; 2082 }; 2083 2084 rkcif: rkcif@27c10000 { 2085 compatible = "rockchip,rk3576-cif"; 2086 reg = <0x0 0x27c10000 0x0 0x800>; 2087 reg-names = "cif_regs"; 2088 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 2089 interrupt-names = "cif-intr"; 2090 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>, 2091 <&cru CLK_VICAP_I0CLK>, <&cru CLK_VICAP_I1CLK>, 2092 <&cru CLK_VICAP_I2CLK>, <&cru CLK_VICAP_I3CLK>, 2093 <&cru CLK_VICAP_I4CLK>; 2094 clock-names = "aclk_cif", "hclk_cif", "dclk_cif", 2095 "i0clk_cif", "i1clk_cif", 2096 "i2clk_cif", "i3clk_cif", 2097 "i4clk_cif"; 2098 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>, 2099 <&cru SRST_VICAP_I0CLK>, <&cru SRST_VICAP_I1CLK>, 2100 <&cru SRST_VICAP_I2CLK>, <&cru SRST_VICAP_I3CLK>, 2101 <&cru SRST_VICAP_I4CLK>; 2102 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", 2103 "rst_cif_iclk0", "rst_cif_iclk1", "rst_cif_iclk2", 2104 "rst_cif_iclk3", "rst_cif_iclk4"; 2105 assigned-clocks = <&cru DCLK_VICAP>; 2106 assigned-clock-rates = <600000000>; 2107 power-domains = <&power RK3576_PD_VI>; 2108 rockchip,grf = <&sys_grf>; 2109 iommus = <&rkcif_mmu>; 2110 status = "disabled"; 2111 }; 2112 2113 rkcif_mmu: iommu@27c10800 { 2114 compatible = "rockchip,iommu-v2"; 2115 reg = <0x0 0x27c10800 0x0 0x100>; 2116 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 2117 interrupt-names = "cif_mmu"; 2118 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; 2119 clock-names = "aclk", "iface"; 2120 power-domains = <&power RK3576_PD_VI>; 2121 rockchip,disable-mmu-reset; 2122 #iommu-cells = <0>; 2123 status = "disabled"; 2124 }; 2125 2126 rkvpss: vpss@27c30000 { 2127 compatible = "rockchip,rk3576-rkvpss"; 2128 reg = <0x0 0x27c30000 0x0 0x3f00>; 2129 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 2131 interrupt-names = "mi_irq", "vpss_irq"; 2132 clocks = <&cru ACLK_VPSS>, <&cru HCLK_VPSS>, 2133 <&cru CLK_CORE_VPSS>; 2134 clock-names = "aclk_vpss", "hclk_vpss", "clk_vpss"; 2135 power-domains = <&power RK3576_PD_VI>; 2136 iommus = <&rkvpss_mmu>; 2137 status = "disabled"; 2138 }; 2139 2140 rkvpss_mmu: iommu@27c33f00 { 2141 compatible = "rockchip,iommu-v2"; 2142 reg = <0x0 0x27c33f00 0x0 0x100>; 2143 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 2144 interrupt-names = "vpss_mmu"; 2145 clocks = <&cru ACLK_VPSS>, <&cru HCLK_VPSS>; 2146 clock-names = "aclk", "iface"; 2147 power-domains = <&power RK3576_PD_VI>; 2148 #iommu-cells = <0>; 2149 rockchip,disable-mmu-reset; 2150 status = "disabled"; 2151 }; 2152 2153 mipi0_csi2_hw: mipi0-csi2-hw@27c80000 { 2154 compatible = "rockchip,rk3576-mipi-csi2-hw"; 2155 reg = <0x0 0x27c80000 0x0 0x10000>; 2156 reg-names = "csihost_regs"; 2157 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>; 2159 interrupt-names = "csi-intr1", "csi-intr2"; 2160 clocks = <&cru PCLK_CSI_HOST_0>, <&cru ICLK_CSIHOST0>; 2161 clock-names = "pclk_csi2host", "iclk_csi2host"; 2162 resets = <&cru SRST_P_CSI_HOST_0>; 2163 reset-names = "srst_csihost_p"; 2164 status = "okay"; 2165 }; 2166 2167 mipi1_csi2_hw: mipi1-csi2-hw@27c90000 { 2168 compatible = "rockchip,rk3576-mipi-csi2-hw"; 2169 reg = <0x0 0x27c90000 0x0 0x10000>; 2170 reg-names = "csihost_regs"; 2171 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 2173 interrupt-names = "csi-intr1", "csi-intr2"; 2174 clocks = <&cru PCLK_CSI_HOST_1>; 2175 clock-names = "pclk_csi2host"; 2176 resets = <&cru SRST_P_CSI_HOST_1>; 2177 reset-names = "srst_csihost_p"; 2178 status = "okay"; 2179 }; 2180 2181 mipi2_csi2_hw: mipi2-csi2-hw@27ca0000 { 2182 compatible = "rockchip,rk3576-mipi-csi2-hw"; 2183 reg = <0x0 0x27ca0000 0x0 0x10000>; 2184 reg-names = "csihost_regs"; 2185 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 2187 interrupt-names = "csi-intr1", "csi-intr2"; 2188 clocks = <&cru PCLK_CSI_HOST_2>; 2189 clock-names = "pclk_csi2host"; 2190 resets = <&cru SRST_P_CSI_HOST_2>; 2191 reset-names = "srst_csihost_p"; 2192 status = "okay"; 2193 }; 2194 2195 mipi3_csi2_hw: mipi3-csi2-hw@27cb0000 { 2196 compatible = "rockchip,rk3576-mipi-csi2-hw"; 2197 reg = <0x0 0x27cb0000 0x0 0x10000>; 2198 reg-names = "csihost_regs"; 2199 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 2200 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 2201 interrupt-names = "csi-intr1", "csi-intr2"; 2202 clocks = <&cru PCLK_CSI_HOST_3>; 2203 clock-names = "pclk_csi2host"; 2204 resets = <&cru SRST_P_CSI_HOST_3>; 2205 reset-names = "srst_csihost_p"; 2206 status = "okay"; 2207 }; 2208 2209 mipi4_csi2_hw: mipi4-csi2-hw@27cc0000 { 2210 compatible = "rockchip,rk3576-mipi-csi2-hw"; 2211 reg = <0x0 0x27cc0000 0x0 0x10000>; 2212 reg-names = "csihost_regs"; 2213 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>; 2215 interrupt-names = "csi-intr1", "csi-intr2"; 2216 clocks = <&cru PCLK_CSI_HOST_4>; 2217 clock-names = "pclk_csi2host"; 2218 resets = <&cru SRST_P_CSI_HOST_4>; 2219 reset-names = "srst_csihost_p"; 2220 status = "okay"; 2221 }; 2222 2223 vop: vop@27d00000 { 2224 compatible = "rockchip,rk3576-vop"; 2225 reg = <0x0 0x27d00000 0x0 0x3000>, 2226 <0x0 0x27d05000 0x0 0x1000>, 2227 <0x0 0x27d06400 0x0 0x800>, 2228 <0x0 0x27d06c00 0x0 0x300>; 2229 reg-names = "regs", 2230 "gamma_lut", 2231 "acm_regs", 2232 "sharp_regs"; 2233 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 2237 interrupt-names = "vop-sys", 2238 "vop-vp0", 2239 "vop-vp1", 2240 "vop-vp2"; 2241 clocks = <&cru ACLK_VOP>, 2242 <&cru HCLK_VOP>, 2243 <&cru DCLK_VP0_SRC>, 2244 <&cru DCLK_VP1_SRC>, 2245 <&cru DCLK_VP2_SRC>; 2246 clock-names = "aclk_vop", 2247 "hclk_vop", 2248 "dclk_vp0", 2249 "dclk_vp1", 2250 "dclk_vp2"; 2251 iommus = <&vop_mmu>; 2252 power-domains = <&power RK3576_PD_VOP>; 2253 rockchip,grf = <&sys_grf>; 2254 rockchip,ioc-grf = <&ioc_grf>; 2255 rockchip,pmu = <&pmu>; 2256 status = "disabled"; 2257 2258 vop_out: ports { 2259 #address-cells = <1>; 2260 #size-cells = <0>; 2261 2262 vp0: port@0 { 2263 #address-cells = <1>; 2264 #size-cells = <0>; 2265 reg = <0>; 2266 2267 vp0_out_dsi: endpoint@0 { 2268 reg = <0>; 2269 remote-endpoint = <&dsi_in_vp0>; 2270 }; 2271 2272 vp0_out_edp: endpoint@1 { 2273 reg = <1>; 2274 remote-endpoint = <&edp_in_vp0>; 2275 }; 2276 2277 vp0_out_hdmi: endpoint@2 { 2278 reg = <2>; 2279 remote-endpoint = <&hdmi_in_vp0>; 2280 }; 2281 2282 vp0_out_dp0: endpoint@3 { 2283 reg = <3>; 2284 remote-endpoint = <&dp0_in_vp0>; 2285 }; 2286 2287 vp0_out_dp1: endpoint@4 { 2288 reg = <4>; 2289 remote-endpoint = <&dp1_in_vp0>; 2290 }; 2291 2292 vp0_out_dp2: endpoint@5 { 2293 reg = <5>; 2294 remote-endpoint = <&dp2_in_vp0>; 2295 }; 2296 }; 2297 2298 vp1: port@1 { 2299 #address-cells = <1>; 2300 #size-cells = <0>; 2301 reg = <1>; 2302 2303 vp1_out_rgb: endpoint@0 { 2304 reg = <0>; 2305 remote-endpoint = <&rgb_in_vp1>; 2306 }; 2307 2308 vp1_out_dsi: endpoint@1 { 2309 reg = <1>; 2310 remote-endpoint = <&dsi_in_vp1>; 2311 }; 2312 2313 vp1_out_edp: endpoint@2 { 2314 reg = <2>; 2315 remote-endpoint = <&edp_in_vp1>; 2316 }; 2317 2318 vp1_out_hdmi: endpoint@3 { 2319 reg = <3>; 2320 remote-endpoint = <&hdmi_in_vp1>; 2321 }; 2322 2323 vp1_out_dp0: endpoint@4 { 2324 reg = <4>; 2325 remote-endpoint = <&dp0_in_vp1>; 2326 }; 2327 2328 vp1_out_dp1: endpoint@5 { 2329 reg = <5>; 2330 remote-endpoint = <&dp1_in_vp1>; 2331 }; 2332 2333 vp1_out_dp2: endpoint@6 { 2334 reg = <6>; 2335 remote-endpoint = <&dp2_in_vp1>; 2336 }; 2337 }; 2338 2339 vp2: port@2 { 2340 #address-cells = <1>; 2341 #size-cells = <0>; 2342 reg = <2>; 2343 2344 vp2_out_rgb: endpoint@0 { 2345 reg = <0>; 2346 remote-endpoint = <&rgb_in_vp2>; 2347 }; 2348 2349 vp2_out_dsi: endpoint@1 { 2350 reg = <1>; 2351 remote-endpoint = <&dsi_in_vp2>; 2352 }; 2353 2354 vp2_out_edp: endpoint@2 { 2355 reg = <2>; 2356 remote-endpoint = <&edp_in_vp2>; 2357 }; 2358 2359 vp2_out_hdmi: endpoint@3 { 2360 reg = <3>; 2361 remote-endpoint = <&hdmi_in_vp2>; 2362 }; 2363 2364 vp2_out_dp0: endpoint@4 { 2365 reg = <4>; 2366 remote-endpoint = <&dp0_in_vp2>; 2367 }; 2368 2369 vp2_out_dp1: endpoint@5 { 2370 reg = <5>; 2371 remote-endpoint = <&dp1_in_vp2>; 2372 }; 2373 2374 vp2_out_dp2: endpoint@6 { 2375 reg = <6>; 2376 remote-endpoint = <&dp2_in_vp2>; 2377 }; 2378 }; 2379 }; 2380 }; 2381 2382 vop_mmu: iommu@27d07e00 { 2383 compatible = "rockchip,iommu-v2"; 2384 reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; 2385 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 2386 interrupt-names = "vop_mmu"; 2387 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 2388 clock-names = "aclk", "iface"; 2389 #iommu-cells = <0>; 2390 rockchip,disable-device-link-resume; 2391 rockchip,shootdown-entire; 2392 status = "disabled"; 2393 }; 2394 2395 spdif_tx2: spdif-tx@27d20000 { 2396 compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; 2397 reg = <0x0 0x27d20000 0x0 0x1000>; 2398 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 2399 clocks = <&cru MCLK_SPDIF_TX2>, <&cru HCLK_SPDIF_TX2>; 2400 clock-names = "mclk", "hclk"; 2401 dmas = <&dmac2 28>; 2402 dma-names = "tx"; 2403 power-domains = <&power RK3576_PD_VO0>; 2404 #sound-dai-cells = <0>; 2405 status = "disabled"; 2406 }; 2407 2408 spdif_rx2: spdif-rx@27d30000 { 2409 compatible = "rockchip,rk3576-spdifrx", "rockchip,rk3308-spdifrx"; 2410 reg = <0x0 0x27d30000 0x0 0x1000>; 2411 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 2412 clocks = <&cru MCLK_SPDIF_RX2>, <&cru HCLK_SPDIF_RX2>; 2413 clock-names = "mclk", "hclk"; 2414 dmas = <&dmac2 27>; 2415 dma-names = "rx"; 2416 power-domains = <&power RK3576_PD_VO0>; 2417 resets = <&cru SRST_M_SPDIF_RX2>; 2418 reset-names = "spdifrx-m"; 2419 status = "disabled"; 2420 }; 2421 2422 sai5: sai@27d40000 { 2423 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 2424 reg = <0x0 0x27d40000 0x0 0x1000>; 2425 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 2426 clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>; 2427 clock-names = "mclk", "hclk"; 2428 dmas = <&dmac2 3>; 2429 dma-names = "rx"; 2430 power-domains = <&power RK3576_PD_VO0>; 2431 resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>; 2432 reset-names = "m", "h"; 2433 #sound-dai-cells = <0>; 2434 sound-name-prefix = "SAI5"; 2435 status = "disabled"; 2436 }; 2437 2438 sai6: sai@27d50000 { 2439 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 2440 reg = <0x0 0x27d50000 0x0 0x1000>; 2441 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 2442 clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>; 2443 clock-names = "mclk", "hclk"; 2444 dmas = <&dmac2 4>, <&dmac2 5>; 2445 dma-names = "tx", "rx"; 2446 power-domains = <&power RK3576_PD_VO0>; 2447 resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>; 2448 reset-names = "m", "h"; 2449 #sound-dai-cells = <0>; 2450 sound-name-prefix = "SAI6"; 2451 status = "disabled"; 2452 }; 2453 2454 dsi: dsi@27d80000 { 2455 compatible = "rockchip,rk3576-mipi-dsi2"; 2456 reg = <0x0 0x27d80000 0x0 0x10000>; 2457 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 2458 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; 2459 clock-names = "pclk", "sys_clk"; 2460 resets = <&cru SRST_P_DSIHOST0>; 2461 reset-names = "apb"; 2462 power-domains = <&power RK3576_PD_VO0>; 2463 phys = <&mipidcphy0>; 2464 phy-names = "dcphy"; 2465 rockchip,grf = <&vo0_grf>; 2466 #address-cells = <1>; 2467 #size-cells = <0>; 2468 status = "disabled"; 2469 2470 ports { 2471 #address-cells = <1>; 2472 #size-cells = <0>; 2473 2474 dsi_in: port@0 { 2475 reg = <0>; 2476 #address-cells = <1>; 2477 #size-cells = <0>; 2478 2479 dsi_in_vp0: endpoint@0 { 2480 reg = <0>; 2481 remote-endpoint = <&vp0_out_dsi>; 2482 status = "disabled"; 2483 }; 2484 2485 dsi_in_vp1: endpoint@1 { 2486 reg = <1>; 2487 remote-endpoint = <&vp1_out_dsi>; 2488 status = "disabled"; 2489 }; 2490 2491 dsi_in_vp2: endpoint@2 { 2492 reg = <2>; 2493 remote-endpoint = <&vp2_out_dsi>; 2494 status = "disabled"; 2495 }; 2496 2497 dsi_in_vopl: endpoint@3 { 2498 reg = <3>; 2499 remote-endpoint = <&vopl_out_dsi>; 2500 status = "disabled"; 2501 }; 2502 }; 2503 }; 2504 }; 2505 2506 hdcp0: hdcp@27d90000 { 2507 compatible = "rockchip,rk3576-hdcp"; 2508 reg = <0x0 0x27d90000 0x0 0x80>; 2509 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2510 clocks = <&aclk_hdcp0>, <&cru PCLK_HDCP0>, 2511 <&cru HCLK_HDCP0>, <&scmi_clk HCLK_HDCP_KEY0>, 2512 <&scmi_clk PCLK_HDCP0_TRNG>; 2513 clock-names = "aclk", "pclk", "hclk", "hclk_key", "pclk_trng"; 2514 resets = <&cru SRST_HDCP0>, <&cru SRST_H_HDCP0>, 2515 <&cru SRST_A_HDCP0>; 2516 reset-names = "hdcp", "h_hdcp", "a_hdcp"; 2517 power-domains = <&power RK3576_PD_VO0>; 2518 rockchip,vo-grf = <&vo0_grf>; 2519 status = "disabled"; 2520 }; 2521 2522 hdmi: hdmi@27da0000 { 2523 compatible = "rockchip,rk3576-dw-hdmi"; 2524 reg = <0x0 0x27da0000 0x0 0x10000>, <0x0 0x27db0000 0x0 0x10000>; 2525 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2526 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2527 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2528 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2529 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 2530 clocks = <&cru PCLK_HDMITX0>, 2531 <&cru CLK_HDMITXHPD>, 2532 <&cru CLK_HDMITX0_EARC>, 2533 <&cru CLK_HDMITX0_REF>, 2534 <&cru MCLK_SAI5_8CH>, 2535 <&cru DCLK_VP0>, 2536 <&cru DCLK_VP1>, 2537 <&cru DCLK_VP2>, 2538 <&cru DCLK_EBC>, 2539 <&hclk_vo1>, 2540 <&hdptxphy_hdmi>; 2541 clock-names = "pclk", 2542 "hpd", 2543 "earc", 2544 "hdmitx_ref", 2545 "aud", 2546 "dclk_vp0", 2547 "dclk_vp1", 2548 "dclk_vp2", 2549 "dclk_ebc", 2550 "hclk_vo1", 2551 "link_clk"; 2552 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHPD>; 2553 reset-names = "ref", "hdp"; 2554 power-domains = <&power RK3576_PD_VO0>; 2555 pinctrl-names = "default"; 2556 pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; 2557 reg-io-width = <4>; 2558 rockchip,grf = <&sys_grf>; 2559 rockchip,vo1_grf = <&vo0_grf>; 2560 phys = <&hdptxphy_hdmi>; 2561 phy-names = "hdmi"; 2562 #sound-dai-cells = <0>; 2563 status = "disabled"; 2564 2565 ports { 2566 #address-cells = <1>; 2567 #size-cells = <0>; 2568 2569 hdmi_in: port@0 { 2570 reg = <0>; 2571 #address-cells = <1>; 2572 #size-cells = <0>; 2573 2574 hdmi_in_vp0: endpoint@0 { 2575 reg = <0>; 2576 remote-endpoint = <&vp0_out_hdmi>; 2577 status = "disabled"; 2578 }; 2579 2580 hdmi_in_vp1: endpoint@1 { 2581 reg = <1>; 2582 remote-endpoint = <&vp1_out_hdmi>; 2583 status = "disabled"; 2584 }; 2585 2586 hdmi_in_vp2: endpoint@2 { 2587 reg = <2>; 2588 remote-endpoint = <&vp2_out_hdmi>; 2589 status = "disabled"; 2590 }; 2591 2592 hdmi_in_vopl: endpoint@3 { 2593 reg = <3>; 2594 remote-endpoint = <&vopl_out_hdmi>; 2595 status = "disabled"; 2596 }; 2597 }; 2598 }; 2599 }; 2600 2601 edp: edp@27dc0000 { 2602 compatible = "rockchip,rk3576-edp"; 2603 reg = <0x0 0x27dc0000 0x0 0x1000>; 2604 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 2605 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, 2606 <&cru CLK_EDP0_200M>, <&hclk_vo0>; 2607 clock-names = "dp", "pclk", "spdif", "hclk"; 2608 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; 2609 reset-names = "dp", "apb"; 2610 phys = <&hdptxphy>; 2611 phy-names = "dp"; 2612 power-domains = <&power RK3576_PD_VO0>; 2613 rockchip,grf = <&vo0_grf>; 2614 status = "disabled"; 2615 2616 ports { 2617 #address-cells = <1>; 2618 #size-cells = <0>; 2619 2620 port@0 { 2621 reg = <0>; 2622 #address-cells = <1>; 2623 #size-cells = <0>; 2624 2625 edp_in_vp0: endpoint@0 { 2626 reg = <0>; 2627 remote-endpoint = <&vp0_out_edp>; 2628 status = "disabled"; 2629 }; 2630 2631 edp_in_vp1: endpoint@1 { 2632 reg = <1>; 2633 remote-endpoint = <&vp1_out_edp>; 2634 status = "disabled"; 2635 }; 2636 2637 edp_in_vp2: endpoint@2 { 2638 reg = <2>; 2639 remote-endpoint = <&vp2_out_edp>; 2640 status = "disabled"; 2641 }; 2642 2643 edp_in_vopl: endpoint@3 { 2644 reg = <3>; 2645 remote-endpoint = <&vopl_out_edp>; 2646 status = "disabled"; 2647 }; 2648 }; 2649 }; 2650 }; 2651 2652 dp: dp@27e40000 { 2653 compatible = "rockchip,rk3576-dp"; 2654 reg = <0x0 0x27e40000 0x0 0x30000>; 2655 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 2656 clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16MHZ_0>, 2657 <&cru ACLK_DP0>; 2658 clock-names = "apb", "aux", "hdcp"; 2659 assigned-clocks = <&cru CLK_AUX16MHZ_0>; 2660 assigned-clock-rates = <16000000>; 2661 resets = <&cru SRST_DP0>; 2662 phys = <&usbdp_phy_dp>; 2663 power-domains = <&power RK3576_PD_VO1>; 2664 status = "disabled"; 2665 2666 dp0: dp0 { 2667 ports { 2668 #address-cells = <1>; 2669 #size-cells = <0>; 2670 2671 port@0 { 2672 reg = <0>; 2673 #address-cells = <1>; 2674 #size-cells = <0>; 2675 2676 dp0_in_vp0: endpoint@0 { 2677 reg = <0>; 2678 remote-endpoint = <&vp0_out_dp0>; 2679 status = "disabled"; 2680 }; 2681 2682 dp0_in_vp1: endpoint@1 { 2683 reg = <1>; 2684 remote-endpoint = <&vp1_out_dp0>; 2685 status = "disabled"; 2686 }; 2687 2688 dp0_in_vp2: endpoint@2 { 2689 reg = <2>; 2690 remote-endpoint = <&vp2_out_dp0>; 2691 status = "disabled"; 2692 }; 2693 }; 2694 }; 2695 }; 2696 2697 dp1: dp1 { 2698 ports { 2699 #address-cells = <1>; 2700 #size-cells = <0>; 2701 2702 port@0 { 2703 reg = <0>; 2704 #address-cells = <1>; 2705 #size-cells = <0>; 2706 2707 dp1_in_vp0: endpoint@0 { 2708 reg = <0>; 2709 remote-endpoint = <&vp0_out_dp1>; 2710 status = "disabled"; 2711 }; 2712 2713 dp1_in_vp1: endpoint@1 { 2714 reg = <1>; 2715 remote-endpoint = <&vp1_out_dp1>; 2716 status = "disabled"; 2717 }; 2718 2719 dp1_in_vp2: endpoint@2 { 2720 reg = <2>; 2721 remote-endpoint = <&vp2_out_dp1>; 2722 status = "disabled"; 2723 }; 2724 }; 2725 }; 2726 }; 2727 2728 dp2: dp2 { 2729 ports { 2730 #address-cells = <1>; 2731 #size-cells = <0>; 2732 port@0 { 2733 reg = <0>; 2734 #address-cells = <1>; 2735 #size-cells = <0>; 2736 2737 dp2_in_vp0: endpoint@0 { 2738 reg = <0>; 2739 remote-endpoint = <&vp0_out_dp2>; 2740 status = "disabled"; 2741 }; 2742 2743 dp2_in_vp1: endpoint@1 { 2744 reg = <1>; 2745 remote-endpoint = <&vp1_out_dp2>; 2746 status = "disabled"; 2747 }; 2748 2749 dp2_in_vp2: endpoint@2 { 2750 reg = <2>; 2751 remote-endpoint = <&vp2_out_dp2>; 2752 status = "disabled"; 2753 }; 2754 }; 2755 }; 2756 }; 2757 }; 2758 2759 hdcp1: hdcp@27e70000 { 2760 compatible = "rockchip,rk3576-hdcp"; 2761 reg = <0x0 0x27e70000 0x0 0x80>; 2762 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 2763 clocks = <&aclk_hdcp1>, <&cru PCLK_HDCP1>, 2764 <&cru HCLK_HDCP1>, <&scmi_clk HCLK_HDCP_KEY1>, 2765 <&scmi_clk PCLK_HDCP1_TRNG>; 2766 clock-names = "aclk", "pclk", "hclk", "hclk_key", "pclk_trng"; 2767 resets = <&cru SRST_HDCP1>, <&cru SRST_H_HDCP1>, 2768 <&cru SRST_A_HDCP1>; 2769 reset-names = "hdcp", "h_hdcp", "a_hdcp"; 2770 power-domains = <&power RK3576_PD_VO1>; 2771 rockchip,vo-grf = <&vo1_grf>; 2772 status = "disabled"; 2773 }; 2774 2775 spdif_tx3: spdif-tx@27ea0000 { 2776 compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; 2777 reg = <0x0 0x27ea0000 0x0 0x1000>; 2778 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 2779 clocks = <&cru MCLK_SPDIF_TX3>, <&cru HCLK_SPDIF_TX3>; 2780 clock-names = "mclk", "hclk"; 2781 dmas = <&dmac2 29>; 2782 dma-names = "tx"; 2783 power-domains = <&power RK3576_PD_VO1>; 2784 #sound-dai-cells = <0>; 2785 status = "disabled"; 2786 }; 2787 2788 spdif_tx4: spdif-tx@27eb0000 { 2789 compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; 2790 reg = <0x0 0x27eb0000 0x0 0x1000>; 2791 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 2792 clocks = <&cru MCLK_SPDIF_TX4>, <&cru HCLK_SPDIF_TX4>; 2793 clock-names = "mclk", "hclk"; 2794 dmas = <&dmac1 6>; 2795 dma-names = "tx"; 2796 power-domains = <&power RK3576_PD_VO1>; 2797 #sound-dai-cells = <0>; 2798 status = "disabled"; 2799 }; 2800 2801 spdif_tx5: spdif-tx@27ec0000 { 2802 compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; 2803 reg = <0x0 0x27ec0000 0x0 0x1000>; 2804 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 2805 clocks = <&cru MCLK_SPDIF_TX5>, <&cru HCLK_SPDIF_TX5>; 2806 clock-names = "mclk", "hclk"; 2807 dmas = <&dmac0 25>; 2808 dma-names = "tx"; 2809 power-domains = <&power RK3576_PD_VO1>; 2810 #sound-dai-cells = <0>; 2811 status = "disabled"; 2812 }; 2813 2814 sai7: sai@27ed0000 { 2815 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 2816 reg = <0x0 0x27ed0000 0x0 0x1000>; 2817 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 2818 clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>; 2819 clock-names = "mclk", "hclk"; 2820 dmas = <&dmac2 19>; 2821 dma-names = "tx"; 2822 power-domains = <&power RK3576_PD_VO1>; 2823 resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>; 2824 reset-names = "m", "h"; 2825 #sound-dai-cells = <0>; 2826 sound-name-prefix = "SAI7"; 2827 status = "disabled"; 2828 }; 2829 2830 sai8: sai@27ee0000 { 2831 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 2832 reg = <0x0 0x27ee0000 0x0 0x1000>; 2833 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 2834 clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>; 2835 clock-names = "mclk", "hclk"; 2836 dmas = <&dmac1 7>; 2837 dma-names = "tx"; 2838 power-domains = <&power RK3576_PD_VO1>; 2839 resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>; 2840 reset-names = "m", "h"; 2841 #sound-dai-cells = <0>; 2842 sound-name-prefix = "SAI8"; 2843 status = "disabled"; 2844 }; 2845 2846 sai9: sai@27ef0000 { 2847 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 2848 reg = <0x0 0x27ef0000 0x0 0x1000>; 2849 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2850 clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>; 2851 clock-names = "mclk", "hclk"; 2852 dmas = <&dmac0 26>; 2853 dma-names = "tx"; 2854 power-domains = <&power RK3576_PD_VO1>; 2855 resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>; 2856 reset-names = "m", "h"; 2857 #sound-dai-cells = <0>; 2858 sound-name-prefix = "SAI9"; 2859 status = "disabled"; 2860 }; 2861 2862 pcie0: pcie@2a200000 { 2863 compatible = "rockchip,rk3576-pcie", "snps,dw-pcie"; 2864 #address-cells = <3>; 2865 #size-cells = <2>; 2866 bus-range = <0x0 0xf>; 2867 clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, 2868 <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, 2869 <&cru CLK_PCIE0_AUX>; 2870 clock-names = "aclk_mst", "aclk_slv", 2871 "aclk_dbi", "pclk", 2872 "aux"; 2873 device_type = "pci"; 2874 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 2875 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 2876 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 2877 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 2878 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 2879 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 2880 #interrupt-cells = <1>; 2881 interrupt-map-mask = <0 0 0 7>; 2882 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 2883 <0 0 0 2 &pcie0_intc 1>, 2884 <0 0 0 3 &pcie0_intc 2>, 2885 <0 0 0 4 &pcie0_intc 3>; 2886 linux,pci-domain = <0>; 2887 num-ib-windows = <8>; 2888 num-viewport = <8>; 2889 num-ob-windows = <2>; 2890 max-link-speed = <2>; 2891 num-lanes = <1>; 2892 phys = <&combphy0_ps PHY_TYPE_PCIE>; 2893 phy-names = "pcie-phy"; 2894 power-domains = <&power RK3576_PD_PHP>; 2895 ranges = <0x81000000 0x0 0x20000000 0x0 0x20000000 0x0 0x00100000 2896 0x82000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00f00000 2897 0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; 2898 reg = <0x0 0x2a200000 0x0 0x00010000>, 2899 <0x0 0x22000000 0x0 0x00400000>, 2900 <0x0 0x20000000 0x0 0x00100000>; 2901 reg-names = "pcie-apb", "pcie-dbi", "config"; 2902 resets = <&cru SRST_PCIE0_POWER_UP>; 2903 reset-names = "pipe"; 2904 status = "disabled"; 2905 2906 pcie0_intc: legacy-interrupt-controller { 2907 interrupt-controller; 2908 #address-cells = <0>; 2909 #interrupt-cells = <1>; 2910 interrupt-parent = <&gic>; 2911 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; 2912 }; 2913 }; 2914 2915 pcie1: pcie@2a210000 { 2916 compatible = "rockchip,rk3576-pcie", "snps,dw-pcie"; 2917 #address-cells = <3>; 2918 #size-cells = <2>; 2919 bus-range = <0x20 0x2f>; 2920 clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, 2921 <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, 2922 <&cru CLK_PCIE1_AUX>; 2923 clock-names = "aclk_mst", "aclk_slv", 2924 "aclk_dbi", "pclk", 2925 "aux"; 2926 device_type = "pci"; 2927 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2928 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2929 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 2930 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2931 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 2932 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 2933 #interrupt-cells = <1>; 2934 interrupt-map-mask = <0 0 0 7>; 2935 interrupt-map = <0 0 0 1 &pcie1_intc 0>, 2936 <0 0 0 2 &pcie1_intc 1>, 2937 <0 0 0 3 &pcie1_intc 2>, 2938 <0 0 0 4 &pcie1_intc 3>; 2939 linux,pci-domain = <0>; 2940 num-ib-windows = <8>; 2941 num-viewport = <8>; 2942 num-ob-windows = <2>; 2943 max-link-speed = <2>; 2944 num-lanes = <1>; 2945 phys = <&combphy1_psu PHY_TYPE_PCIE>; 2946 phy-names = "pcie-phy"; 2947 power-domains = <&power RK3576_PD_SUBPHP>; 2948 ranges = <0x81000000 0x0 0x21000000 0x0 0x21000000 0x0 0x00100000 2949 0x82000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00f00000 2950 0x83000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; 2951 reg = <0x0 0x2a210000 0x0 0x00010000>, 2952 <0x0 0x22400000 0x0 0x00400000>, 2953 <0x0 0x21000000 0x0 0x00100000>; 2954 reg-names = "pcie-apb", "pcie-dbi", "config"; 2955 resets = <&cru SRST_PCIE1_POWER_UP>; 2956 reset-names = "pipe"; 2957 status = "disabled"; 2958 2959 pcie1_intc: legacy-interrupt-controller { 2960 interrupt-controller; 2961 #address-cells = <0>; 2962 #interrupt-cells = <1>; 2963 interrupt-parent = <&gic>; 2964 interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>; 2965 }; 2966 }; 2967 2968 gmac0: ethernet@2a220000 { 2969 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 2970 reg = <0x0 0x2a220000 0x0 0x10000>; 2971 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 2972 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2973 interrupt-names = "macirq", "eth_wake_irq"; 2974 rockchip,grf = <&sdgmac_grf>; 2975 rockchip,php_grf = <&ioc_grf>; 2976 clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>, 2977 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 2978 <&cru CLK_GMAC0_PTP_REF>; 2979 clock-names = "stmmaceth", "clk_mac_ref", 2980 "pclk_mac", "aclk_mac", 2981 "ptp_ref"; 2982 resets = <&cru SRST_A_GMAC0>; 2983 reset-names = "stmmaceth"; 2984 power-domains = <&power RK3576_PD_SDGMAC>; 2985 2986 snps,mixed-burst; 2987 snps,tso; 2988 2989 snps,axi-config = <&gmac0_stmmac_axi_setup>; 2990 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 2991 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 2992 status = "disabled"; 2993 2994 mdio0: mdio { 2995 compatible = "snps,dwmac-mdio"; 2996 #address-cells = <0x1>; 2997 #size-cells = <0x0>; 2998 }; 2999 3000 gmac0_stmmac_axi_setup: stmmac-axi-config { 3001 snps,wr_osr_lmt = <4>; 3002 snps,rd_osr_lmt = <8>; 3003 snps,blen = <0 0 0 0 16 8 4>; 3004 }; 3005 3006 gmac0_mtl_rx_setup: rx-queues-config { 3007 snps,rx-queues-to-use = <1>; 3008 queue0 {}; 3009 }; 3010 3011 gmac0_mtl_tx_setup: tx-queues-config { 3012 snps,tx-queues-to-use = <1>; 3013 queue0 {}; 3014 }; 3015 }; 3016 3017 gmac1: ethernet@2a230000 { 3018 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 3019 reg = <0x0 0x2a230000 0x0 0x10000>; 3020 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 3021 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 3022 interrupt-names = "macirq", "eth_wake_irq"; 3023 rockchip,grf = <&sdgmac_grf>; 3024 rockchip,php_grf = <&ioc_grf>; 3025 clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>, 3026 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 3027 <&cru CLK_GMAC1_PTP_REF>; 3028 clock-names = "stmmaceth", "clk_mac_ref", 3029 "pclk_mac", "aclk_mac", 3030 "ptp_ref"; 3031 resets = <&cru SRST_A_GMAC1>; 3032 reset-names = "stmmaceth"; 3033 power-domains = <&power RK3576_PD_SDGMAC>; 3034 3035 snps,mixed-burst; 3036 snps,tso; 3037 3038 snps,axi-config = <&gmac1_stmmac_axi_setup>; 3039 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 3040 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 3041 status = "disabled"; 3042 3043 mdio1: mdio { 3044 compatible = "snps,dwmac-mdio"; 3045 #address-cells = <0x1>; 3046 #size-cells = <0x0>; 3047 }; 3048 3049 gmac1_stmmac_axi_setup: stmmac-axi-config { 3050 snps,wr_osr_lmt = <4>; 3051 snps,rd_osr_lmt = <8>; 3052 snps,blen = <0 0 0 0 16 8 4>; 3053 }; 3054 3055 gmac1_mtl_rx_setup: rx-queues-config { 3056 snps,rx-queues-to-use = <1>; 3057 queue0 {}; 3058 }; 3059 3060 gmac1_mtl_tx_setup: tx-queues-config { 3061 snps,tx-queues-to-use = <1>; 3062 queue0 {}; 3063 }; 3064 }; 3065 3066 sata0: sata@2a240000 { 3067 compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; 3068 reg = <0 0x2a240000 0 0x1000>; 3069 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 3070 <&cru CLK_RXOOB0>; 3071 clock-names = "sata", "pmalive", "rxoob"; 3072 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 3073 interrupt-names = "hostc"; 3074 power-domains = <&power RK3576_PD_SUBPHP>; 3075 phys = <&combphy0_ps PHY_TYPE_SATA>; 3076 phy-names = "sata-phy"; 3077 ports-implemented = <0x1>; 3078 status = "disabled"; 3079 }; 3080 3081 sata1: sata@2a250000 { 3082 compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; 3083 reg = <0 0x2a250000 0 0x1000>; 3084 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 3085 <&cru CLK_RXOOB1>; 3086 clock-names = "sata", "pmalive", "rxoob"; 3087 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 3088 interrupt-names = "hostc"; 3089 power-domains = <&power RK3576_PD_SUBPHP>; 3090 phys = <&combphy1_psu PHY_TYPE_SATA>; 3091 phy-names = "sata-phy"; 3092 ports-implemented = <0x1>; 3093 status = "disabled"; 3094 }; 3095 3096 mmu0: iommu@2a260000 { 3097 compatible = "rockchip,iommu-v2"; 3098 reg = <0x0 0x2a260000 0x0 0x100>; 3099 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 3100 interrupt-names = "mmu0"; 3101 clocks = <&cru ACLK_MMU0>, <&cru ACLK_SLV_MMU0>, <&cru PCLK_PHP_ROOT>; 3102 clock-names = "aclk", "iface", "root"; 3103 power-domains = <&power RK3576_PD_PHP>; 3104 #iommu-cells = <0>; 3105 status = "disabled"; 3106 }; 3107 3108 mmu1: iommu@2a270000 { 3109 compatible = "rockchip,iommu-v2"; 3110 reg = <0x0 0x2a270000 0x0 0x100>; 3111 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 3112 interrupt-names = "mmu1"; 3113 clocks = <&cru ACLK_MMU1>, <&cru ACLK_SLV_MMU1>, <&cru PCLK_PHP_ROOT>; 3114 clock-names = "aclk", "iface", "root"; 3115 power-domains = <&power RK3576_PD_PHP>; 3116 #iommu-cells = <0>; 3117 status = "disabled"; 3118 }; 3119 3120 mmu2: iommu@2a2c0000 { 3121 compatible = "rockchip,iommu-v2"; 3122 reg = <0x0 0x2a2c0000 0x0 0x100>; 3123 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 3124 interrupt-names = "mmu2"; 3125 clocks = <&cru ACLK_MMU2>, <&cru ACLK_SLV_MMU2>, <&cru PCLK_USB_ROOT>; 3126 clock-names = "aclk", "iface", "root"; 3127 power-domains = <&power RK3576_PD_USB>; 3128 #iommu-cells = <0>; 3129 status = "disabled"; 3130 }; 3131 3132 ufs: ufs@2a2d0000 { 3133 compatible = "rockchip,rk3576-ufs"; 3134 reg = <0x0 0x2a2d0000 0 0x10000>, /* 0: HCI standard */ 3135 <0x0 0x2b040000 0 0x10000>, /* 1: Mphy */ 3136 <0x0 0x2601f000 0 0x1000>, /* 2: HCI Vendor specified */ 3137 <0x0 0x2603c000 0 0x1000>, /* 3: Mphy Vendor specified */ 3138 <0x0 0x2a2e0000 0 0x10000>; /* 4: HCI apb */ 3139 reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; 3140 clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, 3141 <&cru CLK_REF_UFS_CLKOUT>; 3142 clock-names = "core", "pclk", "pclk_mphy", 3143 "ref_out"; 3144 assigned-clocks = <&cru CLK_REF_OSC_MPHY>; 3145 assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; 3146 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 3147 power-domains = <&power RK3576_PD_USB>; 3148 pinctrl-0 = <&ufs_rst &ufs_refclk>; 3149 pinctrl-names = "default"; 3150 resets = <&cru SRST_A_UFS_BIU>; 3151 reset-names = "rst"; 3152 status = "disabled"; 3153 }; 3154 3155 sfc1: spi@2a300000 { 3156 compatible = "rockchip,sfc"; 3157 reg = <0x0 0x2a300000 0x0 0x4000>; 3158 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 3159 clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; 3160 clock-names = "clk_sfc", "hclk_sfc"; 3161 assigned-clocks = <&cru SCLK_FSPI1_X2>; 3162 assigned-clock-rates = <80000000>; 3163 #address-cells = <1>; 3164 #size-cells = <0>; 3165 status = "disabled"; 3166 }; 3167 3168 sdmmc: mmc@2a310000 { 3169 compatible = "rockchip,rk3576-dw-mshc", 3170 "rockchip,rk3288-dw-mshc"; 3171 reg = <0x0 0x2a310000 0x0 0x4000>; 3172 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 3173 max-frequency = <200000000>; 3174 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; 3175 clock-names = "biu", "ciu"; 3176 fifo-depth = <0x100>; 3177 pinctrl-names = "default"; 3178 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>; 3179 resets = <&cru SRST_H_SDMMC0>; 3180 reset-names = "reset"; 3181 rockchip,use-v2-tuning; 3182 status = "disabled"; 3183 }; 3184 3185 sdio: mmc@2a320000 { 3186 compatible = "rockchip,rk3576-dw-mshc", 3187 "rockchip,rk3288-dw-mshc"; 3188 reg = <0x0 0x2a320000 0x0 0x4000>; 3189 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 3190 max-frequency = <200000000>; 3191 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>; 3192 clock-names = "biu", "ciu"; 3193 fifo-depth = <0x100>; 3194 pinctrl-names = "default"; 3195 pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>; 3196 resets = <&cru SRST_H_SDIO>; 3197 reset-names = "reset"; 3198 rockchip,use-v2-tuning; 3199 status = "disabled"; 3200 }; 3201 3202 sdhci: mmc@2a330000 { 3203 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; 3204 reg = <0x0 0x2a330000 0x0 0x10000>; 3205 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 3206 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; 3207 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 3208 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 3209 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 3210 <&cru TCLK_EMMC>; 3211 clock-names = "core", "bus", "axi", "block", "timer"; 3212 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 3213 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 3214 <&cru SRST_T_EMMC>; 3215 reset-names = "core", "bus", "axi", "block", "timer"; 3216 max-frequency = <200000000>; 3217 status = "disabled"; 3218 }; 3219 3220 sfc0: spi@2a340000 { 3221 compatible = "rockchip,sfc"; 3222 reg = <0x0 0x2a340000 0x0 0x4000>; 3223 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 3224 clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; 3225 clock-names = "clk_sfc", "hclk_sfc"; 3226 assigned-clocks = <&cru SCLK_FSPI_X2>; 3227 assigned-clock-rates = <80000000>; 3228 #address-cells = <1>; 3229 #size-cells = <0>; 3230 status = "disabled"; 3231 }; 3232 3233 crypto: crypto@2a400000 { 3234 compatible = "rockchip,crypto-v4"; 3235 reg = <0x0 0x2a400000 0x0 0x2000>; 3236 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 3237 clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, 3238 <&cru CLK_PKA_CRYPTO_NS>; 3239 clock-names = "aclk", "hclk", "pka"; 3240 assigned-clocks = <&cru ACLK_CRYPTO_NS>, <&cru CLK_PKA_CRYPTO_NS>; 3241 assigned-clock-rates = <300000000>, <300000000>; 3242 resets = <&cru SRST_H_CRYPTO_NS>; 3243 reset-names = "crypto-rst"; 3244 status = "disabled"; 3245 }; 3246 3247 rng: rng@2a410000 { 3248 compatible = "rockchip,rkrng"; 3249 reg = <0x0 0x2a410000 0x0 0x200>; 3250 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 3251 clocks = <&cru HCLK_TRNG_NS>; 3252 clock-names = "hclk_trng"; 3253 resets = <&cru SRST_H_TRNG_NS>; 3254 reset-names = "reset"; 3255 status = "disabled"; 3256 }; 3257 3258 otp: otp@2a580000 { 3259 compatible = "rockchip,rk3576-otp"; 3260 reg = <0x0 0x2a580000 0x0 0x400>; 3261 #address-cells = <1>; 3262 #size-cells = <1>; 3263 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>; 3264 clock-names = "otpc", "apb"; 3265 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; 3266 reset-names = "otpc", "apb"; 3267 3268 /* Data cells */ 3269 cpu_code: cpu-code@2 { 3270 reg = <0x02 0x2>; 3271 }; 3272 otp_cpu_version: cpu-version@5 { 3273 reg = <0x05 0x1>; 3274 bits = <3 3>; 3275 }; 3276 otp_id: id@a { 3277 reg = <0x0a 0x10>; 3278 }; 3279 cpub_leakage: cpub-leakage@1e { 3280 reg = <0x1e 0x1>; 3281 }; 3282 cpul_leakage: cpul-leakage@1f { 3283 reg = <0x1f 0x1>; 3284 }; 3285 npu_leakage: npu-leakage@20 { 3286 reg = <0x20 0x1>; 3287 }; 3288 gpu_leakage: gpu-leakage@21 { 3289 reg = <0x21 0x1>; 3290 }; 3291 log_leakage: log-leakage@22 { 3292 reg = <0x22 0x1>; 3293 }; 3294 }; 3295 3296 sai0: sai@2a600000 { 3297 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 3298 reg = <0x0 0x2a600000 0x0 0x1000>; 3299 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 3300 clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>; 3301 clock-names = "mclk", "hclk"; 3302 dmas = <&dmac0 0>, <&dmac0 1>; 3303 dma-names = "tx", "rx"; 3304 power-domains = <&power RK3576_PD_AUDIO>; 3305 resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; 3306 reset-names = "m", "h"; 3307 pinctrl-names = "default"; 3308 pinctrl-0 = <&sai0m0_lrck 3309 &sai0m0_sclk 3310 &sai0m0_sdi0 3311 &sai0m0_sdi1 3312 &sai0m0_sdi2 3313 &sai0m0_sdi3 3314 &sai0m0_sdo0 3315 &sai0m0_sdo1 3316 &sai0m0_sdo2 3317 &sai0m0_sdo3>; 3318 #sound-dai-cells = <0>; 3319 sound-name-prefix = "SAI0"; 3320 status = "disabled"; 3321 }; 3322 3323 sai1: sai@2a610000 { 3324 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 3325 reg = <0x0 0x2a610000 0x0 0x1000>; 3326 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 3327 clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>; 3328 clock-names = "mclk", "hclk"; 3329 dmas = <&dmac0 2>, <&dmac0 3>; 3330 dma-names = "tx", "rx"; 3331 power-domains = <&power RK3576_PD_AUDIO>; 3332 resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; 3333 reset-names = "m", "h"; 3334 pinctrl-names = "default"; 3335 pinctrl-0 = <&sai1m0_lrck 3336 &sai1m0_sclk 3337 &sai1m0_sdi0 3338 &sai1m0_sdo0 3339 &sai1m0_sdo1 3340 &sai1m0_sdo2 3341 &sai1m0_sdo3>; 3342 #sound-dai-cells = <0>; 3343 sound-name-prefix = "SAI1"; 3344 status = "disabled"; 3345 }; 3346 3347 sai2: sai@2a620000 { 3348 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 3349 reg = <0x0 0x2a620000 0x0 0x1000>; 3350 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 3351 clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>; 3352 clock-names = "mclk", "hclk"; 3353 dmas = <&dmac1 0>, <&dmac1 1>; 3354 dma-names = "tx", "rx"; 3355 power-domains = <&power RK3576_PD_AUDIO>; 3356 resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; 3357 reset-names = "m", "h"; 3358 pinctrl-names = "default"; 3359 pinctrl-0 = <&sai2m0_lrck 3360 &sai2m0_sclk 3361 &sai2m0_sdi 3362 &sai2m0_sdo>; 3363 #sound-dai-cells = <0>; 3364 sound-name-prefix = "SAI2"; 3365 status = "disabled"; 3366 }; 3367 3368 sai3: sai@2a630000 { 3369 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 3370 reg = <0x0 0x2a630000 0x0 0x1000>; 3371 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 3372 clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>; 3373 clock-names = "mclk", "hclk"; 3374 dmas = <&dmac1 2>, <&dmac1 3>; 3375 dma-names = "tx", "rx"; 3376 power-domains = <&power RK3576_PD_AUDIO>; 3377 resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>; 3378 reset-names = "m", "h"; 3379 pinctrl-names = "default"; 3380 pinctrl-0 = <&sai3m0_lrck 3381 &sai3m0_sclk 3382 &sai3m0_sdi 3383 &sai3m0_sdo>; 3384 #sound-dai-cells = <0>; 3385 sound-name-prefix = "SAI3"; 3386 status = "disabled"; 3387 }; 3388 3389 sai4: sai@2a640000 { 3390 compatible = "rockchip,rk3576-sai", "rockchip,sai-v1"; 3391 reg = <0x0 0x2a640000 0x0 0x1000>; 3392 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 3393 clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>; 3394 clock-names = "mclk", "hclk"; 3395 dmas = <&dmac2 0>, <&dmac2 1>; 3396 dma-names = "tx", "rx"; 3397 power-domains = <&power RK3576_PD_AUDIO>; 3398 resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>; 3399 reset-names = "m", "h"; 3400 pinctrl-names = "default"; 3401 pinctrl-0 = <&sai4m0_lrck 3402 &sai4m0_sclk 3403 &sai4m0_sdi 3404 &sai4m0_sdo>; 3405 #sound-dai-cells = <0>; 3406 sound-name-prefix = "SAI4"; 3407 status = "disabled"; 3408 }; 3409 3410 spdif_rx0: spdif-rx@2a650000 { 3411 compatible = "rockchip,rk3576-spdifrx", "rockchip,rk3308-spdifrx"; 3412 reg = <0x0 0x2a650000 0x0 0x1000>; 3413 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 3414 clocks = <&cru MCLK_SPDIF_RX0>, <&cru HCLK_SPDIF_RX0>; 3415 clock-names = "mclk", "hclk"; 3416 dmas = <&dmac1 8>; 3417 dma-names = "rx"; 3418 power-domains = <&power RK3576_PD_AUDIO>; 3419 resets = <&cru SRST_M_SPDIF_RX0>; 3420 reset-names = "spdifrx-m"; 3421 pinctrl-names = "default"; 3422 pinctrl-0 = <&spdifm0_rx0>; 3423 status = "disabled"; 3424 }; 3425 3426 spdif_rx1: spdif-rx@2a660000 { 3427 compatible = "rockchip,rk3576-spdifrx", "rockchip,rk3308-spdifrx"; 3428 reg = <0x0 0x2a660000 0x0 0x1000>; 3429 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 3430 clocks = <&cru MCLK_SPDIF_RX1>, <&cru HCLK_SPDIF_RX1>; 3431 clock-names = "mclk", "hclk"; 3432 dmas = <&dmac2 16>; 3433 dma-names = "rx"; 3434 power-domains = <&power RK3576_PD_AUDIO>; 3435 resets = <&cru SRST_M_SPDIF_RX1>; 3436 reset-names = "spdifrx-m"; 3437 pinctrl-names = "default"; 3438 pinctrl-0 = <&spdifm0_rx1>; 3439 status = "disabled"; 3440 }; 3441 3442 spdif_tx0: spdif-tx@2a670000 { 3443 compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; 3444 reg = <0x0 0x2a670000 0x0 0x1000>; 3445 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 3446 clocks = <&cru MCLK_SPDIF_TX0>, <&cru HCLK_SPDIF_TX0>; 3447 clock-names = "mclk", "hclk"; 3448 dmas = <&dmac0 5>; 3449 dma-names = "tx"; 3450 power-domains = <&power RK3576_PD_AUDIO>; 3451 pinctrl-names = "default"; 3452 pinctrl-0 = <&spdifm0_tx0>; 3453 #sound-dai-cells = <0>; 3454 status = "disabled"; 3455 }; 3456 3457 spdif_tx1: spdif-tx@2a680000 { 3458 compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; 3459 reg = <0x0 0x2a680000 0x0 0x1000>; 3460 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 3461 clocks = <&cru MCLK_SPDIF_TX1>, <&cru HCLK_SPDIF_TX1>; 3462 clock-names = "mclk", "hclk"; 3463 dmas = <&dmac1 5>; 3464 dma-names = "tx"; 3465 power-domains = <&power RK3576_PD_AUDIO>; 3466 pinctrl-names = "default"; 3467 pinctrl-0 = <&spdifm0_tx1>; 3468 #sound-dai-cells = <0>; 3469 status = "disabled"; 3470 }; 3471 3472 acdcdig_dsm: acdcdig-dsm@2a6d0000 { 3473 compatible = "rockchip,rk3576-dsm"; 3474 reg = <0x0 0x2a6d0000 0x0 0x1000>; 3475 clocks = <&cru MCLK_ACDCDIG_DSM>, <&cru HCLK_ACDCDIG_DSM>; 3476 clock-names = "dac", "pclk"; 3477 resets = <&cru SRST_M_ACDCDIG_DSM>; 3478 reset-names = "reset" ; 3479 rockchip,grf = <&sys_grf>; 3480 power-domains = <&power RK3576_PD_AUDIO>; 3481 pinctrl-names = "default"; 3482 pinctrl-0 = <&dsm_audm0_ln 3483 &dsm_audm0_lp 3484 &dsm_audm0_rn 3485 &dsm_audm0_rp>; 3486 #sound-dai-cells = <0>; 3487 status = "disabled"; 3488 }; 3489 3490 pdm1: pdm@2a6e0000 { 3491 compatible = "rockchip,rk3576-pdm"; 3492 reg = <0x0 0x2a6e0000 0x0 0x1000>; 3493 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 3494 clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>, <&cru CLK_PDM1_OUT>; 3495 clock-names = "pdm_clk", "pdm_hclk", "pdm_clk_out"; 3496 assigned-clocks = <&cru MCLK_PDM1>; 3497 assigned-clock-parents = <&cru PLL_AUPLL>; 3498 dmas = <&dmac1 4>; 3499 dma-names = "rx"; 3500 pinctrl-names = "default"; 3501 pinctrl-0 = <&pdm1m0_clk0 3502 &pdm1m0_clk1 3503 &pdm1m0_sdi0 3504 &pdm1m0_sdi1 3505 &pdm1m0_sdi2 3506 &pdm1m0_sdi3>; 3507 power-domains = <&power RK3576_PD_AUDIO>; 3508 #sound-dai-cells = <0>; 3509 sound-name-prefix = "PDM1"; 3510 status = "disabled"; 3511 }; 3512 3513 gic: interrupt-controller@2a701000 { 3514 compatible = "arm,gic-400"; 3515 #interrupt-cells = <3>; 3516 #address-cells = <2>; 3517 #size-cells = <2>; 3518 ranges; 3519 interrupt-controller; 3520 3521 reg = <0x0 0x2a701000 0 0x10000>, 3522 <0x0 0x2a702000 0 0x10000>, 3523 <0x0 0x2a704000 0 0x10000>, 3524 <0x0 0x2a706000 0 0x10000>; 3525 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3526 }; 3527 3528 hwlock: hwspinlock@2ab00000 { 3529 compatible = "rockchip,hwspinlock"; 3530 reg = <0x0 0x2ab00000 0x0 0x100>; 3531 #hwlock-cells = <1>; 3532 status = "disabled"; 3533 }; 3534 3535 dmac0: dma-controller@2ab90000 { 3536 compatible = "arm,pl330", "arm,primecell"; 3537 reg = <0x0 0x2ab90000 0x0 0x4000>; 3538 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 3539 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3540 clocks = <&cru ACLK_DMAC0>; 3541 clock-names = "apb_pclk"; 3542 #dma-cells = <1>; 3543 arm,pl330-periph-burst; 3544 }; 3545 3546 dmac1: dma-controller@2abb0000 { 3547 compatible = "arm,pl330", "arm,primecell"; 3548 reg = <0x0 0x2abb0000 0x0 0x4000>; 3549 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 3550 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3551 clocks = <&cru ACLK_DMAC1>; 3552 clock-names = "apb_pclk"; 3553 #dma-cells = <1>; 3554 arm,pl330-periph-burst; 3555 }; 3556 3557 dmac2: dma-controller@2abd0000 { 3558 compatible = "arm,pl330", "arm,primecell"; 3559 reg = <0x0 0x2abd0000 0x0 0x4000>; 3560 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 3561 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3562 clocks = <&cru ACLK_DMAC2>; 3563 clock-names = "apb_pclk"; 3564 #dma-cells = <1>; 3565 arm,pl330-periph-burst; 3566 }; 3567 3568 i3c0: i3c-master@2abe0000 { 3569 compatible = "rockchip,i3c-master"; 3570 reg = <0x0 0x2abe0000 0x0 0x1000>; 3571 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 3572 #address-cells = <3>; 3573 #size-cells = <0>; 3574 clocks = <&cru HCLK_I3C0>, <&cru CLK_I3C0>; 3575 clock-names = "hclk", "i3c"; 3576 dmas = <&dmac0 22>, <&dmac0 23>; 3577 dma-names = "rx", "tx"; 3578 pinctrl-names = "default"; 3579 pinctrl-0 = <&i3c0m0_xfer &i3c0_sdam0_pu>; 3580 status = "disabled"; 3581 }; 3582 3583 i3c1: i3c-master@2abf0000 { 3584 compatible = "rockchip,i3c-master"; 3585 reg = <0x0 0x2abf0000 0x0 0x1000>; 3586 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 3587 #address-cells = <3>; 3588 #size-cells = <0>; 3589 clocks = <&cru HCLK_I3C1>, <&cru CLK_I3C1>; 3590 clock-names = "hclk", "i3c"; 3591 dmas = <&dmac1 22>, <&dmac1 23>; 3592 dma-names = "rx", "tx"; 3593 pinctrl-names = "default"; 3594 pinctrl-0 = <&i3c1m0_xfer &i3c1_sdam0_pu>; 3595 status = "disabled"; 3596 }; 3597 3598 can0: can@2ac00000 { 3599 compatible = "rockchip,rk3576-canfd"; 3600 reg = <0x0 0x2ac00000 0x0 0x1000>; 3601 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 3602 clocks = <&cru CLK_CAN0>, <&cru HCLK_CAN0>; 3603 clock-names = "baudclk", "apb_pclk"; 3604 resets = <&cru SRST_CAN0>, <&cru SRST_H_CAN0>; 3605 reset-names = "can", "can-apb"; 3606 dmas = <&dmac0 20>; 3607 dma-names = "rx"; 3608 status = "disabled"; 3609 }; 3610 3611 can1: can@2ac10000 { 3612 compatible = "rockchip,rk3576-canfd"; 3613 reg = <0x0 0x2ac10000 0x0 0x1000>; 3614 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 3615 clocks = <&cru CLK_CAN1>, <&cru HCLK_CAN1>; 3616 clock-names = "baudclk", "apb_pclk"; 3617 resets = <&cru SRST_CAN1>, <&cru SRST_H_CAN1>; 3618 reset-names = "can", "can-apb"; 3619 dmas = <&dmac1 21>; 3620 dma-names = "rx"; 3621 status = "disabled"; 3622 }; 3623 3624 hw_decompress: decompress@2ac30000 { 3625 compatible = "rockchip,hw-decompress"; 3626 reg = <0x0 0x2ac30000 0x0 0x1000>; 3627 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 3628 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 3629 clock-names = "aclk", "dclk", "pclk"; 3630 resets = <&cru SRST_D_DECOM>; 3631 reset-names = "dresetn"; 3632 status = "disabled"; 3633 }; 3634 3635 i2c1: i2c@2ac40000 { 3636 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3637 reg = <0x0 0x2ac40000 0x0 0x1000>; 3638 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 3639 clock-names = "i2c", "pclk"; 3640 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 3641 pinctrl-names = "default"; 3642 pinctrl-0 = <&i2c1m0_xfer>; 3643 resets = <&cru SRST_I2C1>, <&cru SRST_P_I2C1>; 3644 reset-names = "i2c", "apb"; 3645 #address-cells = <1>; 3646 #size-cells = <0>; 3647 status = "disabled"; 3648 }; 3649 3650 i2c2: i2c@2ac50000 { 3651 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3652 reg = <0x0 0x2ac50000 0x0 0x1000>; 3653 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 3654 clock-names = "i2c", "pclk"; 3655 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 3656 pinctrl-names = "default"; 3657 pinctrl-0 = <&i2c2m0_xfer>; 3658 resets = <&cru SRST_I2C2>, <&cru SRST_P_I2C2>; 3659 reset-names = "i2c", "apb"; 3660 #address-cells = <1>; 3661 #size-cells = <0>; 3662 status = "disabled"; 3663 }; 3664 3665 i2c3: i2c@2ac60000 { 3666 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3667 reg = <0x0 0x2ac60000 0x0 0x1000>; 3668 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 3669 clock-names = "i2c", "pclk"; 3670 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 3671 pinctrl-names = "default"; 3672 pinctrl-0 = <&i2c3m0_xfer>; 3673 resets = <&cru SRST_I2C3>, <&cru SRST_P_I2C3>; 3674 reset-names = "i2c", "apb"; 3675 #address-cells = <1>; 3676 #size-cells = <0>; 3677 status = "disabled"; 3678 }; 3679 3680 i2c4: i2c@2ac70000 { 3681 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3682 reg = <0x0 0x2ac70000 0x0 0x1000>; 3683 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 3684 clock-names = "i2c", "pclk"; 3685 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 3686 pinctrl-names = "default"; 3687 pinctrl-0 = <&i2c4m0_xfer>; 3688 resets = <&cru SRST_I2C4>, <&cru SRST_P_I2C4>; 3689 reset-names = "i2c", "apb"; 3690 #address-cells = <1>; 3691 #size-cells = <0>; 3692 status = "disabled"; 3693 }; 3694 3695 i2c5: i2c@2ac80000 { 3696 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3697 reg = <0x0 0x2ac80000 0x0 0x1000>; 3698 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 3699 clock-names = "i2c", "pclk"; 3700 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 3701 pinctrl-names = "default"; 3702 pinctrl-0 = <&i2c5m0_xfer>; 3703 resets = <&cru SRST_I2C5>, <&cru SRST_P_I2C5>; 3704 reset-names = "i2c", "apb"; 3705 #address-cells = <1>; 3706 #size-cells = <0>; 3707 status = "disabled"; 3708 }; 3709 3710 3711 i2c6: i2c@2ac90000 { 3712 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3713 reg = <0x0 0x2ac90000 0x0 0x1000>; 3714 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 3715 clock-names = "i2c", "pclk"; 3716 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 3717 pinctrl-names = "default"; 3718 pinctrl-0 = <&i2c6m0_xfer>; 3719 resets = <&cru SRST_I2C6>, <&cru SRST_P_I2C6>; 3720 reset-names = "i2c", "apb"; 3721 #address-cells = <1>; 3722 #size-cells = <0>; 3723 status = "disabled"; 3724 }; 3725 3726 i2c7: i2c@2aca0000 { 3727 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3728 reg = <0x0 0x2aca0000 0x0 0x1000>; 3729 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 3730 clock-names = "i2c", "pclk"; 3731 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3732 pinctrl-names = "default"; 3733 pinctrl-0 = <&i2c7m0_xfer>; 3734 resets = <&cru SRST_I2C7>, <&cru SRST_P_I2C7>; 3735 reset-names = "i2c", "apb"; 3736 #address-cells = <1>; 3737 #size-cells = <0>; 3738 status = "disabled"; 3739 }; 3740 3741 i2c8: i2c@2acb0000 { 3742 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 3743 reg = <0x0 0x2acb0000 0x0 0x1000>; 3744 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 3745 clock-names = "i2c", "pclk"; 3746 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 3747 pinctrl-names = "default"; 3748 pinctrl-0 = <&i2c8m0_xfer>; 3749 resets = <&cru SRST_I2C8>, <&cru SRST_P_I2C8>; 3750 reset-names = "i2c", "apb"; 3751 #address-cells = <1>; 3752 #size-cells = <0>; 3753 status = "disabled"; 3754 }; 3755 3756 rktimer: timer@2acc0000 { 3757 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer"; 3758 reg = <0x0 0x2acc0000 0x0 0x20>; 3759 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 3760 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>; 3761 clock-names = "pclk", "timer"; 3762 }; 3763 3764 wdt: watchdog@2ace0000 { 3765 compatible = "snps,dw-wdt"; 3766 reg = <0x0 0x2ace0000 0x0 0x100>; 3767 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 3768 clock-names = "tclk", "pclk"; 3769 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 3770 status = "disabled"; 3771 }; 3772 3773 spi0: spi@2acf0000 { 3774 compatible = "rockchip,rk3066-spi"; 3775 reg = <0x0 0x2acf0000 0x0 0x1000>; 3776 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 3777 #address-cells = <1>; 3778 #size-cells = <0>; 3779 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 3780 clock-names = "spiclk", "apb_pclk"; 3781 dmas = <&dmac0 14>, <&dmac0 15>; 3782 dma-names = "tx", "rx"; 3783 pinctrl-names = "default"; 3784 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 3785 num-cs = <2>; 3786 status = "disabled"; 3787 }; 3788 3789 spi1: spi@2ad00000 { 3790 compatible = "rockchip,rk3066-spi"; 3791 reg = <0x0 0x2ad00000 0x0 0x1000>; 3792 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 3793 #address-cells = <1>; 3794 #size-cells = <0>; 3795 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 3796 clock-names = "spiclk", "apb_pclk"; 3797 dmas = <&dmac0 16>, <&dmac0 17>; 3798 dma-names = "tx", "rx"; 3799 pinctrl-names = "default"; 3800 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 3801 num-cs = <2>; 3802 status = "disabled"; 3803 }; 3804 3805 spi2: spi@2ad10000 { 3806 compatible = "rockchip,rk3066-spi"; 3807 reg = <0x0 0x2ad10000 0x0 0x1000>; 3808 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 3809 #address-cells = <1>; 3810 #size-cells = <0>; 3811 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 3812 clock-names = "spiclk", "apb_pclk"; 3813 dmas = <&dmac1 15>, <&dmac1 16>; 3814 dma-names = "tx", "rx"; 3815 pinctrl-names = "default"; 3816 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 3817 num-cs = <2>; 3818 status = "disabled"; 3819 }; 3820 3821 spi3: spi@2ad20000 { 3822 compatible = "rockchip,rk3066-spi"; 3823 reg = <0x0 0x2ad20000 0x0 0x1000>; 3824 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 3825 #address-cells = <1>; 3826 #size-cells = <0>; 3827 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 3828 clock-names = "spiclk", "apb_pclk"; 3829 dmas = <&dmac1 17>, <&dmac1 18>; 3830 dma-names = "tx", "rx"; 3831 pinctrl-names = "default"; 3832 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>; 3833 num-cs = <2>; 3834 status = "disabled"; 3835 }; 3836 3837 spi4: spi@2ad30000 { 3838 compatible = "rockchip,rk3066-spi"; 3839 reg = <0x0 0x2ad30000 0x0 0x1000>; 3840 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 3841 #address-cells = <1>; 3842 #size-cells = <0>; 3843 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 3844 clock-names = "spiclk", "apb_pclk"; 3845 dmas = <&dmac2 12>, <&dmac2 13>; 3846 dma-names = "tx", "rx"; 3847 pinctrl-names = "default"; 3848 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>; 3849 num-cs = <2>; 3850 status = "disabled"; 3851 }; 3852 3853 uart0: serial@2ad40000 { 3854 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3855 reg = <0x0 0x2ad40000 0x0 0x100>; 3856 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 3857 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 3858 clock-names = "baudclk", "apb_pclk"; 3859 reg-shift = <2>; 3860 reg-io-width = <4>; 3861 dmas = <&dmac0 6>, <&dmac0 7>; 3862 pinctrl-names = "default"; 3863 pinctrl-0 = <&uart0m0_xfer>; 3864 status = "disabled"; 3865 }; 3866 3867 uart2: serial@2ad50000 { 3868 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3869 reg = <0x0 0x2ad50000 0x0 0x100>; 3870 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 3871 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 3872 clock-names = "baudclk", "apb_pclk"; 3873 reg-shift = <2>; 3874 reg-io-width = <4>; 3875 dmas = <&dmac0 10>, <&dmac0 11>; 3876 pinctrl-names = "default"; 3877 pinctrl-0 = <&uart2m0_xfer>; 3878 status = "disabled"; 3879 }; 3880 3881 uart3: serial@2ad60000 { 3882 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3883 reg = <0x0 0x2ad60000 0x0 0x100>; 3884 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 3885 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 3886 clock-names = "baudclk", "apb_pclk"; 3887 reg-shift = <2>; 3888 reg-io-width = <4>; 3889 dmas = <&dmac0 12>, <&dmac0 13>; 3890 pinctrl-names = "default"; 3891 pinctrl-0 = <&uart3m0_xfer>; 3892 status = "disabled"; 3893 }; 3894 3895 uart4: serial@2ad70000 { 3896 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3897 reg = <0x0 0x2ad70000 0x0 0x100>; 3898 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 3899 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 3900 clock-names = "baudclk", "apb_pclk"; 3901 reg-shift = <2>; 3902 reg-io-width = <4>; 3903 dmas = <&dmac1 9>, <&dmac1 10>; 3904 pinctrl-names = "default"; 3905 pinctrl-0 = <&uart4m0_xfer>; 3906 status = "disabled"; 3907 }; 3908 3909 uart5: serial@2ad80000 { 3910 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3911 reg = <0x0 0x2ad80000 0x0 0x100>; 3912 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3913 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 3914 clock-names = "baudclk", "apb_pclk"; 3915 reg-shift = <2>; 3916 reg-io-width = <4>; 3917 dmas = <&dmac1 11>, <&dmac1 12>; 3918 pinctrl-names = "default"; 3919 pinctrl-0 = <&uart5m0_xfer>; 3920 status = "disabled"; 3921 }; 3922 3923 uart6: serial@2ad90000 { 3924 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3925 reg = <0x0 0x2ad90000 0x0 0x100>; 3926 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3927 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 3928 clock-names = "baudclk", "apb_pclk"; 3929 reg-shift = <2>; 3930 reg-io-width = <4>; 3931 dmas = <&dmac1 13>, <&dmac1 14>; 3932 pinctrl-names = "default"; 3933 pinctrl-0 = <&uart6m0_xfer>; 3934 status = "disabled"; 3935 }; 3936 3937 uart7: serial@2ada0000 { 3938 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3939 reg = <0x0 0x2ada0000 0x0 0x100>; 3940 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3941 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 3942 clock-names = "baudclk", "apb_pclk"; 3943 reg-shift = <2>; 3944 reg-io-width = <4>; 3945 dmas = <&dmac2 6>, <&dmac2 7>; 3946 pinctrl-names = "default"; 3947 pinctrl-0 = <&uart7m0_xfer>; 3948 status = "disabled"; 3949 }; 3950 3951 uart8: serial@2adb0000 { 3952 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3953 reg = <0x0 0x2adb0000 0x0 0x100>; 3954 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 3955 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 3956 clock-names = "baudclk", "apb_pclk"; 3957 reg-shift = <2>; 3958 reg-io-width = <4>; 3959 dmas = <&dmac2 8>, <&dmac2 9>; 3960 pinctrl-names = "default"; 3961 pinctrl-0 = <&uart8m0_xfer>; 3962 status = "disabled"; 3963 }; 3964 3965 uart9: serial@2adc0000 { 3966 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 3967 reg = <0x0 0x2adc0000 0x0 0x100>; 3968 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 3969 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 3970 clock-names = "baudclk", "apb_pclk"; 3971 reg-shift = <2>; 3972 reg-io-width = <4>; 3973 dmas = <&dmac2 10>, <&dmac2 11>; 3974 pinctrl-names = "default"; 3975 pinctrl-0 = <&uart9m0_xfer>; 3976 status = "disabled"; 3977 }; 3978 3979 pwm1_6ch_0: pwm@2add0000 { 3980 compatible = "rockchip,rk3576-pwm"; 3981 reg = <0x0 0x2add0000 0x0 0x1000>; 3982 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3983 #pwm-cells = <3>; 3984 pinctrl-names = "active"; 3985 pinctrl-0 = <&pwm1m0_ch0>; 3986 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 3987 clock-names = "pwm", "pclk"; 3988 status = "disabled"; 3989 }; 3990 3991 pwm1_6ch_1: pwm@2add1000 { 3992 compatible = "rockchip,rk3576-pwm"; 3993 reg = <0x0 0x2add1000 0x0 0x1000>; 3994 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3995 #pwm-cells = <3>; 3996 pinctrl-names = "active"; 3997 pinctrl-0 = <&pwm1m0_ch1>; 3998 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 3999 clock-names = "pwm", "pclk"; 4000 status = "disabled"; 4001 }; 4002 4003 pwm1_6ch_2: pwm@2add2000 { 4004 compatible = "rockchip,rk3576-pwm"; 4005 reg = <0x0 0x2add2000 0x0 0x1000>; 4006 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 4007 #pwm-cells = <3>; 4008 pinctrl-names = "active"; 4009 pinctrl-0 = <&pwm1m0_ch2>; 4010 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 4011 clock-names = "pwm", "pclk"; 4012 status = "disabled"; 4013 }; 4014 4015 pwm1_6ch_3: pwm@2add3000 { 4016 compatible = "rockchip,rk3576-pwm"; 4017 reg = <0x0 0x2add3000 0x0 0x1000>; 4018 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 4019 #pwm-cells = <3>; 4020 pinctrl-names = "active"; 4021 pinctrl-0 = <&pwm1m0_ch3>; 4022 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 4023 clock-names = "pwm", "pclk"; 4024 status = "disabled"; 4025 }; 4026 4027 pwm1_6ch_4: pwm@2add4000 { 4028 compatible = "rockchip,rk3576-pwm"; 4029 reg = <0x0 0x2add4000 0x0 0x1000>; 4030 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 4031 #pwm-cells = <3>; 4032 pinctrl-names = "active"; 4033 pinctrl-0 = <&pwm1m0_ch4>; 4034 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 4035 clock-names = "pwm", "pclk"; 4036 status = "disabled"; 4037 }; 4038 4039 pwm1_6ch_5: pwm@2add5000 { 4040 compatible = "rockchip,rk3576-pwm"; 4041 reg = <0x0 0x2add5000 0x0 0x1000>; 4042 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 4043 #pwm-cells = <3>; 4044 pinctrl-names = "active"; 4045 pinctrl-0 = <&pwm1m0_ch5>; 4046 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 4047 clock-names = "pwm", "pclk"; 4048 status = "disabled"; 4049 }; 4050 4051 pwm2_8ch_0: pwm@2ade0000 { 4052 compatible = "rockchip,rk3576-pwm"; 4053 reg = <0x0 0x2ade0000 0x0 0x1000>; 4054 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 4055 #pwm-cells = <3>; 4056 pinctrl-names = "active"; 4057 pinctrl-0 = <&pwm2m0_ch0>; 4058 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4059 clock-names = "pwm", "pclk"; 4060 status = "disabled"; 4061 }; 4062 4063 pwm2_8ch_1: pwm@2ade1000 { 4064 compatible = "rockchip,rk3576-pwm"; 4065 reg = <0x0 0x2ade1000 0x0 0x1000>; 4066 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 4067 #pwm-cells = <3>; 4068 pinctrl-names = "active"; 4069 pinctrl-0 = <&pwm2m0_ch1>; 4070 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4071 clock-names = "pwm", "pclk"; 4072 status = "disabled"; 4073 }; 4074 4075 pwm2_8ch_2: pwm@2ade2000 { 4076 compatible = "rockchip,rk3576-pwm"; 4077 reg = <0x0 0x2ade2000 0x0 0x1000>; 4078 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 4079 #pwm-cells = <3>; 4080 pinctrl-names = "active"; 4081 pinctrl-0 = <&pwm2m0_ch2>; 4082 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4083 clock-names = "pwm", "pclk"; 4084 status = "disabled"; 4085 }; 4086 4087 pwm2_8ch_3: pwm@2ade3000 { 4088 compatible = "rockchip,rk3576-pwm"; 4089 reg = <0x0 0x2ade3000 0x0 0x1000>; 4090 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 4091 #pwm-cells = <3>; 4092 pinctrl-names = "active"; 4093 pinctrl-0 = <&pwm2m0_ch3>; 4094 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4095 clock-names = "pwm", "pclk"; 4096 status = "disabled"; 4097 }; 4098 4099 pwm2_8ch_4: pwm@2ade4000 { 4100 compatible = "rockchip,rk3576-pwm"; 4101 reg = <0x0 0x2ade4000 0x0 0x1000>; 4102 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 4103 #pwm-cells = <3>; 4104 pinctrl-names = "active"; 4105 pinctrl-0 = <&pwm2m0_ch4>; 4106 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4107 clock-names = "pwm", "pclk"; 4108 status = "disabled"; 4109 }; 4110 4111 pwm2_8ch_5: pwm@2ade5000 { 4112 compatible = "rockchip,rk3576-pwm"; 4113 reg = <0x0 0x2ade5000 0x0 0x1000>; 4114 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 4115 #pwm-cells = <3>; 4116 pinctrl-names = "active"; 4117 pinctrl-0 = <&pwm2m0_ch5>; 4118 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4119 clock-names = "pwm", "pclk"; 4120 status = "disabled"; 4121 }; 4122 4123 pwm2_8ch_6: pwm@2ade6000 { 4124 compatible = "rockchip,rk3576-pwm"; 4125 reg = <0x0 0x2ade6000 0x0 0x1000>; 4126 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 4127 #pwm-cells = <3>; 4128 pinctrl-names = "active"; 4129 pinctrl-0 = <&pwm2m0_ch6>; 4130 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4131 clock-names = "pwm", "pclk"; 4132 status = "disabled"; 4133 }; 4134 4135 pwm2_8ch_7: pwm@2ade7000 { 4136 compatible = "rockchip,rk3576-pwm"; 4137 reg = <0x0 0x2ade7000 0x0 0x1000>; 4138 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 4139 #pwm-cells = <3>; 4140 pinctrl-names = "active"; 4141 pinctrl-0 = <&pwm2m0_ch7>; 4142 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4143 clock-names = "pwm", "pclk"; 4144 status = "disabled"; 4145 }; 4146 4147 saradc: adc@2ae00000 { 4148 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc"; 4149 reg = <0x0 0x2ae00000 0x0 0x10000>; 4150 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 4151 #io-channel-cells = <1>; 4152 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 4153 clock-names = "saradc", "apb_pclk"; 4154 resets = <&cru SRST_P_SARADC>; 4155 reset-names = "saradc-apb"; 4156 status = "disabled"; 4157 }; 4158 4159 mailbox0: mailbox@2ae50000 { 4160 compatible = "rockchip,rk3576-mailbox"; 4161 reg = <0x0 0x2ae50000 0x0 0x20>; 4162 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 4163 clocks = <&cru PCLK_MAILBOX0>; 4164 clock-names = "pclk_mailbox"; 4165 #mbox-cells = <1>; 4166 status = "disabled"; 4167 }; 4168 4169 mailbox1: mailbox@2ae51000 { 4170 compatible = "rockchip,rk3576-mailbox"; 4171 reg = <0x0 0x2ae51000 0x0 0x20>; 4172 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 4173 clocks = <&cru PCLK_MAILBOX0>; 4174 clock-names = "pclk_mailbox"; 4175 #mbox-cells = <1>; 4176 status = "disabled"; 4177 }; 4178 4179 mailbox2: mailbox@2ae52000 { 4180 compatible = "rockchip,rk3576-mailbox"; 4181 reg = <0x0 0x2ae52000 0x0 0x20>; 4182 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 4183 clocks = <&cru PCLK_MAILBOX0>; 4184 clock-names = "pclk_mailbox"; 4185 #mbox-cells = <1>; 4186 status = "disabled"; 4187 }; 4188 4189 mailbox3: mailbox@2ae53000 { 4190 compatible = "rockchip,rk3576-mailbox"; 4191 reg = <0x0 0x2ae53000 0x0 0x20>; 4192 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 4193 clocks = <&cru PCLK_MAILBOX0>; 4194 clock-names = "pclk_mailbox"; 4195 #mbox-cells = <1>; 4196 status = "disabled"; 4197 }; 4198 4199 mailbox4: mailbox@2ae54000 { 4200 compatible = "rockchip,rk3576-mailbox"; 4201 reg = <0x0 0x2ae54000 0x0 0x20>; 4202 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 4203 clocks = <&cru PCLK_MAILBOX0>; 4204 clock-names = "pclk_mailbox"; 4205 #mbox-cells = <1>; 4206 status = "disabled"; 4207 }; 4208 4209 mailbox5: mailbox@2ae55000 { 4210 compatible = "rockchip,rk3576-mailbox"; 4211 reg = <0x0 0x2ae55000 0x0 0x20>; 4212 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 4213 clocks = <&cru PCLK_MAILBOX0>; 4214 clock-names = "pclk_mailbox"; 4215 #mbox-cells = <1>; 4216 status = "disabled"; 4217 }; 4218 4219 mailbox6: mailbox@2ae56000 { 4220 compatible = "rockchip,rk3576-mailbox"; 4221 reg = <0x0 0x2ae56000 0x0 0x20>; 4222 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 4223 clocks = <&cru PCLK_MAILBOX0>; 4224 clock-names = "pclk_mailbox"; 4225 #mbox-cells = <1>; 4226 status = "disabled"; 4227 }; 4228 4229 mailbox7: mailbox@2ae57000 { 4230 compatible = "rockchip,rk3576-mailbox"; 4231 reg = <0x0 0x2ae57000 0x0 0x20>; 4232 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 4233 clocks = <&cru PCLK_MAILBOX0>; 4234 clock-names = "pclk_mailbox"; 4235 #mbox-cells = <1>; 4236 status = "disabled"; 4237 }; 4238 4239 mailbox8: mailbox@2ae58000 { 4240 compatible = "rockchip,rk3576-mailbox"; 4241 reg = <0x0 0x2ae58000 0x0 0x20>; 4242 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4243 clocks = <&cru PCLK_MAILBOX0>; 4244 clock-names = "pclk_mailbox"; 4245 #mbox-cells = <1>; 4246 status = "disabled"; 4247 }; 4248 4249 mailbox9: mailbox@2ae59000 { 4250 compatible = "rockchip,rk3576-mailbox"; 4251 reg = <0x0 0x2ae59000 0x0 0x20>; 4252 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 4253 clocks = <&cru PCLK_MAILBOX0>; 4254 clock-names = "pclk_mailbox"; 4255 #mbox-cells = <1>; 4256 status = "disabled"; 4257 }; 4258 4259 mailbox10: mailbox@2ae5a000 { 4260 compatible = "rockchip,rk3576-mailbox"; 4261 reg = <0x0 0x2ae5a000 0x0 0x20>; 4262 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 4263 clocks = <&cru PCLK_MAILBOX0>; 4264 clock-names = "pclk_mailbox"; 4265 #mbox-cells = <1>; 4266 status = "disabled"; 4267 }; 4268 4269 mailbox11: mailbox@2ae5b000 { 4270 compatible = "rockchip,rk3576-mailbox"; 4271 reg = <0x0 0x2ae5b000 0x0 0x20>; 4272 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 4273 clocks = <&cru PCLK_MAILBOX0>; 4274 clock-names = "pclk_mailbox"; 4275 #mbox-cells = <1>; 4276 status = "disabled"; 4277 }; 4278 4279 mailbox12: mailbox@2ae5c000 { 4280 compatible = "rockchip,rk3576-mailbox"; 4281 reg = <0x0 0x2ae5c000 0x0 0x20>; 4282 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 4283 clocks = <&cru PCLK_MAILBOX0>; 4284 clock-names = "pclk_mailbox"; 4285 #mbox-cells = <1>; 4286 status = "disabled"; 4287 }; 4288 4289 mailbox13: mailbox@2ae5d000 { 4290 compatible = "rockchip,rk3576-mailbox"; 4291 reg = <0x0 0x2ae5d000 0x0 0x20>; 4292 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4293 clocks = <&cru PCLK_MAILBOX0>; 4294 clock-names = "pclk_mailbox"; 4295 #mbox-cells = <1>; 4296 status = "disabled"; 4297 }; 4298 4299 tsadc: tsadc@2ae70000 { 4300 compatible = "rockchip,rk3576-tsadc"; 4301 reg = <0x0 0x2ae70000 0x0 0x400>; 4302 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 4303 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 4304 clock-names = "tsadc", "apb_pclk"; 4305 assigned-clocks = <&cru CLK_TSADC>; 4306 assigned-clock-rates = <2000000>; 4307 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; 4308 reset-names = "tsadc", "tsadc-apb"; 4309 #thermal-sensor-cells = <1>; 4310 rockchip,hw-tshut-temp = <120000>; 4311 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 4312 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 4313 status = "disabled"; 4314 }; 4315 4316 i2c9: i2c@2ae80000 { 4317 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 4318 reg = <0x0 0x2ae80000 0x0 0x1000>; 4319 clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>; 4320 clock-names = "i2c", "pclk"; 4321 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 4322 pinctrl-names = "default"; 4323 pinctrl-0 = <&i2c9m0_xfer>; 4324 resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>; 4325 reset-names = "i2c", "apb"; 4326 #address-cells = <1>; 4327 #size-cells = <0>; 4328 status = "disabled"; 4329 }; 4330 4331 uart10: serial@2afc0000 { 4332 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 4333 reg = <0x0 0x2afc0000 0x0 0x100>; 4334 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 4335 clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>; 4336 clock-names = "baudclk", "apb_pclk"; 4337 reg-shift = <2>; 4338 reg-io-width = <4>; 4339 dmas = <&dmac2 21>, <&dmac2 22>; 4340 pinctrl-names = "default"; 4341 pinctrl-0 = <&uart10m0_xfer>; 4342 status = "disabled"; 4343 }; 4344 4345 uart11: serial@2afd0000 { 4346 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 4347 reg = <0x0 0x2afd0000 0x0 0x100>; 4348 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 4349 clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>; 4350 clock-names = "baudclk", "apb_pclk"; 4351 reg-shift = <2>; 4352 reg-io-width = <4>; 4353 dmas = <&dmac2 23>, <&dmac2 24>; 4354 pinctrl-names = "default"; 4355 pinctrl-0 = <&uart11m0_xfer>; 4356 status = "disabled"; 4357 }; 4358 4359 hdptxphy: phy@2b000000 { 4360 compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; 4361 reg = <0x0 0x2b000000 0x0 0x2000>; 4362 clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_PMUPHY_ROOT>; 4363 clock-names = "ref", "apb"; 4364 resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, 4365 <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; 4366 reset-names = "apb", "init", "cmn", "lane"; 4367 rockchip,grf = <&hdptxphy_grf>; 4368 #phy-cells = <0>; 4369 status = "disabled"; 4370 }; 4371 4372 hdptxphy_hdmi: hdmiphy@2b000000 { 4373 compatible = "rockchip,rk3576-hdptx-phy-hdmi", "rockchip,rk3588-hdptx-phy-hdmi"; 4374 reg = <0x0 0x2b000000 0x0 0x2000>; 4375 clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_PMUPHY_ROOT>; 4376 clock-names = "ref", "apb"; 4377 clock-output-names = "clk_hdmiphy_pixel0"; 4378 #clock-cells = <0>; 4379 resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, 4380 <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; 4381 reset-names = "apb", "init", "cmn", "lane"; 4382 rockchip,grf = <&hdptxphy_grf>; 4383 #phy-cells = <0>; 4384 status = "disabled"; 4385 }; 4386 4387 usbdp_phy: phy@2b010000 { 4388 compatible = "rockchip,rk3576-usbdp-phy"; 4389 reg = <0x0 0x2b010000 0x0 0x10000>; 4390 rockchip,u2phy-grf = <&usb2phy_grf>; 4391 rockchip,usb-grf = <&usb_grf>; 4392 rockchip,usbdpphy-grf = <&usbdpphy_grf>; 4393 rockchip,vo-grf = <&vo1_grf>; 4394 clocks = <&cru CLK_PHY_REF_SRC >, 4395 <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>, 4396 <&cru PCLK_USBDPPHY>; 4397 clock-names = "refclk", "immortal", "pclk"; 4398 resets = <&cru SRST_USBDP_COMBO_PHY_INIT>, 4399 <&cru SRST_USBDP_COMBO_PHY_CMN>, 4400 <&cru SRST_USBDP_COMBO_PHY_LANE>, 4401 <&cru SRST_USBDP_COMBO_PHY_PCS>, 4402 <&cru SRST_P_USBDPPHY>; 4403 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 4404 status = "disabled"; 4405 4406 usbdp_phy_dp: dp-port { 4407 #phy-cells = <0>; 4408 status = "disabled"; 4409 }; 4410 4411 usbdp_phy_u3: u3-port { 4412 #phy-cells = <0>; 4413 status = "disabled"; 4414 }; 4415 }; 4416 4417 mipidcphy0: phy@2b020000 { 4418 compatible = "rockchip,rk3588-mipi-dcphy"; 4419 reg = <0x0 0x2b020000 0x0 0x10000>; 4420 rockchip,grf = <&mipidcphy0_grf>; 4421 clocks = <&cru PCLK_MIPI_DCPHY>; 4422 clock-names = "pclk"; 4423 resets = <&cru SRST_M_MIPI_DCPHY>, 4424 <&cru SRST_P_MIPI_DCPHY>, 4425 <&cru SRST_P_DCPHY_GRF>, 4426 <&cru SRST_S_MIPI_DCPHY>; 4427 reset-names = "m_phy", "apb", "grf", "s_phy"; 4428 #phy-cells = <0>; 4429 status = "okay"; 4430 }; 4431 4432 csi2_dphy0_hw: csi2-dphy0-hw@2b030000 { 4433 compatible = "rockchip,rk3588-csi2-dphy-hw"; 4434 reg = <0x0 0x2b030000 0x0 0x8000>; 4435 clocks = <&cru PCLK_CSIDPHY>; 4436 clock-names = "pclk"; 4437 resets = <&cru SRST_P_CSIPHY>; 4438 reset-names = "srst_p_csiphy"; 4439 rockchip,grf = <&mipidphy0_grf>; 4440 rockchip,sys_grf = <&sys_grf>; 4441 status = "okay"; 4442 }; 4443 4444 combphy0_ps: phy@2b050000 { 4445 compatible = "rockchip,rk3576-naneng-combphy"; 4446 reg = <0x0 0x2b050000 0x0 0x100>; 4447 #phy-cells = <1>; 4448 clocks = <&cru CLK_REF_PCIE0_PHY>, 4449 <&cru PCLK_PCIE2_COMBOPHY0>, 4450 <&cru PCLK_PCIE0>; 4451 clock-names = "refclk", "apbclk", "pipe_clk"; 4452 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>; 4453 assigned-clock-rates = <100000000>; 4454 resets = <&cru SRST_P_PCIE2_COMBOPHY0>, 4455 <&cru SRST_PCIE0_PIPE_PHY>; 4456 reset-names = "combphy-apb", "combphy"; 4457 rockchip,pipe-grf = <&php_grf>; 4458 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 4459 status = "disabled"; 4460 }; 4461 4462 combphy1_psu: phy@2b060000 { 4463 compatible = "rockchip,rk3576-naneng-combphy"; 4464 reg = <0x0 0x2b060000 0x0 0x100>; 4465 #phy-cells = <1>; 4466 clocks = <&cru CLK_REF_PCIE1_PHY>, 4467 <&cru PCLK_PCIE2_COMBOPHY1>, 4468 <&cru PCLK_PCIE1>; 4469 clock-names = "refclk", "apbclk", "pipe_clk"; 4470 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>; 4471 assigned-clock-rates = <100000000>; 4472 resets = <&cru SRST_P_PCIE2_COMBOPHY1>, 4473 <&cru SRST_PCIE1_PIPE_PHY>; 4474 reset-names = "combphy-apb", "combphy"; 4475 rockchip,pipe-grf = <&php_grf>; 4476 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 4477 status = "disabled"; 4478 }; 4479 4480 csi2_dphy1_hw: csi2-dphy1-hw@2b070000 { 4481 compatible = "rockchip,rk3588-csi2-dphy-hw"; 4482 reg = <0x0 0x2b070000 0x0 0x8000>; 4483 clocks = <&cru PCLK_CSIDPHY1>; 4484 clock-names = "pclk"; 4485 resets = <&cru SRST_P_CSIDPHY1>; 4486 reset-names = "srst_p_csiphy1"; 4487 rockchip,grf = <&mipidphy1_grf>; 4488 rockchip,sys_grf = <&sys_grf>; 4489 status = "okay"; 4490 }; 4491 4492 scmi_shmem: scmi-shmem@4010f000 { 4493 compatible = "arm,scmi-shmem"; 4494 reg = <0x0 0x4010f000 0x0 0x100>; 4495 }; 4496 4497 pinctrl: pinctrl { 4498 compatible = "rockchip,rk3576-pinctrl"; 4499 rockchip,grf = <&ioc_grf>; 4500 #address-cells = <2>; 4501 #size-cells = <2>; 4502 ranges; 4503 4504 gpio0: gpio@27320000 { 4505 compatible = "rockchip,gpio-bank"; 4506 reg = <0x0 0x27320000 0x0 0x200>; 4507 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 4508 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 4509 4510 gpio-controller; 4511 #gpio-cells = <2>; 4512 gpio-ranges = <&pinctrl 0 0 32>; 4513 interrupt-controller; 4514 #interrupt-cells = <2>; 4515 }; 4516 4517 gpio1: gpio@2ae10000 { 4518 compatible = "rockchip,gpio-bank"; 4519 reg = <0x0 0x2ae10000 0x0 0x200>; 4520 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 4521 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 4522 4523 gpio-controller; 4524 #gpio-cells = <2>; 4525 gpio-ranges = <&pinctrl 0 32 32>; 4526 interrupt-controller; 4527 #interrupt-cells = <2>; 4528 }; 4529 4530 gpio2: gpio@2ae20000 { 4531 compatible = "rockchip,gpio-bank"; 4532 reg = <0x0 0x2ae20000 0x0 0x200>; 4533 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 4534 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 4535 4536 gpio-controller; 4537 #gpio-cells = <2>; 4538 gpio-ranges = <&pinctrl 0 64 32>; 4539 interrupt-controller; 4540 #interrupt-cells = <2>; 4541 }; 4542 4543 gpio3: gpio@2ae30000 { 4544 compatible = "rockchip,gpio-bank"; 4545 reg = <0x0 0x2ae30000 0x0 0x200>; 4546 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 4547 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 4548 4549 gpio-controller; 4550 #gpio-cells = <2>; 4551 gpio-ranges = <&pinctrl 0 96 32>; 4552 interrupt-controller; 4553 #interrupt-cells = <2>; 4554 }; 4555 4556 gpio4: gpio@2ae40000 { 4557 compatible = "rockchip,gpio-bank"; 4558 reg = <0x0 0x2ae40000 0x0 0x200>; 4559 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 4560 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 4561 4562 gpio-controller; 4563 #gpio-cells = <2>; 4564 gpio-ranges = <&pinctrl 0 128 32>; 4565 interrupt-controller; 4566 #interrupt-cells = <2>; 4567 }; 4568 }; 4569}; 4570 4571#include "rk3576-pinctrl.dtsi" 4572
