1/* 2 * (C) Copyright 2023 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8 9/ { 10 aliases { 11 mmc0 = &sdhci; 12 mmc1 = &sdmmc; 13 }; 14 15 chosen { 16 stdout-path = &uart0; 17 u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, "same-as-spl"; 18 }; 19}; 20 21&firmware { 22 u-boot,dm-pre-reloc; 23}; 24 25&gpio0 { 26 u-boot,dm-spl; 27 status = "okay"; 28}; 29 30&gpio1 { 31 u-boot,dm-pre-reloc; 32 status = "okay"; 33}; 34 35&gpio2 { 36 u-boot,dm-pre-reloc; 37 status = "okay"; 38}; 39 40&gpio3 { 41 u-boot,dm-pre-reloc; 42 status = "okay"; 43}; 44 45&gpio4 { 46 u-boot,dm-pre-reloc; 47 status = "okay"; 48}; 49 50&scmi { 51 u-boot,dm-pre-reloc; 52}; 53 54&scmi_clk { 55 u-boot,dm-pre-reloc; 56}; 57 58&scmi_shmem { 59 u-boot,dm-pre-reloc; 60}; 61 62&sys_grf { 63 u-boot,dm-spl; 64 status = "okay"; 65}; 66 67&ioc_grf { 68 u-boot,dm-spl; 69 status = "okay"; 70}; 71 72&cru { 73 u-boot,dm-spl; 74 status = "okay"; 75}; 76 77&psci { 78 u-boot,dm-pre-reloc; 79 status = "okay"; 80}; 81 82&crypto { 83 u-boot,dm-spl; 84 status = "okay"; 85}; 86 87&uart0 { 88 u-boot,dm-spl; 89 status = "okay"; 90}; 91 92&rng { 93 u-boot,dm-pre-reloc; 94 status = "okay"; 95}; 96 97&sfc0 { 98 u-boot,dm-spl; 99 status = "okay"; 100 101 #address-cells = <1>; 102 #size-cells = <0>; 103 spi_nand: flash@0 { 104 u-boot,dm-spl; 105 compatible = "spi-nand"; 106 reg = <0>; 107 spi-tx-bus-width = <1>; 108 spi-rx-bus-width = <4>; 109 spi-max-frequency = <80000000>; 110 }; 111 112 spi_nor: flash@1 { 113 u-boot,dm-spl; 114 compatible = "jedec,spi-nor"; 115 label = "sfc_nor"; 116 reg = <0>; 117 spi-tx-bus-width = <1>; 118 spi-rx-bus-width = <4>; 119 spi-max-frequency = <80000000>; 120 }; 121}; 122 123&saradc { 124 u-boot,dm-pre-reloc; 125 status = "okay"; 126}; 127 128&sdmmc { 129 bus-width = <4>; 130 u-boot,dm-spl; 131 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; 132 status = "okay"; 133}; 134 135&sdhci { 136 bus-width = <8>; 137 u-boot,dm-spl; 138 mmc-hs400-1_8v; 139 mmc-hs400-enhanced-strobe; 140 non-removable; 141 status = "okay"; 142}; 143 144&pinctrl { 145 u-boot,dm-spl; 146 /delete-node/ sdmmc; 147 sdmmc { 148 u-boot,dm-spl; 149 sdmmc_bus4: sdmmc-bus4 { 150 u-boot,dm-spl; 151 rockchip,pins = 152 /* sdmmc_d0 */ 153 <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, 154 /* sdmmc_d1 */ 155 <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, 156 /* sdmmc_d2 */ 157 <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, 158 /* sdmmc_d3 */ 159 <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; 160 }; 161 162 sdmmc_clk: sdmmc-clk { 163 u-boot,dm-spl; 164 rockchip,pins = 165 /* sdmmc_clk */ 166 <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; 167 }; 168 169 sdmmc_cmd: sdmmc-cmd { 170 u-boot,dm-spl; 171 rockchip,pins = 172 /* sdmmc_cmd */ 173 <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; 174 }; 175 176 sdmmc_det: sdmmc-det { 177 u-boot,dm-spl; 178 rockchip,pins = 179 /* sdmmc_det */ 180 <0 RK_PA4 1 &pcfg_pull_up>; 181 }; 182 183 sdmmc_pwren: sdmmc-pwren { 184 u-boot,dm-spl; 185 rockchip,pins = 186 /* sdmmc_pwren */ 187 <0 RK_PA5 2 &pcfg_pull_none>; 188 }; 189 }; 190}; 191 192&pcfg_pull_up_drv_level_2 { 193 u-boot,dm-spl; 194}; 195 196&pcfg_pull_up { 197 u-boot,dm-spl; 198}; 199 200&pcfg_pull_none 201{ 202 u-boot,dm-spl; 203}; 204 205&php_grf { 206 u-boot,dm-pre-reloc; 207 status = "okay"; 208}; 209 210&pipe_phy0_grf { 211 u-boot,dm-pre-reloc; 212 status = "okay"; 213}; 214 215&pipe_phy1_grf { 216 u-boot,dm-pre-reloc; 217 status = "okay"; 218}; 219 220&usbdpphy_grf { 221 u-boot,dm-pre-reloc; 222}; 223 224&usbdp_phy { 225 u-boot,dm-pre-reloc; 226 status = "okay"; 227}; 228 229&usbdp_phy_u3 { 230 u-boot,dm-pre-reloc; 231 status = "okay"; 232}; 233 234&usb_grf { 235 u-boot,dm-pre-reloc; 236}; 237 238&usb2phy_grf { 239 u-boot,dm-pre-reloc; 240}; 241 242&u2phy0 { 243 u-boot,dm-pre-reloc; 244 status = "okay"; 245}; 246 247&u2phy0_otg { 248 u-boot,dm-pre-reloc; 249 status = "okay"; 250}; 251 252&ufs { 253 u-boot,dm-spl; 254 status = "okay"; 255}; 256