1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include <dt-bindings/power/rk3568-power.h> 11 12/ { 13 compatible = "rockchip,rk3568"; 14 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 serial0 = &uart0; 27 serial1 = &uart1; 28 serial2 = &uart2; 29 serial3 = &uart3; 30 serial4 = &uart4; 31 serial5 = &uart5; 32 serial6 = &uart6; 33 serial7 = &uart7; 34 serial8 = &uart8; 35 serial9 = &uart9; 36 spi0 = &spi0; 37 spi1 = &spi1; 38 spi2 = &spi2; 39 spi3 = &spi3; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a55"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 }; 52#if 0 53 cpu1: cpu@100 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x0 0x100>; 57 enable-method = "psci"; 58 }; 59 60 cpu2: cpu@200 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a55"; 63 reg = <0x0 0x200>; 64 enable-method = "psci"; 65 }; 66 67 cpu3: cpu@300 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a55"; 70 reg = <0x0 0x300>; 71 enable-method = "psci"; 72 }; 73#endif 74 }; 75 76#if 0 77 arm-pmu { 78 compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3"; 79 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 84 }; 85#endif 86 87 psci { 88 compatible = "arm,psci-1.0"; 89 method = "smc"; 90 }; 91 92 timer { 93 compatible = "arm,armv8-timer"; 94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 95 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 96 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 98 }; 99 100 xin24m: xin24m { 101 compatible = "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <24000000>; 104 clock-output-names = "xin24m"; 105 }; 106 107 usbdrd30: usbdrd { 108 compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; 109 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 110 <&cru ACLK_USB3OTG0>; 111 clock-names = "ref_clk", "suspend_clk", 112 "bus_clk"; 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 status = "disabled"; 117 118 usbdrd_dwc3: dwc3@fcc00000 { 119 compatible = "snps,dwc3"; 120 reg = <0x0 0xfcc00000 0x0 0x400000>; 121 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 122 dr_mode = "otg"; 123 phys = <&u2phy0_otg>; 124 phy-names = "usb2-phy"; 125 phy_type = "utmi_wide"; 126 power-domains = <&power RK3568_PD_PIPE>; 127 resets = <&cru SRST_USB3OTG0>; 128 reset-names = "usb3-otg"; 129 snps,dis_enblslpm_quirk; 130 snps,dis-u2-freeclk-exists-quirk; 131 snps,dis_u2_susphy_quirk; 132 snps,dis-del-phy-power-chg-quirk; 133 snps,dis-tx-ipgap-linecheck-quirk; 134 snps,xhci-trb-ent-quirk; 135 status = "disabled"; 136 }; 137 }; 138 139 usbhost30: usbhost { 140 compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; 141 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 142 <&cru ACLK_USB3OTG1>; 143 clock-names = "ref_clk", "suspend_clk", 144 "bus_clk"; 145 #address-cells = <2>; 146 #size-cells = <2>; 147 ranges; 148 status = "disabled"; 149 150 usbhost_dwc3: dwc3@fd000000 { 151 compatible = "snps,dwc3"; 152 reg = <0x0 0xfd000000 0x0 0x400000>; 153 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 154 dr_mode = "host"; 155 phys = <&u2phy0_host>; 156 phy-names = "usb2-phy"; 157 phy_type = "utmi_wide"; 158 power-domains = <&power RK3568_PD_PIPE>; 159 resets = <&cru SRST_USB3OTG1>; 160 reset-names = "usb3-host"; 161 snps,dis_enblslpm_quirk; 162 snps,dis-u2-freeclk-exists-quirk; 163 snps,dis_u2_susphy_quirk; 164 snps,dis-del-phy-power-chg-quirk; 165 snps,dis-tx-ipgap-linecheck-quirk; 166 snps,xhci-trb-ent-quirk; 167 status = "disabled"; 168 }; 169 }; 170 171 gic: interrupt-controller@fd400000 { 172 compatible = "arm,gic-v3"; 173 #interrupt-cells = <3>; 174 #address-cells = <2>; 175 #size-cells = <2>; 176 ranges; 177 interrupt-controller; 178 179 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 180 <0x0 0xfd460000 0 0xc0000>; /* GICR */ 181 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 182 its: interrupt-controller@fd440000 { 183 compatible = "arm,gic-v3-its"; 184 msi-controller; 185 reg = <0x0 0xfd440000 0x0 0x20000>; 186 }; 187 }; 188 189 usb_host0_ehci: usb@fd800000 { 190 compatible = "generic-ehci"; 191 reg = <0x0 0xfd800000 0x0 0x40000>; 192 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>; 194 clock-names = "usbhost", "arbiter"; 195 phys = <&u2phy1_otg>; 196 phy-names = "usb"; 197 status = "disabled"; 198 }; 199 200 usb_host0_ohci: usb@fd840000 { 201 compatible = "generic-ohci"; 202 reg = <0x0 0xfd840000 0x0 0x40000>; 203 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>; 205 clock-names = "usbhost", "arbiter"; 206 phys = <&u2phy1_otg>; 207 phy-names = "usb"; 208 status = "disabled"; 209 }; 210 211 usb_host1_ehci: usb@fd880000 { 212 compatible = "generic-ehci"; 213 reg = <0x0 0xfd880000 0x0 0x40000>; 214 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>; 216 clock-names = "usbhost", "arbiter"; 217 phys = <&u2phy1_host>; 218 phy-names = "usb"; 219 status = "disabled"; 220 }; 221 222 usb_host1_ohci: usb@fd8c0000 { 223 compatible = "generic-ohci"; 224 reg = <0x0 0xfd8c0000 0x0 0x40000>; 225 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>; 227 clock-names = "usbhost", "arbiter"; 228 phys = <&u2phy1_host>; 229 phy-names = "usb"; 230 status = "disabled"; 231 }; 232 233 pmugrf: syscon@fdc20000 { 234 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 235 reg = <0x0 0xfdc20000 0x0 0x10000>; 236 237 pmu_io_domains: io-domains { 238 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 239 status = "disabled"; 240 }; 241 }; 242 243 pipegrf: syscon@fdc50000 { 244 compatible = "rockchip,rk3568-pipegrf", "syscon"; 245 reg = <0x0 0xfdc50000 0x0 0x1000>; 246 }; 247 248 grf: syscon@fdc60000 { 249 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 250 reg = <0x0 0xfdc60000 0x0 0x10000>; 251 252 io_domains: io-domains { 253 compatible = "rockchip,rk3568-io-voltage-domain"; 254 status = "disabled"; 255 }; 256 }; 257 258 pipe_phy_grf0: syscon@fdc70000 { 259 compatible = "rockchip,pipe-phy-grf", "syscon"; 260 reg = <0x0 0xfdc70000 0x0 0x1000>; 261 }; 262 263 pipe_phy_grf1: syscon@fdc80000 { 264 compatible = "rockchip,pipe-phy-grf", "syscon"; 265 reg = <0x0 0xfdc80000 0x0 0x1000>; 266 }; 267 268 pipe_phy_grf2: syscon@fdc90000 { 269 compatible = "rockchip,pipe-phy-grf", "syscon"; 270 reg = <0x0 0xfdc90000 0x0 0x1000>; 271 }; 272 273 usb2phy0_grf: syscon@fdca0000 { 274 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 275 reg = <0x0 0xfdca0000 0x0 0x8000>; 276 }; 277 278 usb2phy1_grf: syscon@fdca8000 { 279 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 280 reg = <0x0 0xfdca8000 0x0 0x8000>; 281 }; 282 283 pmucru: clock-controller@fdd00000 { 284 compatible = "rockchip,rk3568-pmucru"; 285 reg = <0x0 0xfdd00000 0x0 0x1000>; 286 rockchip,grf = <&grf>; 287 #clock-cells = <1>; 288 #reset-cells = <1>; 289 }; 290 291 cru: clock-controller@fdd20000 { 292 compatible = "rockchip,rk3568-cru"; 293 reg = <0x0 0xfdd20000 0x0 0x1000>; 294 rockchip,grf = <&grf>; 295 #clock-cells = <1>; 296 #reset-cells = <1>; 297 298 assigned-clocks = 299 <&pmucru CLK_RTC_32K>, <&pmucru PLL_PPLL>, 300 <&pmucru PCLK_PMU>, <&cru PLL_CPLL>, 301 <&cru PLL_GPLL>, <&cru ARMCLK>, 302 <&cru ACLK_BUS>, <&cru PCLK_BUS>, 303 <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, 304 <&cru HCLK_TOP>, <&cru PCLK_TOP>, 305 <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>; 306 assigned-clock-rates = 307 <32768>, <100000000>, 308 <100000000>, <1000000000>, 309 <1188000000>, <600000000>, 310 <150000000>, <100000000>, 311 <300000000>, <200000000>, 312 <150000000>, <100000000>, 313 <300000000>, <150000000>; 314 assigned-clock-parents = 315 <&pmucru CLK_RTC32K_FRAC>; 316 }; 317 318 i2c0: i2c@fdd40000 { 319 compatible = "rockchip,rk3399-i2c"; 320 reg = <0x0 0xfdd40000 0x0 0x1000>; 321 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 322 clock-names = "i2c", "pclk"; 323 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&i2c0_xfer>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 status = "disabled"; 329 }; 330 331 uart0: serial@fdd50000 { 332 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 333 reg = <0x0 0xfdd50000 0x0 0x100>; 334 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 336 clock-names = "baudclk", "apb_pclk"; 337 reg-shift = <2>; 338 reg-io-width = <4>; 339 dmas = <&dmac0 0>, <&dmac0 1>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&uart0_xfer>; 342 status = "disabled"; 343 }; 344 345 pwm0: pwm@fdd70000 { 346 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 347 reg = <0x0 0xfdd70000 0x0 0x10>; 348 #pwm-cells = <3>; 349 pinctrl-names = "active"; 350 pinctrl-0 = <&pwm0m0_pins>; 351 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 352 clock-names = "pwm", "pclk"; 353 status = "disabled"; 354 }; 355 356 pwm1: pwm@fdd70010 { 357 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 358 reg = <0x0 0xfdd70010 0x0 0x10>; 359 #pwm-cells = <3>; 360 pinctrl-names = "active"; 361 pinctrl-0 = <&pwm1m0_pins>; 362 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 363 clock-names = "pwm", "pclk"; 364 status = "disabled"; 365 }; 366 367 pwm2: pwm@fdd70020 { 368 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 369 reg = <0x0 0xfdd70020 0x0 0x10>; 370 #pwm-cells = <3>; 371 pinctrl-names = "active"; 372 pinctrl-0 = <&pwm2m0_pins>; 373 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 374 clock-names = "pwm", "pclk"; 375 status = "disabled"; 376 }; 377 378 pwm3: pwm@fdd70030 { 379 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 380 reg = <0x0 0xfdd70030 0x0 0x10>; 381 #pwm-cells = <3>; 382 pinctrl-names = "active"; 383 pinctrl-0 = <&pwm3_pins>; 384 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 385 clock-names = "pwm", "pclk"; 386 status = "disabled"; 387 }; 388 389 pmu: power-management@fdd90000 { 390 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 391 reg = <0x0 0xfdd90000 0x0 0x1000>; 392 393 power: power-controller { 394 compatible = "rockchip,rk3568-power-controller"; 395 #power-domain-cells = <1>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 status = "okay"; 399 400 /* These power domains are grouped by VD_NPU */ 401 pd_npu@RK3568_PD_NPU { 402 reg = <RK3568_PD_NPU>; 403 pm_qos = <&qos_npu>; 404 }; 405 /* These power domains are grouped by VD_GPU */ 406 pd_gpu@RK3568_PD_GPU { 407 reg = <RK3568_PD_GPU>; 408 pm_qos = <&qos_gpu>; 409 }; 410 /* These power domains are grouped by VD_LOGIC */ 411 pd_vi@RK3568_PD_VI { 412 reg = <RK3568_PD_VI>; 413 pm_qos = <&qos_isp>, 414 <&qos_vicap0>, 415 <&qos_vicap1>; 416 }; 417 pd_vo@RK3568_PD_VO { 418 reg = <RK3568_PD_VO>; 419 pm_qos = <&qos_hdcp>, 420 <&qos_vop_m0>, 421 <&qos_vop_m1>; 422 }; 423 pd_rga@RK3568_PD_RGA { 424 reg = <RK3568_PD_RGA>; 425 pm_qos = <&qos_ebc>, 426 <&qos_iep>, 427 <&qos_jpeg_dec>, 428 <&qos_jpeg_enc>, 429 <&qos_rga_rd>, 430 <&qos_rga_wr>; 431 }; 432 pd_vpu@RK3568_PD_VPU { 433 reg = <RK3568_PD_VPU>; 434 pm_qos = <&qos_vpu>; 435 }; 436 pd_rkvdec@RK3568_PD_RKVDEC { 437 reg = <RK3568_PD_RKVDEC>; 438 pm_qos = <&qos_rkvdec>; 439 }; 440 pd_rkvenc@RK3568_PD_RKVENC { 441 reg = <RK3568_PD_RKVENC>; 442 pm_qos = <&qos_rkvenc_rd_m0>, 443 <&qos_rkvenc_rd_m1>, 444 <&qos_rkvenc_wr_m0>; 445 }; 446 pd_pipe@RK3568_PD_PIPE { 447 reg = <RK3568_PD_PIPE>; 448 pm_qos = <&qos_pcie2x1>, 449 <&qos_pcie3x1>, 450 <&qos_pcie3x2>, 451 <&qos_sata0>, 452 <&qos_sata1>, 453 <&qos_sata2>, 454 <&qos_usb3_0>, 455 <&qos_usb3_1>; 456 }; 457 }; 458 }; 459 460 gpu: gpu@fde60000 { 461 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 462 reg = <0x0 0xfde60000 0x0 0x4000>; 463 464 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 467 interrupt-names = "GPU", "MMU", "JOB"; 468 469 upthreshold = <40>; 470 downdifferential = <10>; 471 472 clocks = <&cru CLK_GPU>; 473 clock-names = "clk_mali"; 474 power-domains = <&power RK3568_PD_GPU>; 475 #cooling-cells = <2>; 476 operating-points-v2 = <&gpu_opp_table>; 477 478 status = "disabled"; 479 power_model { 480 compatible = "arm,mali-simple-power-model"; 481 static-coefficient = <411000>; 482 dynamic-coefficient = <733>; 483 ts = <32000 4700 (-80) 2>; 484 thermal-zone = "gpu-thermal"; 485 }; 486 }; 487 488 gpu_opp_table: opp-table2 { 489 compatible = "operating-points-v2"; 490 491 opp-200000000 { 492 opp-hz = /bits/ 64 <200000000>; 493 opp-microvolt = <1000000>; 494 }; 495 opp-300000000 { 496 opp-hz = /bits/ 64 <300000000>; 497 opp-microvolt = <1000000>; 498 }; 499 opp-400000000 { 500 opp-hz = /bits/ 64 <400000000>; 501 opp-microvolt = <1000000>; 502 }; 503 opp-600000000 { 504 opp-hz = /bits/ 64 <600000000>; 505 opp-microvolt = <1000000>; 506 }; 507 }; 508 509 qos_gpu: qos@fe128000 { 510 compatible = "syscon"; 511 reg = <0x0 0xfe128000 0x0 0x20>; 512 }; 513 514 qos_rkvenc_rd_m0: qos@fe138080 { 515 compatible = "syscon"; 516 reg = <0x0 0xfe138080 0x0 0x20>; 517 }; 518 519 qos_rkvenc_rd_m1: qos@fe138100 { 520 compatible = "syscon"; 521 reg = <0x0 0xfe138100 0x0 0x20>; 522 }; 523 524 qos_rkvenc_wr_m0: qos@fe138180 { 525 compatible = "syscon"; 526 reg = <0x0 0xfe138180 0x0 0x20>; 527 }; 528 529 qos_isp: qos@fe148000 { 530 compatible = "syscon"; 531 reg = <0x0 0xfe148000 0x0 0x20>; 532 }; 533 534 qos_vicap0: qos@fe148080 { 535 compatible = "syscon"; 536 reg = <0x0 0xfe148080 0x0 0x20>; 537 }; 538 539 qos_vicap1: qos@fe148100 { 540 compatible = "syscon"; 541 reg = <0x0 0xfe148100 0x0 0x20>; 542 }; 543 544 qos_vpu: qos@fe150000 { 545 compatible = "syscon"; 546 reg = <0x0 0xfe150000 0x0 0x20>; 547 }; 548 549 qos_ebc: qos@fe158000 { 550 compatible = "syscon"; 551 reg = <0x0 0xfe158000 0x0 0x20>; 552 }; 553 554 qos_iep: qos@fe158100 { 555 compatible = "syscon"; 556 reg = <0x0 0xfe158100 0x0 0x20>; 557 }; 558 559 qos_jpeg_dec: qos@fe158180 { 560 compatible = "syscon"; 561 reg = <0x0 0xfe158180 0x0 0x20>; 562 }; 563 564 qos_jpeg_enc: qos@fe158200 { 565 compatible = "syscon"; 566 reg = <0x0 0xfe158200 0x0 0x20>; 567 }; 568 569 qos_rga_rd: qos@fe158280 { 570 compatible = "syscon"; 571 reg = <0x0 0xfe158280 0x0 0x20>; 572 }; 573 574 qos_rga_wr: qos@fe158300 { 575 compatible = "syscon"; 576 reg = <0x0 0xfe158300 0x0 0x20>; 577 }; 578 579 qos_npu: qos@fe180000 { 580 compatible = "syscon"; 581 reg = <0x0 0xfe180000 0x0 0x20>; 582 }; 583 584 qos_pcie2x1: qos@fe190000 { 585 compatible = "syscon"; 586 reg = <0x0 0xfe190000 0x0 0x20>; 587 }; 588 589 qos_pcie3x1: qos@fe190080 { 590 compatible = "syscon"; 591 reg = <0x0 0xfe190080 0x0 0x20>; 592 }; 593 594 qos_pcie3x2: qos@fe190100 { 595 compatible = "syscon"; 596 reg = <0x0 0xfe190100 0x0 0x20>; 597 }; 598 599 qos_sata0: qos@fe190200 { 600 compatible = "syscon"; 601 reg = <0x0 0xfe190200 0x0 0x20>; 602 }; 603 604 qos_sata1: qos@fe190280 { 605 compatible = "syscon"; 606 reg = <0x0 0xfe190280 0x0 0x20>; 607 }; 608 609 qos_sata2: qos@fe190300 { 610 compatible = "syscon"; 611 reg = <0x0 0xfe190300 0x0 0x20>; 612 }; 613 614 qos_usb3_0: qos@fe190380 { 615 compatible = "syscon"; 616 reg = <0x0 0xfe190380 0x0 0x20>; 617 }; 618 619 qos_usb3_1: qos@fe190400 { 620 compatible = "syscon"; 621 reg = <0x0 0xfe190400 0x0 0x20>; 622 }; 623 624 qos_rkvdec: qos@fe198000 { 625 compatible = "syscon"; 626 reg = <0x0 0xfe198000 0x0 0x20>; 627 }; 628 629 qos_hdcp: qos@fe1a8000 { 630 compatible = "syscon"; 631 reg = <0x0 0xfe1a8000 0x0 0x20>; 632 }; 633 634 qos_vop_m0: qos@fe1a8080 { 635 compatible = "syscon"; 636 reg = <0x0 0xfe1a8080 0x0 0x20>; 637 }; 638 639 qos_vop_m1: qos@fe1a8100 { 640 compatible = "syscon"; 641 reg = <0x0 0xfe1a8100 0x0 0x20>; 642 }; 643 644 sdmmc2: dwmmc@fe000000 { 645 compatible = "rockchip,rk3568-dw-mshc", 646 "rockchip,rk3288-dw-mshc"; 647 reg = <0x0 0xfe000000 0x0 0x4000>; 648 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 649 max-frequency = <150000000>; 650 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 651 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 652 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 653 fifo-depth = <0x100>; 654 resets = <&cru SRST_SDMMC2>; 655 reset-names = "reset"; 656 status = "disabled"; 657 }; 658 659 sdmmc0: dwmmc@fe2b0000 { 660 compatible = "rockchip,rk3568-dw-mshc", 661 "rockchip,rk3288-dw-mshc"; 662 reg = <0x0 0xfe2b0000 0x0 0x4000>; 663 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 664 max-frequency = <150000000>; 665 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 666 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 667 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 668 fifo-depth = <0x100>; 669 resets = <&cru SRST_SDMMC0>; 670 reset-names = "reset"; 671 status = "disabled"; 672 }; 673 674 sdmmc1: dwmmc@fe2c0000 { 675 compatible = "rockchip,rk3568-dw-mshc", 676 "rockchip,rk3288-dw-mshc"; 677 reg = <0x0 0xfe2c0000 0x0 0x4000>; 678 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 679 max-frequency = <150000000>; 680 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 681 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 682 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 683 fifo-depth = <0x100>; 684 resets = <&cru SRST_SDMMC1>; 685 reset-names = "reset"; 686 status = "disabled"; 687 }; 688 689 sfc: sfc@fe300000 { 690 compatible = "rockchip,sfc"; 691 reg = <0x0 0xfe300000 0x0 0x4000>; 692 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 694 clock-names = "clk_sfc", "hclk_sfc"; 695 assigned-clocks = <&cru SCLK_SFC>; 696 assigned-clock-rates = <100000000>; 697 status = "disabled"; 698 }; 699 700 sdhci: sdhci@fe310000 { 701 compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci"; 702 reg = <0x0 0xfe310000 0x0 0x10000>; 703 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 704 assigned-clocks = <&cru CCLK_EMMC>, <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 705 assigned-clock-rates = <200000000>, <200000000>, <24000000>; 706 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 707 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 708 <&cru TCLK_EMMC>; 709 clock-names = "core", "bus", "axi", "block", "timer"; 710 status = "disabled"; 711 }; 712 713 nandc0: nandc@fe330000 { 714 compatible = "rockchip,rk-nandc"; 715 reg = <0x0 0xfe330000 0x0 0x4000>; 716 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 717 nandc_id = <0>; 718 clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>; 719 clock-names = "clk_nandc", "hclk_nandc"; 720 status = "disabled"; 721 }; 722 723 i2s0_8ch: i2s@fe400000 { 724 compatible = "rockchip,rk3568-i2s-tdm"; 725 reg = <0x0 0xfe400000 0x0 0x1000>; 726 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 728 clock-names = "mclk_tx", "mclk_rx", "hclk"; 729 dmas = <&dmac1 0>; 730 dma-names = "tx"; 731 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 732 reset-names = "tx-m", "rx-m"; 733 rockchip,cru = <&cru>; 734 rockchip,grf = <&grf>; 735 rockchip,playback-only; 736 status = "disabled"; 737 }; 738 739 i2s1_8ch: i2s@fe410000 { 740 compatible = "rockchip,rk3568-i2s-tdm"; 741 reg = <0x0 0xfe410000 0x0 0x1000>; 742 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 744 clock-names = "mclk_tx", "mclk_rx", "hclk"; 745 dmas = <&dmac1 2>, <&dmac1 3>; 746 dma-names = "tx", "rx"; 747 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 748 reset-names = "tx-m", "rx-m"; 749 rockchip,cru = <&cru>; 750 rockchip,grf = <&grf>; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&i2s1sclktxm0 753 &i2s1sclkrxm0 754 &i2s1lrcktxm0 755 &i2s1lrckrxm0 756 &i2s1sdi0m0 757 &i2s1sdi1m0 758 &i2s1sdi2m0 759 &i2s1sdi3m0 760 &i2s1sdo0m0 761 &i2s1sdo1m0 762 &i2s1sdo2m0 763 &i2s1sdo3m0>; 764 status = "disabled"; 765 }; 766 767 i2s2_2ch: i2s@fe420000 { 768 compatible = "rockchip,rk3568-i2s-tdm"; 769 reg = <0x0 0xfe420000 0x0 0x1000>; 770 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 772 clock-names = "mclk_tx", "mclk_rx", "hclk"; 773 dmas = <&dmac1 4>, <&dmac1 5>; 774 dma-names = "tx", "rx"; 775 rockchip,cru = <&cru>; 776 rockchip,grf = <&grf>; 777 rockchip,clk-trcm = <1>; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&i2s2sclktxm0 780 &i2s2lrcktxm0 781 &i2s2sdim0 782 &i2s2sdom0>; 783 status = "disabled"; 784 }; 785 786 i2s3_2ch: i2s@fe430000 { 787 compatible = "rockchip,rk3568-i2s-tdm"; 788 reg = <0x0 0xfe430000 0x0 0x1000>; 789 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>; 791 clock-names = "mclk_tx", "mclk_rx", "hclk"; 792 dmas = <&dmac1 6>, <&dmac1 7>; 793 dma-names = "tx", "rx"; 794 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 795 reset-names = "tx-m", "rx-m"; 796 rockchip,cru = <&cru>; 797 rockchip,grf = <&grf>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&i2s3sclkm0 800 &i2s3lrckm0 801 &i2s3sdim0 802 &i2s3sdom0>; 803 status = "disabled"; 804 }; 805 806 pdm: pdm@fe440000 { 807 compatible = "rockchip,rk3568-pdm", "rockchip,pdm"; 808 reg = <0x0 0xfe440000 0x0 0x1000>; 809 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 810 clock-names = "pdm_clk", "pdm_hclk"; 811 dmas = <&dmac1 9>; 812 dma-names = "rx"; 813 status = "disabled"; 814 }; 815 816 spdif_8ch: spdif@fe460000 { 817 compatible = "rockchip,rk3588-spdif"; 818 reg = <0x0 0xfe460000 0x0 0x1000>; 819 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 820 dmas = <&dmac1 1>; 821 dma-names = "tx"; 822 clock-names = "mclk", "hclk"; 823 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 824 pinctrl-names = "default"; 825 pinctrl-0 = <&spdifm0_pins>; 826 status = "disabled"; 827 }; 828 829 audpwm: audpwm@fe470000 { 830 compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1"; 831 reg = <0x0 0xfe470000 0x0 0x1000>; 832 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>; 833 clock-names = "clk", "hclk"; 834 dmas = <&dmac1 8>; 835 dma-names = "tx"; 836 rockchip,sample-width-bits = <11>; 837 rockchip,interpolat-points = <1>; 838 status = "disabled"; 839 }; 840 841 dig_acodec: codec-digital@fe478000 { 842 compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1"; 843 reg = <0x0 0xfe478000 0x0 0x1000>; 844 clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, <&cru HCLK_ACDCDIG>; 845 clock-names = "adc", "dac", "pclk"; 846 pinctrl-names = "default"; 847 pinctrl-0 = <&acodec_pins>; 848 resets = <&cru SRST_ACDCDIG>; 849 reset-names = "reset" ; 850 rockchip,grf = <&grf>; 851 status = "disabled"; 852 }; 853 854 dmac0: dmac@fe530000 { 855 compatible = "arm,pl330", "arm,primecell"; 856 reg = <0x0 0xfe530000 0x0 0x4000>; 857 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&cru ACLK_DMAC0>; 860 clock-names = "apb_pclk"; 861 #dma-cells = <1>; 862 arm,pl330-periph-burst; 863 }; 864 865 dmac1: dmac@fe550000 { 866 compatible = "arm,pl330", "arm,primecell"; 867 reg = <0x0 0xfe550000 0x0 0x4000>; 868 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&cru ACLK_DMAC1>; 871 clock-names = "apb_pclk"; 872 #dma-cells = <1>; 873 arm,pl330-periph-burst; 874 }; 875 876 can0: can@fe570000 { 877 compatible = "rockchip,canfd-1.0"; 878 reg = <0x0 0xfe570000 0x0 0x1000>; 879 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 881 clock-names = "baudclk", "apb_pclk"; 882 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 883 reset-names = "can", "can-apb"; 884 tx-fifo-depth = <1>; 885 rx-fifo-depth = <6>; 886 status = "disabled"; 887 }; 888 889 can1: can@fe580000 { 890 compatible = "rockchip,canfd-1.0"; 891 reg = <0x0 0xfe580000 0x0 0x1000>; 892 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 894 clock-names = "baudclk", "apb_pclk"; 895 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 896 reset-names = "can", "can-apb"; 897 tx-fifo-depth = <1>; 898 rx-fifo-depth = <6>; 899 status = "disabled"; 900 }; 901 902 can2: can@fe590000 { 903 compatible = "rockchip,canfd-1.0"; 904 reg = <0x0 0xfe590000 0x0 0x1000>; 905 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 907 clock-names = "baudclk", "apb_pclk"; 908 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; 909 reset-names = "can", "can-apb"; 910 tx-fifo-depth = <1>; 911 rx-fifo-depth = <6>; 912 status = "disabled"; 913 }; 914 915 i2c1: i2c@fe5a0000 { 916 compatible = "rockchip,rk3399-i2c"; 917 reg = <0x0 0xfe5a0000 0x0 0x1000>; 918 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 919 clock-names = "i2c", "pclk"; 920 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 921 pinctrl-names = "default"; 922 pinctrl-0 = <&i2c1_xfer>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 status = "disabled"; 926 }; 927 928 i2c2: i2c@fe5b0000 { 929 compatible = "rockchip,rk3399-i2c"; 930 reg = <0x0 0xfe5b0000 0x0 0x1000>; 931 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 932 clock-names = "i2c", "pclk"; 933 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&i2c2m0_xfer>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 status = "disabled"; 939 }; 940 941 i2c3: i2c@fe5c0000 { 942 compatible = "rockchip,rk3399-i2c"; 943 reg = <0x0 0xfe5c0000 0x0 0x1000>; 944 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 945 clock-names = "i2c", "pclk"; 946 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&i2c3m0_xfer>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 status = "disabled"; 952 }; 953 954 i2c4: i2c@fe5d0000 { 955 compatible = "rockchip,rk3399-i2c"; 956 reg = <0x0 0xfe5d0000 0x0 0x1000>; 957 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 958 clock-names = "i2c", "pclk"; 959 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&i2c4m0_xfer>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 i2c5: i2c@fe5e0000 { 968 compatible = "rockchip,rk3399-i2c"; 969 reg = <0x0 0xfe5e0000 0x0 0x1000>; 970 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 971 clock-names = "i2c", "pclk"; 972 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&i2c5m0_xfer>; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 status = "disabled"; 978 }; 979 980 wdt: watchdog@fe600000 { 981 compatible = "snps,dw-wdt"; 982 reg = <0x0 0xfe600000 0x0 0x100>; 983 clocks = <&cru PCLK_WDT_NS>; 984 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 985 status = "okay"; 986 }; 987 988 spi0: spi@fe610000 { 989 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 990 reg = <0x0 0xfe610000 0x0 0x1000>; 991 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 992 #address-cells = <1>; 993 #size-cells = <0>; 994 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 995 clock-names = "spiclk", "apb_pclk"; 996 dmas = <&dmac0 20>, <&dmac0 21>; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&spi0clkm0 &spi0cs0m0 &spi0cs1m0 &spi0misom0 &spi0mosim0>; 999 status = "disabled"; 1000 }; 1001 1002 spi1: spi@fe620000 { 1003 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1004 reg = <0x0 0xfe620000 0x0 0x1000>; 1005 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1009 clock-names = "spiclk", "apb_pclk"; 1010 dmas = <&dmac0 22>, <&dmac0 23>; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&spi1clkm0 &spi1cs0m0 &spi1cs1m0 &spi1misom0 &spi1mosim0>; 1013 status = "disabled"; 1014 }; 1015 1016 spi2: spi@fe630000 { 1017 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1018 reg = <0x0 0xfe630000 0x0 0x1000>; 1019 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1023 clock-names = "spiclk", "apb_pclk"; 1024 dmas = <&dmac0 24>, <&dmac0 25>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&spi2clkm0 &spi2cs0m0 &spi2cs1m0 &spi2misom0 &spi2mosim0>; 1027 status = "disabled"; 1028 }; 1029 1030 spi3: spi@fe640000 { 1031 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1032 reg = <0x0 0xfe640000 0x0 0x1000>; 1033 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1037 clock-names = "spiclk", "apb_pclk"; 1038 dmas = <&dmac0 26>, <&dmac0 27>; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&spi3clkm0 &spi3cs0m0 &spi3cs1m0 &spi3misom0 &spi3mosim0>; 1041 status = "disabled"; 1042 }; 1043 1044 uart1: serial@fe650000 { 1045 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1046 reg = <0x0 0xfe650000 0x0 0x100>; 1047 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1049 clock-names = "baudclk", "apb_pclk"; 1050 reg-shift = <2>; 1051 reg-io-width = <4>; 1052 dmas = <&dmac0 2>, <&dmac0 3>; 1053 pinctrl-names = "default"; 1054 pinctrl-0 = <&uart1m0_xfer>; 1055 status = "disabled"; 1056 }; 1057 1058 uart2: serial@fe660000 { 1059 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1060 reg = <0x0 0xfe660000 0x0 0x100>; 1061 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1063 clock-names = "baudclk", "apb_pclk"; 1064 reg-shift = <2>; 1065 reg-io-width = <4>; 1066 dmas = <&dmac0 4>, <&dmac0 5>; 1067 pinctrl-names = "default"; 1068 pinctrl-0 = <&uart2m0_xfer>; 1069 status = "disabled"; 1070 }; 1071 1072 uart3: serial@fe670000 { 1073 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1074 reg = <0x0 0xfe670000 0x0 0x100>; 1075 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1076 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1077 clock-names = "baudclk", "apb_pclk"; 1078 reg-shift = <2>; 1079 reg-io-width = <4>; 1080 dmas = <&dmac0 6>, <&dmac0 7>; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&uart3m0_xfer>; 1083 status = "disabled"; 1084 }; 1085 1086 uart4: serial@fe680000 { 1087 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1088 reg = <0x0 0xfe680000 0x0 0x100>; 1089 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1091 clock-names = "baudclk", "apb_pclk"; 1092 reg-shift = <2>; 1093 reg-io-width = <4>; 1094 dmas = <&dmac0 8>, <&dmac0 9>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&uart4m0_xfer>; 1097 status = "disabled"; 1098 }; 1099 1100 uart5: serial@fe690000 { 1101 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1102 reg = <0x0 0xfe690000 0x0 0x100>; 1103 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1105 clock-names = "baudclk", "apb_pclk"; 1106 reg-shift = <2>; 1107 reg-io-width = <4>; 1108 dmas = <&dmac0 10>, <&dmac0 11>; 1109 pinctrl-names = "default"; 1110 pinctrl-0 = <&uart5m0_xfer>; 1111 status = "disabled"; 1112 }; 1113 1114 uart6: serial@fe6a0000 { 1115 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1116 reg = <0x0 0xfe6a0000 0x0 0x100>; 1117 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1119 clock-names = "baudclk", "apb_pclk"; 1120 reg-shift = <2>; 1121 reg-io-width = <4>; 1122 dmas = <&dmac0 12>, <&dmac0 13>; 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&uart6m0_xfer>; 1125 status = "disabled"; 1126 }; 1127 1128 uart7: serial@fe6b0000 { 1129 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1130 reg = <0x0 0xfe6b0000 0x0 0x100>; 1131 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1133 clock-names = "baudclk", "apb_pclk"; 1134 reg-shift = <2>; 1135 reg-io-width = <4>; 1136 dmas = <&dmac0 14>, <&dmac0 15>; 1137 pinctrl-names = "default"; 1138 pinctrl-0 = <&uart7m0_xfer>; 1139 status = "disabled"; 1140 }; 1141 1142 uart8: serial@fe6c0000 { 1143 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1144 reg = <0x0 0xfe6c0000 0x0 0x100>; 1145 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1147 clock-names = "baudclk", "apb_pclk"; 1148 reg-shift = <2>; 1149 reg-io-width = <4>; 1150 dmas = <&dmac0 16>, <&dmac0 17>; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&uart8m0_xfer>; 1153 status = "disabled"; 1154 }; 1155 1156 uart9: serial@fe6d0000 { 1157 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1158 reg = <0x0 0xfe6d0000 0x0 0x100>; 1159 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1161 clock-names = "baudclk", "apb_pclk"; 1162 reg-shift = <2>; 1163 reg-io-width = <4>; 1164 dmas = <&dmac0 18>, <&dmac0 19>; 1165 pinctrl-names = "default"; 1166 pinctrl-0 = <&uart9m0_xfer>; 1167 status = "disabled"; 1168 }; 1169 1170 pwm4: pwm@fe6e0000 { 1171 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1172 reg = <0x0 0xfe6e0000 0x0 0x10>; 1173 #pwm-cells = <3>; 1174 pinctrl-names = "active"; 1175 pinctrl-0 = <&pwm4_pins>; 1176 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1177 clock-names = "pwm", "pclk"; 1178 status = "disabled"; 1179 }; 1180 1181 pwm5: pwm@fe6e0010 { 1182 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1183 reg = <0x0 0xfe6e0010 0x0 0x10>; 1184 #pwm-cells = <3>; 1185 pinctrl-names = "active"; 1186 pinctrl-0 = <&pwm5_pins>; 1187 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1188 clock-names = "pwm", "pclk"; 1189 status = "disabled"; 1190 }; 1191 1192 pwm6: pwm@fe6e0020 { 1193 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1194 reg = <0x0 0xfe6e0020 0x0 0x10>; 1195 #pwm-cells = <3>; 1196 pinctrl-names = "active"; 1197 pinctrl-0 = <&pwm6_pins>; 1198 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1199 clock-names = "pwm", "pclk"; 1200 status = "disabled"; 1201 }; 1202 1203 pwm7: pwm@fe6e0030 { 1204 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1205 reg = <0x0 0xfe6e0030 0x0 0x10>; 1206 #pwm-cells = <3>; 1207 pinctrl-names = "active"; 1208 pinctrl-0 = <&pwm7_pins>; 1209 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1210 clock-names = "pwm", "pclk"; 1211 status = "disabled"; 1212 }; 1213 1214 pwm8: pwm@fe6f0000 { 1215 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1216 reg = <0x0 0xfe6f0000 0x0 0x10>; 1217 #pwm-cells = <3>; 1218 pinctrl-names = "active"; 1219 pinctrl-0 = <&pwm8m0_pins>; 1220 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1221 clock-names = "pwm", "pclk"; 1222 status = "disabled"; 1223 }; 1224 1225 pwm9: pwm@fe6f0010 { 1226 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1227 reg = <0x0 0xfe6f0010 0x0 0x10>; 1228 #pwm-cells = <3>; 1229 pinctrl-names = "active"; 1230 pinctrl-0 = <&pwm9m0_pins>; 1231 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1232 clock-names = "pwm", "pclk"; 1233 status = "disabled"; 1234 }; 1235 1236 pwm10: pwm@fe6f0020 { 1237 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1238 reg = <0x0 0xfe6f0020 0x0 0x10>; 1239 #pwm-cells = <3>; 1240 pinctrl-names = "active"; 1241 pinctrl-0 = <&pwm10m0_pins>; 1242 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1243 clock-names = "pwm", "pclk"; 1244 status = "disabled"; 1245 }; 1246 1247 pwm11: pwm@fe6f0030 { 1248 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1249 reg = <0x0 0xfe6f0030 0x0 0x10>; 1250 #pwm-cells = <3>; 1251 pinctrl-names = "active"; 1252 pinctrl-0 = <&pwm11m0_pins>; 1253 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1254 clock-names = "pwm", "pclk"; 1255 status = "disabled"; 1256 }; 1257 1258 pwm12: pwm@fe700000 { 1259 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1260 reg = <0x0 0xfe700000 0x0 0x10>; 1261 #pwm-cells = <3>; 1262 pinctrl-names = "active"; 1263 pinctrl-0 = <&pwm12m0_pins>; 1264 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1265 clock-names = "pwm", "pclk"; 1266 status = "disabled"; 1267 }; 1268 1269 pwm13: pwm@fe700010 { 1270 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1271 reg = <0x0 0xfe700010 0x0 0x10>; 1272 #pwm-cells = <3>; 1273 pinctrl-names = "active"; 1274 pinctrl-0 = <&pwm13m0_pins>; 1275 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1276 clock-names = "pwm", "pclk"; 1277 status = "disabled"; 1278 }; 1279 1280 pwm14: pwm@fe700020 { 1281 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1282 reg = <0x0 0xfe700020 0x0 0x10>; 1283 #pwm-cells = <3>; 1284 pinctrl-names = "active"; 1285 pinctrl-0 = <&pwm14m0_pins>; 1286 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1287 clock-names = "pwm", "pclk"; 1288 status = "disabled"; 1289 }; 1290 1291 pwm15: pwm@fe700030 { 1292 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1293 reg = <0x0 0xfe700030 0x0 0x10>; 1294 #pwm-cells = <3>; 1295 pinctrl-names = "active"; 1296 pinctrl-0 = <&pwm15m0_pins>; 1297 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1298 clock-names = "pwm", "pclk"; 1299 status = "disabled"; 1300 }; 1301 1302 saradc: saradc@fe720000 { 1303 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1304 reg = <0x0 0xfe720000 0x0 0x100>; 1305 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1306 #io-channel-cells = <1>; 1307 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1308 clock-names = "saradc", "apb_pclk"; 1309 resets = <&cru SRST_P_SARADC>; 1310 reset-names = "saradc-apb"; 1311 status = "disabled"; 1312 }; 1313 1314 combphy0_us: phy@fe820000 { 1315 compatible = "rockchip,rk3568-naneng-combphy"; 1316 reg = <0x0 0xfe820000 0x0 0x100>; 1317 #phy-cells = <1>; 1318 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>; 1319 clock-names = "refclk", "apbclk"; 1320 resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; 1321 reset-names = "combphy-apb", "combphy"; 1322 rockchip,pipe-grf = <&pipegrf>; 1323 rockchip,pipe-phy-grf = <&pipe_phy_grf0>; 1324 status = "disabled"; 1325 }; 1326 1327 combphy1_usq: phy@fe830000 { 1328 compatible = "rockchip,rk3568-naneng-combphy"; 1329 reg = <0x0 0xfe830000 0x0 0x100>; 1330 #phy-cells = <1>; 1331 clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>; 1332 clock-names = "refclk", "apbclk"; 1333 resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; 1334 reset-names = "combphy-apb", "combphy"; 1335 rockchip,pipe-grf = <&pipegrf>; 1336 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1337 status = "disabled"; 1338 }; 1339 1340 combphy2_psq: phy@fe840000 { 1341 compatible = "rockchip,rk3568-naneng-combphy"; 1342 reg = <0x0 0xfe840000 0x0 0x100>; 1343 #phy-cells = <1>; 1344 clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>; 1345 clock-names = "refclk", "apbclk"; 1346 resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; 1347 reset-names = "combphy-apb", "combphy"; 1348 rockchip,pipe-grf = <&pipegrf>; 1349 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1350 status = "disabled"; 1351 }; 1352 1353 usb2phy0: usb2-phy@fe8a0000 { 1354 compatible = "rockchip,rk3568-usb2phy"; 1355 reg = <0x0 0xfe8a0000 0x0 0x10000>; 1356 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1357 clocks = <&pmucru CLK_USBPHY0_REF>; 1358 clock-names = "phyclk"; 1359 #clock-cells = <0>; 1360 clock-output-names = "usb480m_phy"; 1361 rockchip,usbgrf = <&usb2phy0_grf>; 1362 status = "disabled"; 1363 1364 u2phy0_host: host-port { 1365 #phy-cells = <0>; 1366 status = "disabled"; 1367 }; 1368 1369 u2phy0_otg: otg-port { 1370 #phy-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 }; 1374 1375 usb2phy1: usb2-phy@fe8b0000 { 1376 compatible = "rockchip,rk3568-usb2phy"; 1377 reg = <0x0 0xfe8b0000 0x0 0x10000>; 1378 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1379 clocks = <&pmucru CLK_USBPHY1_REF>; 1380 clock-names = "phyclk"; 1381 rockchip,usbgrf = <&usb2phy1_grf>; 1382 status = "disabled"; 1383 1384 u2phy1_host: host-port { 1385 #phy-cells = <0>; 1386 status = "disabled"; 1387 }; 1388 1389 u2phy1_otg: otg-port { 1390 #phy-cells = <0>; 1391 status = "disabled"; 1392 }; 1393 }; 1394 1395 pinctrl: pinctrl { 1396 compatible = "rockchip,rk3568-pinctrl"; 1397 rockchip,grf = <&grf>; 1398 rockchip,pmu = <&pmugrf>; 1399 #address-cells = <2>; 1400 #size-cells = <2>; 1401 ranges; 1402 1403 gpio0: gpio@fdd60000 { 1404 compatible = "rockchip,gpio-bank"; 1405 reg = <0x0 0xfdd60000 0x0 0x100>; 1406 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1407 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1408 1409 gpio-controller; 1410 #gpio-cells = <2>; 1411 gpio-ranges = <&pinctrl 0 0 32>; 1412 interrupt-controller; 1413 #interrupt-cells = <2>; 1414 }; 1415 1416 gpio1: gpio@fe740000 { 1417 compatible = "rockchip,gpio-bank"; 1418 reg = <0x0 0xfe740000 0x0 0x100>; 1419 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1420 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1421 1422 gpio-controller; 1423 #gpio-cells = <2>; 1424 gpio-ranges = <&pinctrl 0 32 32>; 1425 interrupt-controller; 1426 #interrupt-cells = <2>; 1427 }; 1428 1429 gpio2: gpio@fe750000 { 1430 compatible = "rockchip,gpio-bank"; 1431 reg = <0x0 0xfe750000 0x0 0x100>; 1432 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1433 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1434 1435 gpio-controller; 1436 #gpio-cells = <2>; 1437 gpio-ranges = <&pinctrl 0 64 32>; 1438 interrupt-controller; 1439 #interrupt-cells = <2>; 1440 }; 1441 1442 gpio3: gpio@fe760000 { 1443 compatible = "rockchip,gpio-bank"; 1444 reg = <0x0 0xfe750000 0x0 0x100>; 1445 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1447 1448 gpio-controller; 1449 #gpio-cells = <2>; 1450 gpio-ranges = <&pinctrl 0 96 32>; 1451 interrupt-controller; 1452 #interrupt-cells = <2>; 1453 }; 1454 1455 gpio4: gpio@fe770000 { 1456 compatible = "rockchip,gpio-bank"; 1457 reg = <0x0 0xfe770000 0x0 0x100>; 1458 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1459 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1460 1461 gpio-controller; 1462 #gpio-cells = <2>; 1463 gpio-ranges = <&pinctrl 0 128 32>; 1464 interrupt-controller; 1465 #interrupt-cells = <2>; 1466 }; 1467 }; 1468}; 1469 1470#include "rk3568-pinctrl.dtsi" 1471