1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include <dt-bindings/power/rk3568-power.h> 11 12/ { 13 compatible = "rockchip,rk3568"; 14 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 serial0 = &uart0; 27 serial1 = &uart1; 28 serial2 = &uart2; 29 serial3 = &uart3; 30 serial4 = &uart4; 31 serial5 = &uart5; 32 serial6 = &uart6; 33 serial7 = &uart7; 34 serial8 = &uart8; 35 serial9 = &uart9; 36 spi0 = &spi0; 37 spi1 = &spi1; 38 spi2 = &spi2; 39 spi3 = &spi3; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a55"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 }; 52#if 0 53 cpu1: cpu@100 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x0 0x100>; 57 enable-method = "psci"; 58 }; 59 60 cpu2: cpu@200 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a55"; 63 reg = <0x0 0x200>; 64 enable-method = "psci"; 65 }; 66 67 cpu3: cpu@300 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a55"; 70 reg = <0x0 0x300>; 71 enable-method = "psci"; 72 }; 73#endif 74 }; 75 76#if 0 77 arm-pmu { 78 compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3"; 79 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 84 }; 85#endif 86 87 psci { 88 compatible = "arm,psci-1.0"; 89 method = "smc"; 90 }; 91 92 timer { 93 compatible = "arm,armv8-timer"; 94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 95 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 96 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 98 }; 99 100 xin24m: xin24m { 101 compatible = "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <24000000>; 104 clock-output-names = "xin24m"; 105 }; 106 107 usbdrd30: usbdrd { 108 compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; 109 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 110 <&cru ACLK_USB3OTG0>; 111 clock-names = "ref_clk", "suspend_clk", 112 "bus_clk"; 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 status = "disabled"; 117 118 usbdrd_dwc3: dwc3@fcc00000 { 119 compatible = "snps,dwc3"; 120 reg = <0x0 0xfcc00000 0x0 0x400000>; 121 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 122 dr_mode = "otg"; 123 phy_type = "utmi_wide"; 124 power-domains = <&power RK3568_PD_PIPE>; 125 resets = <&cru SRST_USB3OTG0>; 126 reset-names = "usb3-otg"; 127 snps,dis_enblslpm_quirk; 128 snps,dis-u2-freeclk-exists-quirk; 129 snps,dis_u2_susphy_quirk; 130 snps,dis-del-phy-power-chg-quirk; 131 snps,dis-tx-ipgap-linecheck-quirk; 132 snps,xhci-trb-ent-quirk; 133 status = "disabled"; 134 }; 135 }; 136 137 usbhost30: usbhost { 138 compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; 139 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 140 <&cru ACLK_USB3OTG1>; 141 clock-names = "ref_clk", "suspend_clk", 142 "bus_clk"; 143 #address-cells = <2>; 144 #size-cells = <2>; 145 ranges; 146 status = "disabled"; 147 148 usbhost_dwc3: dwc3@fd000000 { 149 compatible = "snps,dwc3"; 150 reg = <0x0 0xfd000000 0x0 0x400000>; 151 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 152 dr_mode = "host"; 153 phy_type = "utmi_wide"; 154 power-domains = <&power RK3568_PD_PIPE>; 155 resets = <&cru SRST_USB3OTG1>; 156 reset-names = "usb3-host"; 157 snps,dis_enblslpm_quirk; 158 snps,dis-u2-freeclk-exists-quirk; 159 snps,dis_u2_susphy_quirk; 160 snps,dis-del-phy-power-chg-quirk; 161 snps,dis-tx-ipgap-linecheck-quirk; 162 snps,xhci-trb-ent-quirk; 163 status = "disabled"; 164 }; 165 }; 166 167 gic: interrupt-controller@fd400000 { 168 compatible = "arm,gic-v3"; 169 #interrupt-cells = <3>; 170 #address-cells = <2>; 171 #size-cells = <2>; 172 ranges; 173 interrupt-controller; 174 175 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 176 <0x0 0xfd460000 0 0xc0000>; /* GICR */ 177 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 178 its: interrupt-controller@fd440000 { 179 compatible = "arm,gic-v3-its"; 180 msi-controller; 181 reg = <0x0 0xfd440000 0x0 0x20000>; 182 }; 183 }; 184 185 usb_host0_ehci: usb@fd800000 { 186 compatible = "generic-ehci"; 187 reg = <0x0 0xfd800000 0x0 0x40000>; 188 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>; 190 clock-names = "usbhost", "arbiter"; 191 status = "disabled"; 192 }; 193 194 usb_host0_ohci: usb@fd840000 { 195 compatible = "generic-ohci"; 196 reg = <0x0 0xfd840000 0x0 0x40000>; 197 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>; 199 clock-names = "usbhost", "arbiter"; 200 status = "disabled"; 201 }; 202 203 usb_host1_ehci: usb@fd880000 { 204 compatible = "generic-ehci"; 205 reg = <0x0 0xfd880000 0x0 0x40000>; 206 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>; 208 clock-names = "usbhost", "arbiter"; 209 status = "disabled"; 210 }; 211 212 usb_host1_ohci: usb@fd8c0000 { 213 compatible = "generic-ohci"; 214 reg = <0x0 0xfd8c0000 0x0 0x40000>; 215 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>; 217 clock-names = "usbhost", "arbiter"; 218 status = "disabled"; 219 }; 220 221 pmugrf: syscon@fdc20000 { 222 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 223 reg = <0x0 0xfdc20000 0x0 0x10000>; 224 225 pmu_io_domains: io-domains { 226 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 227 status = "disabled"; 228 }; 229 }; 230 231 pipegrf: syscon@fdc50000 { 232 compatible = "rockchip,rk3568-pipegrf", "syscon"; 233 reg = <0x0 0xfdc50000 0x0 0x1000>; 234 }; 235 236 grf: syscon@fdc60000 { 237 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 238 reg = <0x0 0xfdc60000 0x0 0x10000>; 239 240 io_domains: io-domains { 241 compatible = "rockchip,rk3568-io-voltage-domain"; 242 status = "disabled"; 243 }; 244 }; 245 246 pipe_phy_grf0: syscon@fdc70000 { 247 compatible = "rockchip,pipe-phy-grf", "syscon"; 248 reg = <0x0 0xfdc70000 0x0 0x1000>; 249 }; 250 251 pipe_phy_grf1: syscon@fdc80000 { 252 compatible = "rockchip,pipe-phy-grf", "syscon"; 253 reg = <0x0 0xfdc80000 0x0 0x1000>; 254 }; 255 256 pipe_phy_grf2: syscon@fdc90000 { 257 compatible = "rockchip,pipe-phy-grf", "syscon"; 258 reg = <0x0 0xfdc90000 0x0 0x1000>; 259 }; 260 261 pmucru: clock-controller@fdd00000 { 262 compatible = "rockchip,rk3568-pmucru"; 263 reg = <0x0 0xfdd00000 0x0 0x1000>; 264 rockchip,grf = <&grf>; 265 #clock-cells = <1>; 266 #reset-cells = <1>; 267 }; 268 269 cru: clock-controller@fdd20000 { 270 compatible = "rockchip,rk3568-cru"; 271 reg = <0x0 0xfdd20000 0x0 0x1000>; 272 rockchip,grf = <&grf>; 273 #clock-cells = <1>; 274 #reset-cells = <1>; 275 276 assigned-clocks = 277 <&pmucru CLK_RTC_32K>, <&pmucru PLL_PPLL>, 278 <&pmucru PCLK_PMU>, <&cru PLL_CPLL>, 279 <&cru PLL_GPLL>, <&cru ARMCLK>, 280 <&cru ACLK_BUS>, <&cru PCLK_BUS>, 281 <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, 282 <&cru HCLK_TOP>, <&cru PCLK_TOP>, 283 <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>; 284 assigned-clock-rates = 285 <32768>, <100000000>, 286 <100000000>, <1000000000>, 287 <1188000000>, <600000000>, 288 <150000000>, <100000000>, 289 <300000000>, <200000000>, 290 <150000000>, <100000000>, 291 <300000000>, <150000000>; 292 assigned-clock-parents = 293 <&pmucru CLK_RTC32K_FRAC>; 294 }; 295 296 i2c0: i2c@fdd40000 { 297 compatible = "rockchip,rk3399-i2c"; 298 reg = <0x0 0xfdd40000 0x0 0x1000>; 299 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 300 clock-names = "i2c", "pclk"; 301 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&i2c0_xfer>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 status = "disabled"; 307 }; 308 309 uart0: serial@fdd50000 { 310 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 311 reg = <0x0 0xfdd50000 0x0 0x100>; 312 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 314 clock-names = "baudclk", "apb_pclk"; 315 reg-shift = <2>; 316 reg-io-width = <4>; 317 dmas = <&dmac0 0>, <&dmac0 1>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&uart0_xfer>; 320 status = "disabled"; 321 }; 322 323 pwm0: pwm@fdd70000 { 324 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 325 reg = <0x0 0xfdd70000 0x0 0x10>; 326 #pwm-cells = <3>; 327 pinctrl-names = "active"; 328 pinctrl-0 = <&pwm0m0_pins>; 329 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 330 clock-names = "pwm", "pclk"; 331 status = "disabled"; 332 }; 333 334 pwm1: pwm@fdd70010 { 335 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 336 reg = <0x0 0xfdd70010 0x0 0x10>; 337 #pwm-cells = <3>; 338 pinctrl-names = "active"; 339 pinctrl-0 = <&pwm1m0_pins>; 340 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 341 clock-names = "pwm", "pclk"; 342 status = "disabled"; 343 }; 344 345 pwm2: pwm@fdd70020 { 346 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 347 reg = <0x0 0xfdd70020 0x0 0x10>; 348 #pwm-cells = <3>; 349 pinctrl-names = "active"; 350 pinctrl-0 = <&pwm2m0_pins>; 351 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 352 clock-names = "pwm", "pclk"; 353 status = "disabled"; 354 }; 355 356 pwm3: pwm@fdd70030 { 357 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 358 reg = <0x0 0xfdd70030 0x0 0x10>; 359 #pwm-cells = <3>; 360 pinctrl-names = "active"; 361 pinctrl-0 = <&pwm3_pins>; 362 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 363 clock-names = "pwm", "pclk"; 364 status = "disabled"; 365 }; 366 367 pmu: power-management@fdd90000 { 368 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 369 reg = <0x0 0xfdd90000 0x0 0x1000>; 370 371 power: power-controller { 372 compatible = "rockchip,rk3568-power-controller"; 373 #power-domain-cells = <1>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 status = "okay"; 377 378 /* These power domains are grouped by VD_NPU */ 379 pd_npu@RK3568_PD_NPU { 380 reg = <RK3568_PD_NPU>; 381 pm_qos = <&qos_npu>; 382 }; 383 /* These power domains are grouped by VD_GPU */ 384 pd_gpu@RK3568_PD_GPU { 385 reg = <RK3568_PD_GPU>; 386 pm_qos = <&qos_gpu>; 387 }; 388 /* These power domains are grouped by VD_LOGIC */ 389 pd_vi@RK3568_PD_VI { 390 reg = <RK3568_PD_VI>; 391 pm_qos = <&qos_isp>, 392 <&qos_vicap0>, 393 <&qos_vicap1>; 394 }; 395 pd_vo@RK3568_PD_VO { 396 reg = <RK3568_PD_VO>; 397 pm_qos = <&qos_hdcp>, 398 <&qos_vop_m0>, 399 <&qos_vop_m1>; 400 }; 401 pd_rga@RK3568_PD_RGA { 402 reg = <RK3568_PD_RGA>; 403 pm_qos = <&qos_ebc>, 404 <&qos_iep>, 405 <&qos_jpeg_dec>, 406 <&qos_jpeg_enc>, 407 <&qos_rga_rd>, 408 <&qos_rga_wr>; 409 }; 410 pd_vpu@RK3568_PD_VPU { 411 reg = <RK3568_PD_VPU>; 412 pm_qos = <&qos_vpu>; 413 }; 414 pd_rkvdec@RK3568_PD_RKVDEC { 415 reg = <RK3568_PD_RKVDEC>; 416 pm_qos = <&qos_rkvdec>; 417 }; 418 pd_rkvenc@RK3568_PD_RKVENC { 419 reg = <RK3568_PD_RKVENC>; 420 pm_qos = <&qos_rkvenc_rd_m0>, 421 <&qos_rkvenc_rd_m1>, 422 <&qos_rkvenc_wr_m0>; 423 }; 424 pd_pipe@RK3568_PD_PIPE { 425 reg = <RK3568_PD_PIPE>; 426 pm_qos = <&qos_pcie2x1>, 427 <&qos_pcie3x1>, 428 <&qos_pcie3x2>, 429 <&qos_sata0>, 430 <&qos_sata1>, 431 <&qos_sata2>, 432 <&qos_usb3_0>, 433 <&qos_usb3_1>; 434 }; 435 }; 436 }; 437 438 gpu: gpu@fde60000 { 439 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 440 reg = <0x0 0xfde60000 0x0 0x4000>; 441 442 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 445 interrupt-names = "GPU", "MMU", "JOB"; 446 447 upthreshold = <40>; 448 downdifferential = <10>; 449 450 clocks = <&cru CLK_GPU>; 451 clock-names = "clk_mali"; 452 power-domains = <&power RK3568_PD_GPU>; 453 #cooling-cells = <2>; 454 operating-points-v2 = <&gpu_opp_table>; 455 456 status = "disabled"; 457 power_model { 458 compatible = "arm,mali-simple-power-model"; 459 static-coefficient = <411000>; 460 dynamic-coefficient = <733>; 461 ts = <32000 4700 (-80) 2>; 462 thermal-zone = "gpu-thermal"; 463 }; 464 }; 465 466 gpu_opp_table: opp-table2 { 467 compatible = "operating-points-v2"; 468 469 opp-200000000 { 470 opp-hz = /bits/ 64 <200000000>; 471 opp-microvolt = <1000000>; 472 }; 473 opp-300000000 { 474 opp-hz = /bits/ 64 <300000000>; 475 opp-microvolt = <1000000>; 476 }; 477 opp-400000000 { 478 opp-hz = /bits/ 64 <400000000>; 479 opp-microvolt = <1000000>; 480 }; 481 opp-600000000 { 482 opp-hz = /bits/ 64 <600000000>; 483 opp-microvolt = <1000000>; 484 }; 485 }; 486 487 qos_gpu: qos@fe128000 { 488 compatible = "syscon"; 489 reg = <0x0 0xfe128000 0x0 0x20>; 490 }; 491 492 qos_rkvenc_rd_m0: qos@fe138080 { 493 compatible = "syscon"; 494 reg = <0x0 0xfe138080 0x0 0x20>; 495 }; 496 497 qos_rkvenc_rd_m1: qos@fe138100 { 498 compatible = "syscon"; 499 reg = <0x0 0xfe138100 0x0 0x20>; 500 }; 501 502 qos_rkvenc_wr_m0: qos@fe138180 { 503 compatible = "syscon"; 504 reg = <0x0 0xfe138180 0x0 0x20>; 505 }; 506 507 qos_isp: qos@fe148000 { 508 compatible = "syscon"; 509 reg = <0x0 0xfe148000 0x0 0x20>; 510 }; 511 512 qos_vicap0: qos@fe148080 { 513 compatible = "syscon"; 514 reg = <0x0 0xfe148080 0x0 0x20>; 515 }; 516 517 qos_vicap1: qos@fe148100 { 518 compatible = "syscon"; 519 reg = <0x0 0xfe148100 0x0 0x20>; 520 }; 521 522 qos_vpu: qos@fe150000 { 523 compatible = "syscon"; 524 reg = <0x0 0xfe150000 0x0 0x20>; 525 }; 526 527 qos_ebc: qos@fe158000 { 528 compatible = "syscon"; 529 reg = <0x0 0xfe158000 0x0 0x20>; 530 }; 531 532 qos_iep: qos@fe158100 { 533 compatible = "syscon"; 534 reg = <0x0 0xfe158100 0x0 0x20>; 535 }; 536 537 qos_jpeg_dec: qos@fe158180 { 538 compatible = "syscon"; 539 reg = <0x0 0xfe158180 0x0 0x20>; 540 }; 541 542 qos_jpeg_enc: qos@fe158200 { 543 compatible = "syscon"; 544 reg = <0x0 0xfe158200 0x0 0x20>; 545 }; 546 547 qos_rga_rd: qos@fe158280 { 548 compatible = "syscon"; 549 reg = <0x0 0xfe158280 0x0 0x20>; 550 }; 551 552 qos_rga_wr: qos@fe158300 { 553 compatible = "syscon"; 554 reg = <0x0 0xfe158300 0x0 0x20>; 555 }; 556 557 qos_npu: qos@fe180000 { 558 compatible = "syscon"; 559 reg = <0x0 0xfe180000 0x0 0x20>; 560 }; 561 562 qos_pcie2x1: qos@fe190000 { 563 compatible = "syscon"; 564 reg = <0x0 0xfe190000 0x0 0x20>; 565 }; 566 567 qos_pcie3x1: qos@fe190080 { 568 compatible = "syscon"; 569 reg = <0x0 0xfe190080 0x0 0x20>; 570 }; 571 572 qos_pcie3x2: qos@fe190100 { 573 compatible = "syscon"; 574 reg = <0x0 0xfe190100 0x0 0x20>; 575 }; 576 577 qos_sata0: qos@fe190200 { 578 compatible = "syscon"; 579 reg = <0x0 0xfe190200 0x0 0x20>; 580 }; 581 582 qos_sata1: qos@fe190280 { 583 compatible = "syscon"; 584 reg = <0x0 0xfe190280 0x0 0x20>; 585 }; 586 587 qos_sata2: qos@fe190300 { 588 compatible = "syscon"; 589 reg = <0x0 0xfe190300 0x0 0x20>; 590 }; 591 592 qos_usb3_0: qos@fe190380 { 593 compatible = "syscon"; 594 reg = <0x0 0xfe190380 0x0 0x20>; 595 }; 596 597 qos_usb3_1: qos@fe190400 { 598 compatible = "syscon"; 599 reg = <0x0 0xfe190400 0x0 0x20>; 600 }; 601 602 qos_rkvdec: qos@fe198000 { 603 compatible = "syscon"; 604 reg = <0x0 0xfe198000 0x0 0x20>; 605 }; 606 607 qos_hdcp: qos@fe1a8000 { 608 compatible = "syscon"; 609 reg = <0x0 0xfe1a8000 0x0 0x20>; 610 }; 611 612 qos_vop_m0: qos@fe1a8080 { 613 compatible = "syscon"; 614 reg = <0x0 0xfe1a8080 0x0 0x20>; 615 }; 616 617 qos_vop_m1: qos@fe1a8100 { 618 compatible = "syscon"; 619 reg = <0x0 0xfe1a8100 0x0 0x20>; 620 }; 621 622 sdmmc2: dwmmc@fe000000 { 623 compatible = "rockchip,rk3568-dw-mshc", 624 "rockchip,rk3288-dw-mshc"; 625 reg = <0x0 0xfe000000 0x0 0x4000>; 626 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 627 max-frequency = <150000000>; 628 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 629 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 630 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 631 fifo-depth = <0x100>; 632 resets = <&cru SRST_SDMMC2>; 633 reset-names = "reset"; 634 status = "disabled"; 635 }; 636 637 sdmmc0: dwmmc@fe2b0000 { 638 compatible = "rockchip,rk3568-dw-mshc", 639 "rockchip,rk3288-dw-mshc"; 640 reg = <0x0 0xfe2b0000 0x0 0x4000>; 641 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 642 max-frequency = <150000000>; 643 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 644 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 645 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 646 fifo-depth = <0x100>; 647 resets = <&cru SRST_SDMMC0>; 648 reset-names = "reset"; 649 status = "disabled"; 650 }; 651 652 sdmmc1: dwmmc@fe2c0000 { 653 compatible = "rockchip,rk3568-dw-mshc", 654 "rockchip,rk3288-dw-mshc"; 655 reg = <0x0 0xfe2c0000 0x0 0x4000>; 656 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 657 max-frequency = <150000000>; 658 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 659 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 660 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 661 fifo-depth = <0x100>; 662 resets = <&cru SRST_SDMMC1>; 663 reset-names = "reset"; 664 status = "disabled"; 665 }; 666 667 sdhci: sdhci@fe310000 { 668 compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci"; 669 reg = <0x0 0xfe310000 0x0 0x10000>; 670 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 671 assigned-clocks = <&cru CCLK_EMMC>, <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 672 assigned-clock-rates = <200000000>, <200000000>, <24000000>; 673 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 674 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 675 <&cru TCLK_EMMC>; 676 clock-names = "core", "bus", "axi", "block", "timer"; 677 status = "disabled"; 678 }; 679 680 nandc0: nandc@fe330000 { 681 compatible = "rockchip,rk-nandc"; 682 reg = <0x0 0xfe330000 0x0 0x4000>; 683 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 684 nandc_id = <0>; 685 clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>; 686 clock-names = "clk_nandc", "hclk_nandc"; 687 status = "disabled"; 688 }; 689 690 i2s0_8ch: i2s@fe400000 { 691 compatible = "rockchip,rk3568-i2s-tdm"; 692 reg = <0x0 0xfe400000 0x0 0x1000>; 693 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 695 clock-names = "mclk_tx", "mclk_rx", "hclk"; 696 dmas = <&dmac1 0>; 697 dma-names = "tx"; 698 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 699 reset-names = "tx-m", "rx-m"; 700 rockchip,cru = <&cru>; 701 rockchip,grf = <&grf>; 702 rockchip,playback-only; 703 status = "disabled"; 704 }; 705 706 i2s1_8ch: i2s@fe410000 { 707 compatible = "rockchip,rk3568-i2s-tdm"; 708 reg = <0x0 0xfe410000 0x0 0x1000>; 709 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 711 clock-names = "mclk_tx", "mclk_rx", "hclk"; 712 dmas = <&dmac1 2>, <&dmac1 3>; 713 dma-names = "tx", "rx"; 714 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 715 reset-names = "tx-m", "rx-m"; 716 rockchip,cru = <&cru>; 717 rockchip,grf = <&grf>; 718 pinctrl-names = "default"; 719 pinctrl-0 = <&i2s1sclktxm0 720 &i2s1sclkrxm0 721 &i2s1lrcktxm0 722 &i2s1lrckrxm0 723 &i2s1sdi0m0 724 &i2s1sdi1m0 725 &i2s1sdi2m0 726 &i2s1sdi3m0 727 &i2s1sdo0m0 728 &i2s1sdo1m0 729 &i2s1sdo2m0 730 &i2s1sdo3m0>; 731 status = "disabled"; 732 }; 733 734 i2s2_2ch: i2s@fe420000 { 735 compatible = "rockchip,rk3568-i2s-tdm"; 736 reg = <0x0 0xfe420000 0x0 0x1000>; 737 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 739 clock-names = "mclk_tx", "mclk_rx", "hclk"; 740 dmas = <&dmac1 4>, <&dmac1 5>; 741 dma-names = "tx", "rx"; 742 rockchip,cru = <&cru>; 743 rockchip,grf = <&grf>; 744 rockchip,clk-trcm = <1>; 745 pinctrl-names = "default"; 746 pinctrl-0 = <&i2s2sclktxm0 747 &i2s2lrcktxm0 748 &i2s2sdim0 749 &i2s2sdom0>; 750 status = "disabled"; 751 }; 752 753 i2s3_2ch: i2s@fe430000 { 754 compatible = "rockchip,rk3568-i2s-tdm"; 755 reg = <0x0 0xfe430000 0x0 0x1000>; 756 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>; 758 clock-names = "mclk_tx", "mclk_rx", "hclk"; 759 dmas = <&dmac1 6>, <&dmac1 7>; 760 dma-names = "tx", "rx"; 761 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 762 reset-names = "tx-m", "rx-m"; 763 rockchip,cru = <&cru>; 764 rockchip,grf = <&grf>; 765 pinctrl-names = "default"; 766 pinctrl-0 = <&i2s3sclkm0 767 &i2s3lrckm0 768 &i2s3sdim0 769 &i2s3sdom0>; 770 status = "disabled"; 771 }; 772 773 pdm: pdm@fe440000 { 774 compatible = "rockchip,rk3568-pdm", "rockchip,pdm"; 775 reg = <0x0 0xfe440000 0x0 0x1000>; 776 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 777 clock-names = "pdm_clk", "pdm_hclk"; 778 dmas = <&dmac1 9>; 779 dma-names = "rx"; 780 status = "disabled"; 781 }; 782 783 spdif_8ch: spdif@fe460000 { 784 compatible = "rockchip,rk3588-spdif"; 785 reg = <0x0 0xfe460000 0x0 0x1000>; 786 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 787 dmas = <&dmac1 1>; 788 dma-names = "tx"; 789 clock-names = "mclk", "hclk"; 790 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 791 pinctrl-names = "default"; 792 pinctrl-0 = <&spdifm0_pins>; 793 status = "disabled"; 794 }; 795 796 audpwm: audpwm@fe470000 { 797 compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1"; 798 reg = <0x0 0xfe470000 0x0 0x1000>; 799 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>; 800 clock-names = "clk", "hclk"; 801 dmas = <&dmac1 8>; 802 dma-names = "tx"; 803 rockchip,sample-width-bits = <11>; 804 rockchip,interpolat-points = <1>; 805 status = "disabled"; 806 }; 807 808 dig_acodec: codec-digital@fe478000 { 809 compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1"; 810 reg = <0x0 0xfe478000 0x0 0x1000>; 811 clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, <&cru HCLK_ACDCDIG>; 812 clock-names = "adc", "dac", "pclk"; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&acodec_pins>; 815 resets = <&cru SRST_ACDCDIG>; 816 reset-names = "reset" ; 817 rockchip,grf = <&grf>; 818 status = "disabled"; 819 }; 820 821 dmac0: dmac@fe530000 { 822 compatible = "arm,pl330", "arm,primecell"; 823 reg = <0x0 0xfe530000 0x0 0x4000>; 824 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&cru ACLK_DMAC0>; 827 clock-names = "apb_pclk"; 828 #dma-cells = <1>; 829 arm,pl330-periph-burst; 830 }; 831 832 dmac1: dmac@fe550000 { 833 compatible = "arm,pl330", "arm,primecell"; 834 reg = <0x0 0xfe550000 0x0 0x4000>; 835 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&cru ACLK_DMAC1>; 838 clock-names = "apb_pclk"; 839 #dma-cells = <1>; 840 arm,pl330-periph-burst; 841 }; 842 843 can0: can@fe570000 { 844 compatible = "rockchip,canfd-1.0"; 845 reg = <0x0 0xfe570000 0x0 0x1000>; 846 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 848 clock-names = "baudclk", "apb_pclk"; 849 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 850 reset-names = "can", "can-apb"; 851 tx-fifo-depth = <1>; 852 rx-fifo-depth = <6>; 853 status = "disabled"; 854 }; 855 856 can1: can@fe580000 { 857 compatible = "rockchip,canfd-1.0"; 858 reg = <0x0 0xfe580000 0x0 0x1000>; 859 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 861 clock-names = "baudclk", "apb_pclk"; 862 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 863 reset-names = "can", "can-apb"; 864 tx-fifo-depth = <1>; 865 rx-fifo-depth = <6>; 866 status = "disabled"; 867 }; 868 869 can2: can@fe590000 { 870 compatible = "rockchip,canfd-1.0"; 871 reg = <0x0 0xfe590000 0x0 0x1000>; 872 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 874 clock-names = "baudclk", "apb_pclk"; 875 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; 876 reset-names = "can", "can-apb"; 877 tx-fifo-depth = <1>; 878 rx-fifo-depth = <6>; 879 status = "disabled"; 880 }; 881 882 i2c1: i2c@fe5a0000 { 883 compatible = "rockchip,rk3399-i2c"; 884 reg = <0x0 0xfe5a0000 0x0 0x1000>; 885 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 886 clock-names = "i2c", "pclk"; 887 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 888 pinctrl-names = "default"; 889 pinctrl-0 = <&i2c1_xfer>; 890 #address-cells = <1>; 891 #size-cells = <0>; 892 status = "disabled"; 893 }; 894 895 i2c2: i2c@fe5b0000 { 896 compatible = "rockchip,rk3399-i2c"; 897 reg = <0x0 0xfe5b0000 0x0 0x1000>; 898 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 899 clock-names = "i2c", "pclk"; 900 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 901 pinctrl-names = "default"; 902 pinctrl-0 = <&i2c2m0_xfer>; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 status = "disabled"; 906 }; 907 908 i2c3: i2c@fe5c0000 { 909 compatible = "rockchip,rk3399-i2c"; 910 reg = <0x0 0xfe5c0000 0x0 0x1000>; 911 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 912 clock-names = "i2c", "pclk"; 913 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 914 pinctrl-names = "default"; 915 pinctrl-0 = <&i2c3m0_xfer>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 status = "disabled"; 919 }; 920 921 i2c4: i2c@fe5d0000 { 922 compatible = "rockchip,rk3399-i2c"; 923 reg = <0x0 0xfe5d0000 0x0 0x1000>; 924 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 925 clock-names = "i2c", "pclk"; 926 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 927 pinctrl-names = "default"; 928 pinctrl-0 = <&i2c4m0_xfer>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 status = "disabled"; 932 }; 933 934 i2c5: i2c@fe5e0000 { 935 compatible = "rockchip,rk3399-i2c"; 936 reg = <0x0 0xfe5e0000 0x0 0x1000>; 937 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 938 clock-names = "i2c", "pclk"; 939 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&i2c5m0_xfer>; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 status = "disabled"; 945 }; 946 947 wdt: watchdog@fe600000 { 948 compatible = "snps,dw-wdt"; 949 reg = <0x0 0xfe600000 0x0 0x100>; 950 clocks = <&cru PCLK_WDT_NS>; 951 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 952 status = "okay"; 953 }; 954 955 spi0: spi@fe610000 { 956 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 957 reg = <0x0 0xfe610000 0x0 0x1000>; 958 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 962 clock-names = "spiclk", "apb_pclk"; 963 dmas = <&dmac0 20>, <&dmac0 21>; 964 pinctrl-names = "default"; 965 pinctrl-0 = <&spi0clkm0 &spi0cs0m0 &spi0cs1m0 &spi0misom0 &spi0mosim0>; 966 status = "disabled"; 967 }; 968 969 spi1: spi@fe620000 { 970 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 971 reg = <0x0 0xfe620000 0x0 0x1000>; 972 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 976 clock-names = "spiclk", "apb_pclk"; 977 dmas = <&dmac0 22>, <&dmac0 23>; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&spi1clkm0 &spi1cs0m0 &spi1cs1m0 &spi1misom0 &spi1mosim0>; 980 status = "disabled"; 981 }; 982 983 spi2: spi@fe630000 { 984 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 985 reg = <0x0 0xfe630000 0x0 0x1000>; 986 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 990 clock-names = "spiclk", "apb_pclk"; 991 dmas = <&dmac0 24>, <&dmac0 25>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&spi2clkm0 &spi2cs0m0 &spi2cs1m0 &spi2misom0 &spi2mosim0>; 994 status = "disabled"; 995 }; 996 997 spi3: spi@fe640000 { 998 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 999 reg = <0x0 0xfe640000 0x0 0x1000>; 1000 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1004 clock-names = "spiclk", "apb_pclk"; 1005 dmas = <&dmac0 26>, <&dmac0 27>; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&spi3clkm0 &spi3cs0m0 &spi3cs1m0 &spi3misom0 &spi3mosim0>; 1008 status = "disabled"; 1009 }; 1010 1011 uart1: serial@fe650000 { 1012 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1013 reg = <0x0 0xfe650000 0x0 0x100>; 1014 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1016 clock-names = "baudclk", "apb_pclk"; 1017 reg-shift = <2>; 1018 reg-io-width = <4>; 1019 dmas = <&dmac0 2>, <&dmac0 3>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&uart1m0_xfer>; 1022 status = "disabled"; 1023 }; 1024 1025 uart2: serial@fe660000 { 1026 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1027 reg = <0x0 0xfe660000 0x0 0x100>; 1028 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1030 clock-names = "baudclk", "apb_pclk"; 1031 reg-shift = <2>; 1032 reg-io-width = <4>; 1033 dmas = <&dmac0 4>, <&dmac0 5>; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&uart2m0_xfer>; 1036 status = "disabled"; 1037 }; 1038 1039 uart3: serial@fe670000 { 1040 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1041 reg = <0x0 0xfe670000 0x0 0x100>; 1042 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1043 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1044 clock-names = "baudclk", "apb_pclk"; 1045 reg-shift = <2>; 1046 reg-io-width = <4>; 1047 dmas = <&dmac0 6>, <&dmac0 7>; 1048 pinctrl-names = "default"; 1049 pinctrl-0 = <&uart3m0_xfer>; 1050 status = "disabled"; 1051 }; 1052 1053 uart4: serial@fe680000 { 1054 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1055 reg = <0x0 0xfe680000 0x0 0x100>; 1056 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1057 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1058 clock-names = "baudclk", "apb_pclk"; 1059 reg-shift = <2>; 1060 reg-io-width = <4>; 1061 dmas = <&dmac0 8>, <&dmac0 9>; 1062 pinctrl-names = "default"; 1063 pinctrl-0 = <&uart4m0_xfer>; 1064 status = "disabled"; 1065 }; 1066 1067 uart5: serial@fe690000 { 1068 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1069 reg = <0x0 0xfe690000 0x0 0x100>; 1070 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1072 clock-names = "baudclk", "apb_pclk"; 1073 reg-shift = <2>; 1074 reg-io-width = <4>; 1075 dmas = <&dmac0 10>, <&dmac0 11>; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&uart5m0_xfer>; 1078 status = "disabled"; 1079 }; 1080 1081 uart6: serial@fe6a0000 { 1082 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1083 reg = <0x0 0xfe6a0000 0x0 0x100>; 1084 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1086 clock-names = "baudclk", "apb_pclk"; 1087 reg-shift = <2>; 1088 reg-io-width = <4>; 1089 dmas = <&dmac0 12>, <&dmac0 13>; 1090 pinctrl-names = "default"; 1091 pinctrl-0 = <&uart6m0_xfer>; 1092 status = "disabled"; 1093 }; 1094 1095 uart7: serial@fe6b0000 { 1096 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1097 reg = <0x0 0xfe6b0000 0x0 0x100>; 1098 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1100 clock-names = "baudclk", "apb_pclk"; 1101 reg-shift = <2>; 1102 reg-io-width = <4>; 1103 dmas = <&dmac0 14>, <&dmac0 15>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&uart7m0_xfer>; 1106 status = "disabled"; 1107 }; 1108 1109 uart8: serial@fe6c0000 { 1110 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1111 reg = <0x0 0xfe6c0000 0x0 0x100>; 1112 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1114 clock-names = "baudclk", "apb_pclk"; 1115 reg-shift = <2>; 1116 reg-io-width = <4>; 1117 dmas = <&dmac0 16>, <&dmac0 17>; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&uart8m0_xfer>; 1120 status = "disabled"; 1121 }; 1122 1123 uart9: serial@fe6d0000 { 1124 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1125 reg = <0x0 0xfe6d0000 0x0 0x100>; 1126 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1128 clock-names = "baudclk", "apb_pclk"; 1129 reg-shift = <2>; 1130 reg-io-width = <4>; 1131 dmas = <&dmac0 18>, <&dmac0 19>; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&uart9m0_xfer>; 1134 status = "disabled"; 1135 }; 1136 1137 pwm4: pwm@fe6e0000 { 1138 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1139 reg = <0x0 0xfe6e0000 0x0 0x10>; 1140 #pwm-cells = <3>; 1141 pinctrl-names = "active"; 1142 pinctrl-0 = <&pwm4_pins>; 1143 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1144 clock-names = "pwm", "pclk"; 1145 status = "disabled"; 1146 }; 1147 1148 pwm5: pwm@fe6e0010 { 1149 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1150 reg = <0x0 0xfe6e0010 0x0 0x10>; 1151 #pwm-cells = <3>; 1152 pinctrl-names = "active"; 1153 pinctrl-0 = <&pwm5_pins>; 1154 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1155 clock-names = "pwm", "pclk"; 1156 status = "disabled"; 1157 }; 1158 1159 pwm6: pwm@fe6e0020 { 1160 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1161 reg = <0x0 0xfe6e0020 0x0 0x10>; 1162 #pwm-cells = <3>; 1163 pinctrl-names = "active"; 1164 pinctrl-0 = <&pwm6_pins>; 1165 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1166 clock-names = "pwm", "pclk"; 1167 status = "disabled"; 1168 }; 1169 1170 pwm7: pwm@fe6e0030 { 1171 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1172 reg = <0x0 0xfe6e0030 0x0 0x10>; 1173 #pwm-cells = <3>; 1174 pinctrl-names = "active"; 1175 pinctrl-0 = <&pwm7_pins>; 1176 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1177 clock-names = "pwm", "pclk"; 1178 status = "disabled"; 1179 }; 1180 1181 pwm8: pwm@fe6f0000 { 1182 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1183 reg = <0x0 0xfe6f0000 0x0 0x10>; 1184 #pwm-cells = <3>; 1185 pinctrl-names = "active"; 1186 pinctrl-0 = <&pwm8m0_pins>; 1187 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1188 clock-names = "pwm", "pclk"; 1189 status = "disabled"; 1190 }; 1191 1192 pwm9: pwm@fe6f0010 { 1193 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1194 reg = <0x0 0xfe6f0010 0x0 0x10>; 1195 #pwm-cells = <3>; 1196 pinctrl-names = "active"; 1197 pinctrl-0 = <&pwm9m0_pins>; 1198 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1199 clock-names = "pwm", "pclk"; 1200 status = "disabled"; 1201 }; 1202 1203 pwm10: pwm@fe6f0020 { 1204 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1205 reg = <0x0 0xfe6f0020 0x0 0x10>; 1206 #pwm-cells = <3>; 1207 pinctrl-names = "active"; 1208 pinctrl-0 = <&pwm10m0_pins>; 1209 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1210 clock-names = "pwm", "pclk"; 1211 status = "disabled"; 1212 }; 1213 1214 pwm11: pwm@fe6f0030 { 1215 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1216 reg = <0x0 0xfe6f0030 0x0 0x10>; 1217 #pwm-cells = <3>; 1218 pinctrl-names = "active"; 1219 pinctrl-0 = <&pwm11m0_pins>; 1220 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1221 clock-names = "pwm", "pclk"; 1222 status = "disabled"; 1223 }; 1224 1225 pwm12: pwm@fe700000 { 1226 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1227 reg = <0x0 0xfe700000 0x0 0x10>; 1228 #pwm-cells = <3>; 1229 pinctrl-names = "active"; 1230 pinctrl-0 = <&pwm12m0_pins>; 1231 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1232 clock-names = "pwm", "pclk"; 1233 status = "disabled"; 1234 }; 1235 1236 pwm13: pwm@fe700010 { 1237 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1238 reg = <0x0 0xfe700010 0x0 0x10>; 1239 #pwm-cells = <3>; 1240 pinctrl-names = "active"; 1241 pinctrl-0 = <&pwm13m0_pins>; 1242 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1243 clock-names = "pwm", "pclk"; 1244 status = "disabled"; 1245 }; 1246 1247 pwm14: pwm@fe700020 { 1248 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1249 reg = <0x0 0xfe700020 0x0 0x10>; 1250 #pwm-cells = <3>; 1251 pinctrl-names = "active"; 1252 pinctrl-0 = <&pwm14m0_pins>; 1253 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1254 clock-names = "pwm", "pclk"; 1255 status = "disabled"; 1256 }; 1257 1258 pwm15: pwm@fe700030 { 1259 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1260 reg = <0x0 0xfe700030 0x0 0x10>; 1261 #pwm-cells = <3>; 1262 pinctrl-names = "active"; 1263 pinctrl-0 = <&pwm15m0_pins>; 1264 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1265 clock-names = "pwm", "pclk"; 1266 status = "disabled"; 1267 }; 1268 1269 saradc: saradc@fe720000 { 1270 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1271 reg = <0x0 0xfe720000 0x0 0x100>; 1272 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1273 #io-channel-cells = <1>; 1274 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1275 clock-names = "saradc", "apb_pclk"; 1276 resets = <&cru SRST_P_SARADC>; 1277 reset-names = "saradc-apb"; 1278 status = "disabled"; 1279 }; 1280 1281 combphy0_us: phy@fe820000 { 1282 compatible = "rockchip,rk3568-naneng-combphy"; 1283 reg = <0x0 0xfe820000 0x0 0x100>; 1284 #phy-cells = <1>; 1285 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>; 1286 clock-names = "refclk", "apbclk"; 1287 resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; 1288 reset-names = "combphy-apb", "combphy"; 1289 rockchip,pipe-grf = <&pipegrf>; 1290 rockchip,pipe-phy-grf = <&pipe_phy_grf0>; 1291 status = "disabled"; 1292 }; 1293 1294 combphy1_usq: phy@fe830000 { 1295 compatible = "rockchip,rk3568-naneng-combphy"; 1296 reg = <0x0 0xfe830000 0x0 0x100>; 1297 #phy-cells = <1>; 1298 clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>; 1299 clock-names = "refclk", "apbclk"; 1300 resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; 1301 reset-names = "combphy-apb", "combphy"; 1302 rockchip,pipe-grf = <&pipegrf>; 1303 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1304 status = "disabled"; 1305 }; 1306 1307 combphy2_psq: phy@fe840000 { 1308 compatible = "rockchip,rk3568-naneng-combphy"; 1309 reg = <0x0 0xfe840000 0x0 0x100>; 1310 #phy-cells = <1>; 1311 clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>; 1312 clock-names = "refclk", "apbclk"; 1313 resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; 1314 reset-names = "combphy-apb", "combphy"; 1315 rockchip,pipe-grf = <&pipegrf>; 1316 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1317 status = "disabled"; 1318 }; 1319 1320 pinctrl: pinctrl { 1321 compatible = "rockchip,rk3568-pinctrl"; 1322 rockchip,grf = <&grf>; 1323 rockchip,pmu = <&pmugrf>; 1324 #address-cells = <2>; 1325 #size-cells = <2>; 1326 ranges; 1327 1328 gpio0: gpio@fdd60000 { 1329 compatible = "rockchip,gpio-bank"; 1330 reg = <0x0 0xfdd60000 0x0 0x100>; 1331 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1333 1334 gpio-controller; 1335 #gpio-cells = <2>; 1336 gpio-ranges = <&pinctrl 0 0 32>; 1337 interrupt-controller; 1338 #interrupt-cells = <2>; 1339 }; 1340 1341 gpio1: gpio@fe740000 { 1342 compatible = "rockchip,gpio-bank"; 1343 reg = <0x0 0xfe740000 0x0 0x100>; 1344 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1345 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1346 1347 gpio-controller; 1348 #gpio-cells = <2>; 1349 gpio-ranges = <&pinctrl 0 32 32>; 1350 interrupt-controller; 1351 #interrupt-cells = <2>; 1352 }; 1353 1354 gpio2: gpio@fe750000 { 1355 compatible = "rockchip,gpio-bank"; 1356 reg = <0x0 0xfe750000 0x0 0x100>; 1357 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1358 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1359 1360 gpio-controller; 1361 #gpio-cells = <2>; 1362 gpio-ranges = <&pinctrl 0 64 32>; 1363 interrupt-controller; 1364 #interrupt-cells = <2>; 1365 }; 1366 1367 gpio3: gpio@fe760000 { 1368 compatible = "rockchip,gpio-bank"; 1369 reg = <0x0 0xfe750000 0x0 0x100>; 1370 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1371 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1372 1373 gpio-controller; 1374 #gpio-cells = <2>; 1375 gpio-ranges = <&pinctrl 0 96 32>; 1376 interrupt-controller; 1377 #interrupt-cells = <2>; 1378 }; 1379 1380 gpio4: gpio@fe770000 { 1381 compatible = "rockchip,gpio-bank"; 1382 reg = <0x0 0xfe770000 0x0 0x100>; 1383 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1385 1386 gpio-controller; 1387 #gpio-cells = <2>; 1388 gpio-ranges = <&pinctrl 0 128 32>; 1389 interrupt-controller; 1390 #interrupt-cells = <2>; 1391 }; 1392 }; 1393}; 1394 1395#include "rk3568-pinctrl.dtsi" 1396