1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/power/rk3568-power.h> 13 14/ { 15 compatible = "rockchip,rk3568"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 dsi0 = &dsi0; 23 dsi1 = &dsi1; 24 ethernet0 = &gmac0; 25 ethernet1 = &gmac1; 26 gpio0 = &gpio0; 27 gpio1 = &gpio1; 28 gpio2 = &gpio2; 29 gpio3 = &gpio3; 30 gpio4 = &gpio4; 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 lvds0 = &lvds0; 38 lvds1 = &lvds1; 39 serial0 = &uart0; 40 serial1 = &uart1; 41 serial2 = &uart2; 42 serial3 = &uart3; 43 serial4 = &uart4; 44 serial5 = &uart5; 45 serial6 = &uart6; 46 serial7 = &uart7; 47 serial8 = &uart8; 48 serial9 = &uart9; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 }; 54 55 cpus { 56 #address-cells = <2>; 57 #size-cells = <0>; 58 59 cpu0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a55"; 62 reg = <0x0 0x0>; 63 enable-method = "psci"; 64 clocks = <&cru ARMCLK>; 65 operating-points-v2 = <&cpu0_opp_table>; 66 }; 67 68 cpu1: cpu@100 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a55"; 71 reg = <0x0 0x100>; 72 enable-method = "psci"; 73 clocks = <&cru ARMCLK>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 }; 76 77 cpu2: cpu@200 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a55"; 80 reg = <0x0 0x200>; 81 enable-method = "psci"; 82 clocks = <&cru ARMCLK>; 83 operating-points-v2 = <&cpu0_opp_table>; 84 }; 85 86 cpu3: cpu@300 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a55"; 89 reg = <0x0 0x300>; 90 enable-method = "psci"; 91 clocks = <&cru ARMCLK>; 92 operating-points-v2 = <&cpu0_opp_table>; 93 }; 94 }; 95 96 cpu0_opp_table: cpu0-opp-table { 97 compatible = "operating-points-v2"; 98 opp-shared; 99 100 opp-408000000 { 101 opp-hz = /bits/ 64 <408000000>; 102 opp-microvolt = <1000000 1000000 1250000>; 103 clock-latency-ns = <40000>; 104 }; 105 opp-600000000 { 106 opp-hz = /bits/ 64 <600000000>; 107 opp-microvolt = <1000000 1000000 1250000>; 108 clock-latency-ns = <40000>; 109 }; 110 opp-816000000 { 111 opp-hz = /bits/ 64 <816000000>; 112 opp-microvolt = <1000000 1000000 1250000>; 113 clock-latency-ns = <40000>; 114 opp-suspend; 115 }; 116 opp-1008000000 { 117 opp-hz = /bits/ 64 <1008000000>; 118 opp-microvolt = <1000000 1000000 1250000>; 119 clock-latency-ns = <40000>; 120 }; 121 opp-1200000000 { 122 opp-hz = /bits/ 64 <1200000000>; 123 opp-microvolt = <1000000 1000000 1250000>; 124 clock-latency-ns = <40000>; 125 }; 126 }; 127 128 arm-pmu { 129 compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3"; 130 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 134 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 135 }; 136 137 display_subsystem: display-subsystem { 138 compatible = "rockchip,display-subsystem"; 139 ports = <&vop_out>; 140 }; 141 142 mpp_srv: mpp-srv { 143 compatible = "rockchip,mpp-service"; 144 rockchip,taskqueue-count = <5>; 145 rockchip,resetgroup-count = <5>; 146 status = "disabled"; 147 }; 148 149 psci { 150 compatible = "arm,psci-1.0"; 151 method = "smc"; 152 }; 153 154 thermal_zones: thermal-zones { 155 soc_thermal: soc-thermal { 156 polling-delay-passive = <20>; /* milliseconds */ 157 polling-delay = <1000>; /* milliseconds */ 158 159 thermal-sensors = <&tsadc 0>; 160 trips { 161 soc_crit: soc-crit { 162 /* millicelsius */ 163 temperature = <115000>; 164 /* millicelsius */ 165 hysteresis = <2000>; 166 type = "critical"; 167 }; 168 }; 169 }; 170 171 gpu_thermal: gpu-thermal { 172 polling-delay-passive = <20>; /* milliseconds */ 173 polling-delay = <1000>; /* milliseconds */ 174 175 thermal-sensors = <&tsadc 1>; 176 }; 177 }; 178 179 timer { 180 compatible = "arm,armv8-timer"; 181 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 182 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 183 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 184 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 185 }; 186 187 gmac0_clkin: external-gmac0-clock { 188 compatible = "fixed-clock"; 189 clock-frequency = <125000000>; 190 clock-output-names = "gmac0_clkin"; 191 #clock-cells = <0>; 192 }; 193 194 gmac1_clkin: external-gmac1-clock { 195 compatible = "fixed-clock"; 196 clock-frequency = <125000000>; 197 clock-output-names = "gmac1_clkin"; 198 #clock-cells = <0>; 199 }; 200 201 xin24m: xin24m { 202 compatible = "fixed-clock"; 203 #clock-cells = <0>; 204 clock-frequency = <24000000>; 205 clock-output-names = "xin24m"; 206 }; 207 208 sata0: sata@fc000000 { 209 compatible = "snps,dwc-ahci"; 210 reg = <0 0xfc000000 0 0x1000>; 211 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, 212 <&cru CLK_SATA0_RXOOB>; 213 clock-names = "sata", "pmalive", "rxoob"; 214 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 215 interrupt-names = "hostc"; 216 phys = <&combphy0_us PHY_TYPE_SATA>; 217 phy-names = "sata-phy"; 218 ports-implemented = <0x1>; 219 power-domains = <&power RK3568_PD_PIPE>; 220 status = "disabled"; 221 }; 222 223 sata1: sata@fc400000 { 224 compatible = "snps,dwc-ahci"; 225 reg = <0 0xfc400000 0 0x1000>; 226 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 227 <&cru CLK_SATA1_RXOOB>; 228 clock-names = "sata", "pmalive", "rxoob"; 229 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 230 interrupt-names = "hostc"; 231 phys = <&combphy1_usq PHY_TYPE_SATA>; 232 phy-names = "sata-phy"; 233 ports-implemented = <0x1>; 234 power-domains = <&power RK3568_PD_PIPE>; 235 status = "disabled"; 236 }; 237 238 sata2: sata@fc800000 { 239 compatible = "snps,dwc-ahci"; 240 reg = <0 0xfc800000 0 0x1000>; 241 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 242 <&cru CLK_SATA2_RXOOB>; 243 clock-names = "sata", "pmalive", "rxoob"; 244 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 245 interrupt-names = "hostc"; 246 phys = <&combphy2_psq PHY_TYPE_SATA>; 247 phy-names = "sata-phy"; 248 ports-implemented = <0x1>; 249 power-domains = <&power RK3568_PD_PIPE>; 250 status = "disabled"; 251 }; 252 253 usbdrd30: usbdrd { 254 compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; 255 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 256 <&cru ACLK_USB3OTG0>; 257 clock-names = "ref_clk", "suspend_clk", 258 "bus_clk"; 259 #address-cells = <2>; 260 #size-cells = <2>; 261 ranges; 262 status = "disabled"; 263 264 usbdrd_dwc3: dwc3@fcc00000 { 265 compatible = "snps,dwc3"; 266 reg = <0x0 0xfcc00000 0x0 0x400000>; 267 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 268 dr_mode = "otg"; 269 phys = <&u2phy0_otg>; 270 phy-names = "usb2-phy"; 271 phy_type = "utmi_wide"; 272 power-domains = <&power RK3568_PD_PIPE>; 273 resets = <&cru SRST_USB3OTG0>; 274 reset-names = "usb3-otg"; 275 snps,dis_enblslpm_quirk; 276 snps,dis-u2-freeclk-exists-quirk; 277 snps,dis_u2_susphy_quirk; 278 snps,dis-del-phy-power-chg-quirk; 279 snps,dis-tx-ipgap-linecheck-quirk; 280 snps,xhci-trb-ent-quirk; 281 status = "disabled"; 282 }; 283 }; 284 285 usbhost30: usbhost { 286 compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; 287 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 288 <&cru ACLK_USB3OTG1>; 289 clock-names = "ref_clk", "suspend_clk", 290 "bus_clk"; 291 #address-cells = <2>; 292 #size-cells = <2>; 293 ranges; 294 status = "disabled"; 295 296 usbhost_dwc3: dwc3@fd000000 { 297 compatible = "snps,dwc3"; 298 reg = <0x0 0xfd000000 0x0 0x400000>; 299 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 300 dr_mode = "host"; 301 phys = <&u2phy0_host>; 302 phy-names = "usb2-phy"; 303 phy_type = "utmi_wide"; 304 power-domains = <&power RK3568_PD_PIPE>; 305 resets = <&cru SRST_USB3OTG1>; 306 reset-names = "usb3-host"; 307 snps,dis_enblslpm_quirk; 308 snps,dis-u2-freeclk-exists-quirk; 309 snps,dis_u2_susphy_quirk; 310 snps,dis-del-phy-power-chg-quirk; 311 snps,dis-tx-ipgap-linecheck-quirk; 312 snps,xhci-trb-ent-quirk; 313 status = "disabled"; 314 }; 315 }; 316 317 gic: interrupt-controller@fd400000 { 318 compatible = "arm,gic-v3"; 319 #interrupt-cells = <3>; 320 #address-cells = <2>; 321 #size-cells = <2>; 322 ranges; 323 interrupt-controller; 324 325 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 326 <0x0 0xfd460000 0 0xc0000>; /* GICR */ 327 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 328 its: interrupt-controller@fd440000 { 329 compatible = "arm,gic-v3-its"; 330 msi-controller; 331 reg = <0x0 0xfd440000 0x0 0x20000>; 332 status = "disabled"; 333 }; 334 }; 335 336 usb_host0_ehci: usb@fd800000 { 337 compatible = "generic-ehci"; 338 reg = <0x0 0xfd800000 0x0 0x40000>; 339 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 341 <&cru PCLK_USB>, <&usb2phy1>; 342 clock-names = "usbhost", "arbiter", "pclk", "utmi"; 343 phys = <&u2phy1_otg>; 344 phy-names = "usb2-phy"; 345 status = "disabled"; 346 }; 347 348 usb_host0_ohci: usb@fd840000 { 349 compatible = "generic-ohci"; 350 reg = <0x0 0xfd840000 0x0 0x40000>; 351 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 353 <&cru PCLK_USB>, <&usb2phy1>; 354 clock-names = "usbhost", "arbiter", "pclk", "utmi"; 355 phys = <&u2phy1_otg>; 356 phy-names = "usb2-phy"; 357 status = "disabled"; 358 }; 359 360 usb_host1_ehci: usb@fd880000 { 361 compatible = "generic-ehci"; 362 reg = <0x0 0xfd880000 0x0 0x40000>; 363 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 365 <&cru PCLK_USB>, <&usb2phy1>; 366 clock-names = "usbhost", "arbiter", "pclk", "utmi"; 367 phys = <&u2phy1_host>; 368 phy-names = "usb2-phy"; 369 status = "disabled"; 370 }; 371 372 usb_host1_ohci: usb@fd8c0000 { 373 compatible = "generic-ohci"; 374 reg = <0x0 0xfd8c0000 0x0 0x40000>; 375 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 377 <&cru PCLK_USB>, <&usb2phy1>; 378 clock-names = "usbhost", "arbiter", "pclk", "utmi"; 379 phys = <&u2phy1_host>; 380 phy-names = "usb2-phy"; 381 status = "disabled"; 382 }; 383 384 pmugrf: syscon@fdc20000 { 385 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 386 reg = <0x0 0xfdc20000 0x0 0x10000>; 387 388 pmu_io_domains: io-domains { 389 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 390 status = "disabled"; 391 }; 392 393 reboot_mode: reboot-mode { 394 compatible = "syscon-reboot-mode"; 395 offset = <0x200>; 396 mode-bootloader = <BOOT_BL_DOWNLOAD>; 397 mode-charge = <BOOT_CHARGING>; 398 mode-fastboot = <BOOT_FASTBOOT>; 399 mode-loader = <BOOT_BL_DOWNLOAD>; 400 mode-normal = <BOOT_NORMAL>; 401 mode-recovery = <BOOT_RECOVERY>; 402 mode-ums = <BOOT_UMS>; 403 mode-panic = <BOOT_PANIC>; 404 mode-watchdog = <BOOT_WATCHDOG>; 405 }; 406 }; 407 408 pipegrf: syscon@fdc50000 { 409 compatible = "rockchip,rk3568-pipegrf", "syscon"; 410 reg = <0x0 0xfdc50000 0x0 0x1000>; 411 }; 412 413 grf: syscon@fdc60000 { 414 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 415 reg = <0x0 0xfdc60000 0x0 0x10000>; 416 417 io_domains: io-domains { 418 compatible = "rockchip,rk3568-io-voltage-domain"; 419 status = "disabled"; 420 }; 421 422 lvds0: lvds0 { 423 compatible = "rockchip,rk3568-lvds"; 424 phys = <&video_phy0>; 425 phy-names = "phy"; 426 status = "disabled"; 427 428 ports { 429 #address-cells = <1>; 430 #size-cells = <0>; 431 432 port@0 { 433 reg = <0>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 437 lvds0_in_vp1: endpoint@0 { 438 reg = <0>; 439 remote-endpoint = <&vp1_out_lvds0>; 440 }; 441 442 lvds0_in_vp2: endpoint@1 { 443 reg = <1>; 444 remote-endpoint = <&vp2_out_lvds0>; 445 }; 446 }; 447 }; 448 }; 449 450 lvds1: lvds1 { 451 compatible = "rockchip,rk3568-lvds"; 452 phys = <&video_phy1>; 453 phy-names = "phy"; 454 status = "disabled"; 455 456 ports { 457 #address-cells = <1>; 458 #size-cells = <0>; 459 460 port@0 { 461 reg = <0>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 465 lvds1_in_vp1: endpoint@0 { 466 reg = <0>; 467 remote-endpoint = <&vp1_out_lvds1>; 468 }; 469 470 lvds1_in_vp2: endpoint@1 { 471 reg = <1>; 472 remote-endpoint = <&vp2_out_lvds1>; 473 }; 474 }; 475 }; 476 }; 477 478 rgb: rgb { 479 compatible = "rockchip,rk3568-rgb"; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&lcdc_ctl>; 482 status = "disabled"; 483 484 ports { 485 #address-cells = <1>; 486 #size-cells = <0>; 487 488 port@0 { 489 reg = <0>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 493 rgb_in_vp2: endpoint@0 { 494 reg = <0>; 495 remote-endpoint = <&vp2_out_rgb>; 496 }; 497 }; 498 499 }; 500 }; 501 502 }; 503 504 pipe_phy_grf0: syscon@fdc70000 { 505 compatible = "rockchip,pipe-phy-grf", "syscon"; 506 reg = <0x0 0xfdc70000 0x0 0x1000>; 507 }; 508 509 pipe_phy_grf1: syscon@fdc80000 { 510 compatible = "rockchip,pipe-phy-grf", "syscon"; 511 reg = <0x0 0xfdc80000 0x0 0x1000>; 512 }; 513 514 pipe_phy_grf2: syscon@fdc90000 { 515 compatible = "rockchip,pipe-phy-grf", "syscon"; 516 reg = <0x0 0xfdc90000 0x0 0x1000>; 517 }; 518 519 usb2phy0_grf: syscon@fdca0000 { 520 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 521 reg = <0x0 0xfdca0000 0x0 0x8000>; 522 }; 523 524 usb2phy1_grf: syscon@fdca8000 { 525 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 526 reg = <0x0 0xfdca8000 0x0 0x8000>; 527 }; 528 529 edp_phy: edp-phy@fdcb0000 { 530 compatible = "rockchip,rk3568-edp-phy"; 531 reg = <0x0 0xfdcb0000 0x0 0x8000>; 532 clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDPPHY_GRF>; 533 clock-names = "refclk", "pclk"; 534 resets = <&cru SRST_P_EDPPHY_GRF>; 535 reset-names = "apb"; 536 #phy-cells = <0>; 537 status = "disabled"; 538 }; 539 540 pcie30_phy_grf: syscon@fdcb8000 { 541 compatible = "rockchip,pcie30-phy-grf", "syscon"; 542 reg = <0x0 0xfdcb8000 0x0 0x10000>; 543 }; 544 545 pmucru: clock-controller@fdd00000 { 546 compatible = "rockchip,rk3568-pmucru"; 547 reg = <0x0 0xfdd00000 0x0 0x1000>; 548 rockchip,grf = <&grf>; 549 #clock-cells = <1>; 550 #reset-cells = <1>; 551 }; 552 553 cru: clock-controller@fdd20000 { 554 compatible = "rockchip,rk3568-cru"; 555 reg = <0x0 0xfdd20000 0x0 0x1000>; 556 rockchip,grf = <&grf>; 557 #clock-cells = <1>; 558 #reset-cells = <1>; 559 560 assigned-clocks = 561 <&pmucru CLK_RTC_32K>, <&pmucru PLL_PPLL>, 562 <&pmucru PCLK_PMU>, <&cru PLL_CPLL>, 563 <&cru PLL_GPLL>, <&cru ARMCLK>, 564 <&cru ACLK_BUS>, <&cru PCLK_BUS>, 565 <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, 566 <&cru HCLK_TOP>, <&cru PCLK_TOP>, 567 <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>, 568 <&cru PLL_NPLL>; 569 assigned-clock-rates = 570 <32768>, <200000000>, 571 <100000000>, <1000000000>, 572 <1188000000>, <600000000>, 573 <150000000>, <100000000>, 574 <300000000>, <200000000>, 575 <150000000>, <100000000>, 576 <300000000>, <150000000>, 577 <1200000000>; 578 assigned-clock-parents = 579 <&pmucru CLK_RTC32K_FRAC>; 580 }; 581 582 i2c0: i2c@fdd40000 { 583 compatible = "rockchip,rk3399-i2c"; 584 reg = <0x0 0xfdd40000 0x0 0x1000>; 585 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 586 clock-names = "i2c", "pclk"; 587 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&i2c0_xfer>; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 status = "disabled"; 593 }; 594 595 uart0: serial@fdd50000 { 596 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 597 reg = <0x0 0xfdd50000 0x0 0x100>; 598 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 600 clock-names = "baudclk", "apb_pclk"; 601 reg-shift = <2>; 602 reg-io-width = <4>; 603 dmas = <&dmac0 0>, <&dmac0 1>; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&uart0_xfer>; 606 status = "disabled"; 607 }; 608 609 pwm0: pwm@fdd70000 { 610 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 611 reg = <0x0 0xfdd70000 0x0 0x10>; 612 #pwm-cells = <3>; 613 pinctrl-names = "active"; 614 pinctrl-0 = <&pwm0m0_pins>; 615 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 616 clock-names = "pwm", "pclk"; 617 status = "disabled"; 618 }; 619 620 pwm1: pwm@fdd70010 { 621 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 622 reg = <0x0 0xfdd70010 0x0 0x10>; 623 #pwm-cells = <3>; 624 pinctrl-names = "active"; 625 pinctrl-0 = <&pwm1m0_pins>; 626 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 627 clock-names = "pwm", "pclk"; 628 status = "disabled"; 629 }; 630 631 pwm2: pwm@fdd70020 { 632 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 633 reg = <0x0 0xfdd70020 0x0 0x10>; 634 #pwm-cells = <3>; 635 pinctrl-names = "active"; 636 pinctrl-0 = <&pwm2m0_pins>; 637 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 638 clock-names = "pwm", "pclk"; 639 status = "disabled"; 640 }; 641 642 pwm3: pwm@fdd70030 { 643 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 644 reg = <0x0 0xfdd70030 0x0 0x10>; 645 #pwm-cells = <3>; 646 pinctrl-names = "active"; 647 pinctrl-0 = <&pwm3_pins>; 648 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 649 clock-names = "pwm", "pclk"; 650 status = "disabled"; 651 }; 652 653 pmu: power-management@fdd90000 { 654 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 655 reg = <0x0 0xfdd90000 0x0 0x1000>; 656 657 power: power-controller { 658 compatible = "rockchip,rk3568-power-controller"; 659 #power-domain-cells = <1>; 660 #address-cells = <1>; 661 #size-cells = <0>; 662 status = "okay"; 663 664 /* These power domains are grouped by VD_NPU */ 665 pd_npu@RK3568_PD_NPU { 666 reg = <RK3568_PD_NPU>; 667 clocks = <&cru ACLK_NPU_PRE>, 668 <&cru HCLK_NPU_PRE>, 669 <&cru PCLK_NPU_PRE>; 670 pm_qos = <&qos_npu>; 671 }; 672 /* These power domains are grouped by VD_GPU */ 673 pd_gpu@RK3568_PD_GPU { 674 reg = <RK3568_PD_GPU>; 675 clocks = <&cru ACLK_GPU_PRE>, 676 <&cru PCLK_GPU_PRE>; 677 pm_qos = <&qos_gpu>; 678 }; 679 /* These power domains are grouped by VD_LOGIC */ 680 pd_vi@RK3568_PD_VI { 681 reg = <RK3568_PD_VI>; 682 clocks = <&cru HCLK_VI>, 683 <&cru PCLK_VI>; 684 pm_qos = <&qos_isp>, 685 <&qos_vicap0>, 686 <&qos_vicap1>; 687 }; 688 pd_vo@RK3568_PD_VO { 689 reg = <RK3568_PD_VO>; 690 clocks = <&cru HCLK_VO>, 691 <&cru PCLK_VO>, 692 <&cru ACLK_VOP_PRE>; 693 pm_qos = <&qos_hdcp>, 694 <&qos_vop_m0>, 695 <&qos_vop_m1>; 696 }; 697 pd_rga@RK3568_PD_RGA { 698 reg = <RK3568_PD_RGA>; 699 clocks = <&cru HCLK_RGA_PRE>, 700 <&cru PCLK_RGA_PRE>; 701 pm_qos = <&qos_ebc>, 702 <&qos_iep>, 703 <&qos_jpeg_dec>, 704 <&qos_jpeg_enc>, 705 <&qos_rga_rd>, 706 <&qos_rga_wr>; 707 }; 708 pd_vpu@RK3568_PD_VPU { 709 reg = <RK3568_PD_VPU>; 710 clocks = <&cru HCLK_VPU_PRE>; 711 pm_qos = <&qos_vpu>; 712 }; 713 pd_rkvdec@RK3568_PD_RKVDEC { 714 clocks = <&cru HCLK_RKVDEC_PRE>; 715 reg = <RK3568_PD_RKVDEC>; 716 pm_qos = <&qos_rkvdec>; 717 }; 718 pd_rkvenc@RK3568_PD_RKVENC { 719 reg = <RK3568_PD_RKVENC>; 720 clocks = <&cru HCLK_RKVENC_PRE>; 721 pm_qos = <&qos_rkvenc_rd_m0>, 722 <&qos_rkvenc_rd_m1>, 723 <&qos_rkvenc_wr_m0>; 724 }; 725 pd_pipe@RK3568_PD_PIPE { 726 reg = <RK3568_PD_PIPE>; 727 clocks = <&cru PCLK_PIPE>; 728 pm_qos = <&qos_pcie2x1>, 729 <&qos_pcie3x1>, 730 <&qos_pcie3x2>, 731 <&qos_sata0>, 732 <&qos_sata1>, 733 <&qos_sata2>, 734 <&qos_usb3_0>, 735 <&qos_usb3_1>; 736 }; 737 }; 738 }; 739 740 pvtm@fde00000 { 741 compatible = "rockchip,rk3568-core-pvtm"; 742 reg = <0x0 0xfde00000 0x0 0x100>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 pvtm@0 { 746 reg = <0>; 747 clocks = <&cru CLK_CORE_PVTM>, <&cru PCLK_CORE_PVTM>; 748 clock-names = "clk", "pclk"; 749 resets = <&cru SRST_CORE_PVTM>, <&cru SRST_P_CORE_PVTM>; 750 reset-names = "rts", "rst-p"; 751 thermal-zone = "soc-thermal"; 752 }; 753 }; 754 755 gpu: gpu@fde60000 { 756 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 757 reg = <0x0 0xfde60000 0x0 0x4000>; 758 759 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 762 interrupt-names = "GPU", "MMU", "JOB"; 763 764 upthreshold = <40>; 765 downdifferential = <10>; 766 767 clocks = <&cru CLK_GPU>; 768 clock-names = "clk_mali"; 769 power-domains = <&power RK3568_PD_GPU>; 770 #cooling-cells = <2>; 771 operating-points-v2 = <&gpu_opp_table>; 772 773 status = "disabled"; 774 power_model { 775 compatible = "arm,mali-simple-power-model"; 776 static-coefficient = <411000>; 777 dynamic-coefficient = <733>; 778 ts = <32000 4700 (-80) 2>; 779 thermal-zone = "gpu-thermal"; 780 }; 781 }; 782 783 gpu_opp_table: opp-table2 { 784 compatible = "operating-points-v2"; 785 786 opp-200000000 { 787 opp-hz = /bits/ 64 <200000000>; 788 opp-microvolt = <1000000>; 789 }; 790 opp-300000000 { 791 opp-hz = /bits/ 64 <300000000>; 792 opp-microvolt = <1000000>; 793 }; 794 opp-400000000 { 795 opp-hz = /bits/ 64 <400000000>; 796 opp-microvolt = <1000000>; 797 }; 798 opp-600000000 { 799 opp-hz = /bits/ 64 <600000000>; 800 opp-microvolt = <1000000>; 801 }; 802 }; 803 804 pvtm@fde80000 { 805 compatible = "rockchip,rk3568-gpu-pvtm"; 806 reg = <0x0 0xfde80000 0x0 0x100>; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 pvtm@1 { 810 reg = <1>; 811 clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>; 812 clock-names = "clk", "pclk"; 813 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; 814 reset-names = "rts", "rst-p"; 815 thermal-zone = "gpu-thermal"; 816 }; 817 }; 818 819 pvtm@fde90000 { 820 compatible = "rockchip,rk3568-npu-pvtm"; 821 reg = <0x0 0xfde90000 0x0 0x100>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 pvtm@2 { 825 reg = <2>; 826 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>, 827 <&cru HCLK_NPU_PRE>; 828 clock-names = "clk", "pclk", "hclk"; 829 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; 830 reset-names = "rts", "rst-p"; 831 thermal-zone = "soc-thermal"; 832 }; 833 }; 834 835 vdpu: vdpu@fdea0400 { 836 compatible = "rockchip,vpu-decoder-v2"; 837 reg = <0x0 0xfdea0400 0x0 0x400>; 838 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 839 interrupt-names = "irq_dec"; 840 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 841 clock-names = "aclk_vcodec", "hclk_vcodec"; 842 resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; 843 reset-names = "video_a", "video_h"; 844 iommus = <&vdpu_mmu>; 845 power-domains = <&power RK3568_PD_VPU>; 846 rockchip,srv = <&mpp_srv>; 847 rockchip,taskqueue-node = <0>; 848 rockchip,resetgroup-node = <0>; 849 status = "disabled"; 850 }; 851 852 vdpu_mmu: iommu@fdea0800 { 853 compatible = "rockchip,iommu-v2"; 854 reg = <0x0 0xfdea0800 0x0 0x40>; 855 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 856 interrupt-names = "vdpu_mmu"; 857 clock-names = "aclk", "iface"; 858 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 859 power-domains = <&power RK3568_PD_VPU>; 860 #iommu-cells = <0>; 861 status = "disabled"; 862 }; 863 864 rk_rga: rk_rga@fdeb0000 { 865 compatible = "rockchip,rga2"; 866 reg = <0x0 0xfdeb0000 0x0 0x1000>; 867 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 869 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 870 power-domains = <&power RK3568_PD_RGA>; 871 status = "disabled"; 872 }; 873 874 ebc: ebc@fdec0000 { 875 compatible = "rockchip,rk3568-ebc-tcon"; 876 reg = <0x0 0xfdec0000 0x0 0x5000>; 877 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>; 879 clock-names = "hclk", "dclk"; 880 power-domains = <&power RK3568_PD_RGA>; 881 rockchip,grf = <&grf>; 882 pinctrl-names = "default"; 883 pinctrl-0 = <&ebc_pins>; 884 status = "disabled"; 885 }; 886 887 jpegd: jpegd@fded0000 { 888 compatible = "rockchip,rkv-jpeg-decoder-v1"; 889 reg = <0x0 0xfded0000 0x0 0x400>; 890 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; 892 clock-names = "aclk_vcodec", "hclk_vcodec"; 893 rockchip,normal-rates = <297000000>, <0>; 894 resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>; 895 reset-names = "video_a", "video_h"; 896 iommus = <&jpegd_mmu>; 897 rockchip,srv = <&mpp_srv>; 898 rockchip,taskqueue-node = <1>; 899 rockchip,resetgroup-node = <1>; 900 power-domains = <&power RK3568_PD_RGA>; 901 status = "disabled"; 902 }; 903 904 jpegd_mmu: iommu@fded0480 { 905 compatible = "rockchip,iommu-v2"; 906 reg = <0x0 0xfded0480 0x0 0x40>; 907 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 908 interrupt-names = "jpegd_mmu"; 909 clock-names = "aclk", "iface"; 910 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; 911 power-domains = <&power RK3568_PD_RGA>; 912 #iommu-cells = <0>; 913 status = "disabled"; 914 }; 915 916 vepu: vepu@fdee0000 { 917 compatible = "rockchip,vpu-encoder-v2"; 918 reg = <0x0 0xfdee0000 0x0 0x400>; 919 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 921 clock-names = "aclk_vcodec", "hclk_vcodec"; 922 rockchip,normal-rates = <297000000>, <0>; 923 resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>; 924 reset-names = "video_a", "video_h"; 925 iommus = <&vepu_mmu>; 926 rockchip,srv = <&mpp_srv>; 927 rockchip,taskqueue-node = <2>; 928 rockchip,resetgroup-node = <2>; 929 power-domains = <&power RK3568_PD_RGA>; 930 status = "disabled"; 931 }; 932 933 vepu_mmu: iommu@fdee0800 { 934 compatible = "rockchip,iommu-v2"; 935 reg = <0x0 0xfdee0800 0x0 0x40>; 936 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 937 interrupt-names = "vepu_mmu"; 938 clock-names = "aclk", "iface"; 939 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 940 power-domains = <&power RK3568_PD_RGA>; 941 #iommu-cells = <0>; 942 status = "disabled"; 943 }; 944 945 iep: iep@fdef0000 { 946 compatible = "rockchip,iep-v2"; 947 reg = <0x0 0xfdef0000 0x0 0x500>; 948 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 949 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>; 950 clock-names = "aclk", "hclk", "sclk"; 951 resets = <&cru SRST_A_IEP>, <&cru SRST_H_IEP>, 952 <&cru SRST_IEP_CORE>; 953 reset-names = "rst_a", "rst_h", "rst_s"; 954 power-domains = <&power RK3568_PD_RGA>; 955 rockchip,srv = <&mpp_srv>; 956 rockchip,taskqueue-node = <5>; 957 rockchip,resetgroup-node = <5>; 958 iommus = <&iep_mmu>; 959 status = "disabled"; 960 }; 961 962 iep_mmu: iommu@fdef0800 { 963 compatible = "rockchip,iommu-v2"; 964 reg = <0x0 0xfdef0800 0x0 0x100>; 965 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 966 interrupt-names = "iep_mmu"; 967 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 968 clock-names = "aclk", "iface"; 969 #iommu-cells = <0>; 970 power-domains = <&power RK3568_PD_RGA>; 971 //rockchip,disable-device-link-resume; 972 status = "disabled"; 973 }; 974 975 eink: eink@fdf00000 { 976 compatible = "rockchip,rk3568-eink-tcon"; 977 reg = <0x0 0xfdf00000 0x0 0x74>; 978 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>; 980 clock-names = "pclk", "hclk"; 981 status = "disabled"; 982 }; 983 984 rkvenc: rkvenc@fdf40000 { 985 compatible = "rockchip,rkv-encoder-v1"; 986 reg = <0x0 0xfdf40000 0x0 0x400>; 987 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 988 interrupt-names = "irq_enc"; 989 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, 990 <&cru CLK_RKVENC_CORE>; 991 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 992 rockchip,normal-rates = <297000000>, <0>, <400000000>; 993 rockchip,advanced-rates = <297000000>, <0>, <500000000>; 994 rockchip,default-max-load = <2088960>; 995 resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>, 996 <&cru SRST_RKVENC_CORE>; 997 reset-names = "video_a", "video_h", "video_core"; 998 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>; 999 assigned-clock-rates = <297000000>, <297000000>; 1000 iommus = <&rkvenc_mmu>; 1001 node-name = "rkvenc"; 1002 rockchip,srv = <&mpp_srv>; 1003 rockchip,taskqueue-node = <3>; 1004 rockchip,resetgroup-node = <3>; 1005 power-domains = <&power RK3568_PD_RKVENC>; 1006 status = "disabled"; 1007 }; 1008 1009 rkvenc_mmu: iommu@fdf40f00 { 1010 compatible = "rockchip,iommu-v2"; 1011 reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>; 1012 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1014 interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1"; 1015 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; 1016 clock-names = "aclk", "iface"; 1017 rockchip,disable-mmu-reset; 1018 rockchip,enable-cmd-retry; 1019 #iommu-cells = <0>; 1020 power-domains = <&power RK3568_PD_RKVENC>; 1021 status = "disabled"; 1022 }; 1023 1024 rkvdec: rkvdec@fdf80200 { 1025 compatible = "rockchip,rkv-decoder-v2"; 1026 reg = <0x0 0xfdf80200 0x0 0x400>; 1027 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1028 interrupt-names = "irq_dec"; 1029 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 1030 <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>, 1031 <&cru CLK_RKVDEC_HEVC_CA>; 1032 clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac", 1033 "clk_core", "clk_hevc_cabac"; 1034 rockchip,normal-rates = <297000000>, <0>, <297000000>, 1035 <297000000>, <400000000>; 1036 rockchip,advanced-rates = <400000000>, <0>, <400000000>, 1037 <400000000>, <500000000>; 1038 rockchip,default-max-load = <2088960>; 1039 resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, 1040 <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>, 1041 <&cru SRST_RKVDEC_HEVC_CA>; 1042 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>, 1043 <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>; 1044 assigned-clock-rates = <297000000>, <297000000>, <297000000>, <297000000>; 1045 reset-names = "video_a", "video_h", "video_cabac", 1046 "video_core", "video_hevc_cabac"; 1047 power-domains = <&power RK3568_PD_RKVDEC>; 1048 iommus = <&rkvdec_mmu>; 1049 rockchip,srv = <&mpp_srv>; 1050 rockchip,taskqueue-node = <4>; 1051 rockchip,resetgroup-node = <4>; 1052 status = "disabled"; 1053 }; 1054 1055 rkvdec_mmu: iommu@fdf80800 { 1056 compatible = "rockchip,iommu-v2"; 1057 reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>; 1058 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1059 interrupt-names = "rkvdec_mmu"; 1060 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 1061 clock-names = "aclk", "iface"; 1062 power-domains = <&power RK3568_PD_RKVDEC>; 1063 #iommu-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 mipi_csi2: mipi-csi2@fdfb0000 { 1068 compatible = "rockchip,rk3568-mipi-csi2"; 1069 reg = <0x0 0xfdfb0000 0x0 0x10000>; 1070 reg-names = "csihost_regs"; 1071 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1073 interrupt-names = "csi-intr1", "csi-intr2"; 1074 clocks = <&cru PCLK_CSI2HOST1>, <&cru SRST_P_CSI2HOST1>; 1075 clock-names = "pclk_csi2host", "srst_csihost_p"; 1076 power-domains = <&power RK3568_PD_VI>; 1077 status = "disabled"; 1078 }; 1079 1080 rkcif: rkcif@fdfe0000 { 1081 compatible = "rockchip,rk3568-cif"; 1082 reg = <0x0 0xfdfe0000 0x0 0x8000>; 1083 reg-names = "cif_regs"; 1084 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1085 interrupt-names = "cif-intr"; 1086 1087 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, 1088 <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; 1089 clock-names = "aclk_cif", "hclk_cif", 1090 "dclk_cif", "iclk_cif_g"; 1091 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, 1092 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, 1093 <&cru SRST_I_VICAP>; 1094 reset-names = "rst_cif_a", "rst_cif_h", 1095 "rst_cif_d", "rst_cif_p", 1096 "rst_cif_i"; 1097 assigned-clocks = <&cru DCLK_VICAP>; 1098 assigned-clock-rates = <300000000>; 1099 power-domains = <&power RK3568_PD_VI>; 1100 rockchip,grf = <&grf>; 1101 iommus = <&rkcif_mmu>; 1102 status = "disabled"; 1103 }; 1104 1105 rkcif_mmu: iommu@fdfe0800 { 1106 compatible = "rockchip,iommu"; 1107 reg = <0x0 0xfdfe0800 0x0 0x100>; 1108 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1109 interrupt-names = "cif_mmu"; 1110 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; 1111 clock-names = "aclk", "iface"; 1112 power-domains = <&power RK3568_PD_VI>; 1113 #iommu-cells = <0>; 1114 rockchip,disable-mmu-reset; 1115 status = "disabled"; 1116 }; 1117 1118 rkcif_dvp: rkcif_dvp { 1119 compatible = "rockchip,rkcif-dvp"; 1120 rockchip,hw = <&rkcif>; 1121 iommus = <&rkcif_mmu>; 1122 status = "disabled"; 1123 }; 1124 1125 rkcif_dvp_sditf: rkcif_dvp_sditf { 1126 compatible = "rockchip,rkcif-sditf"; 1127 rockchip,cif = <&rkcif_dvp>; 1128 status = "disabled"; 1129 }; 1130 1131 rkcif_mipi_lvds: rkcif_mipi_lvds { 1132 compatible = "rockchip,rkcif-mipi-lvds"; 1133 rockchip,hw = <&rkcif>; 1134 iommus = <&rkcif_mmu>; 1135 status = "disabled"; 1136 }; 1137 1138 rkcif_mipi_lvds_sditf: rkcif_mipi_lvds_sditf { 1139 compatible = "rockchip,rkcif-sditf"; 1140 rockchip,cif = <&rkcif_mipi_lvds>; 1141 status = "disabled"; 1142 }; 1143 1144 rkisp: rkisp@fdff0000 { 1145 compatible = "rockchip,rk3568-rkisp"; 1146 reg = <0x0 0xfdff0000 0x0 0x10000>; 1147 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1150 interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; 1151 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>; 1152 clock-names = "aclk_isp", "hclk_isp", "clk_isp"; 1153 resets = <&cru SRST_ISP>, <&cru SRST_H_ISP>; 1154 reset-names = "isp", "isp-h"; 1155 rockchip,grf = <&grf>; 1156 power-domains = <&power RK3568_PD_VI>; 1157 iommus = <&rkisp_mmu>; 1158 status = "disabled"; 1159 }; 1160 1161 rkisp_mmu: iommu@fdff1a00 { 1162 compatible = "rockchip,iommu"; 1163 reg = <0x0 0xfdff1a00 0x0 0x100>; 1164 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1165 interrupt-names = "isp_mmu"; 1166 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1167 clock-names = "aclk", "iface"; 1168 power-domains = <&power RK3568_PD_VI>; 1169 #iommu-cells = <0>; 1170 rockchip,disable-mmu-reset; 1171 status = "disabled"; 1172 }; 1173 1174 rkisp_vir0: rkisp-vir0 { 1175 compatible = "rockchip,rkisp-vir"; 1176 rockchip,hw = <&rkisp>; 1177 status = "disabled"; 1178 }; 1179 1180 rkisp_vir1: rkisp-vir1 { 1181 compatible = "rockchip,rkisp-vir"; 1182 rockchip,hw = <&rkisp>; 1183 status = "disabled"; 1184 }; 1185 1186 gmac1: ethernet@fe010000 { 1187 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 1188 reg = <0x0 0xfe010000 0x0 0x10000>; 1189 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1191 interrupt-names = "macirq", "eth_wake_irq"; 1192 rockchip,grf = <&grf>; 1193 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 1194 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 1195 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 1196 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 1197 clock-names = "stmmaceth", "mac_clk_rx", 1198 "mac_clk_tx", "clk_mac_refout", 1199 "aclk_mac", "pclk_mac", 1200 "clk_mac_speed", "ptp_ref"; 1201 resets = <&cru SRST_A_GMAC1>; 1202 reset-names = "stmmaceth"; 1203 1204 snps,mixed-burst; 1205 snps,tso; 1206 1207 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1208 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1209 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1210 status = "disabled"; 1211 1212 mdio1: mdio { 1213 compatible = "snps,dwmac-mdio"; 1214 #address-cells = <0x1>; 1215 #size-cells = <0x0>; 1216 }; 1217 1218 gmac1_stmmac_axi_setup: stmmac-axi-config { 1219 snps,wr_osr_lmt = <4>; 1220 snps,rd_osr_lmt = <8>; 1221 snps,blen = <0 0 0 0 16 8 4>; 1222 }; 1223 1224 gmac1_mtl_rx_setup: rx-queues-config { 1225 snps,rx-queues-to-use = <1>; 1226 queue0 {}; 1227 }; 1228 1229 gmac1_mtl_tx_setup: tx-queues-config { 1230 snps,tx-queues-to-use = <1>; 1231 queue0 {}; 1232 }; 1233 }; 1234 1235 vop: vop@fe040000 { 1236 compatible = "rockchip,rk3568-vop"; 1237 reg = <0x0 0xfe040000 0x0 0x3000>; 1238 reg-names = "regs"; 1239 rockchip,grf = <&grf>; 1240 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1241 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 1242 clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2"; 1243 iommus = <&vop_mmu>; 1244 power-domains = <&power RK3568_PD_VO>; 1245 status = "disabled"; 1246 1247 vop_out: ports { 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 1251 port@0 { 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 reg = <0>; 1255 1256 vp0_out_dsi0: endpoint@0 { 1257 reg = <0>; 1258 remote-endpoint = <&dsi0_in_vp0>; 1259 }; 1260 1261 vp0_out_dsi1: endpoint@1 { 1262 reg = <1>; 1263 remote-endpoint = <&dsi1_in_vp0>; 1264 }; 1265 1266 vp0_out_edp: endpoint@2 { 1267 reg = <2>; 1268 remote-endpoint = <&edp_in_vp0>; 1269 }; 1270 1271 vp0_out_hdmi: endpoint@3 { 1272 reg = <3>; 1273 remote-endpoint = <&hdmi_in_vp0>; 1274 }; 1275 }; 1276 1277 port@1 { 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 reg = <1>; 1281 1282 vp1_out_dsi0: endpoint@0 { 1283 reg = <0>; 1284 remote-endpoint = <&dsi0_in_vp1>; 1285 }; 1286 1287 vp1_out_dsi1: endpoint@1 { 1288 reg = <1>; 1289 remote-endpoint = <&dsi1_in_vp1>; 1290 }; 1291 1292 vp1_out_edp: endpoint@2 { 1293 reg = <2>; 1294 remote-endpoint = <&edp_in_vp1>; 1295 }; 1296 1297 vp1_out_hdmi: endpoint@3 { 1298 reg = <3>; 1299 remote-endpoint = <&hdmi_in_vp1>; 1300 }; 1301 1302 vp1_out_lvds0: endpoint@4 { 1303 reg = <4>; 1304 remote-endpoint = <&lvds0_in_vp1>; 1305 }; 1306 1307 vp1_out_lvds1: endpoint@5 { 1308 reg = <5>; 1309 remote-endpoint = <&lvds1_in_vp1>; 1310 }; 1311 1312 }; 1313 1314 port@2 { 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 1318 reg = <2>; 1319 1320 vp2_out_lvds0: endpoint@0 { 1321 reg = <0>; 1322 remote-endpoint = <&lvds0_in_vp2>; 1323 }; 1324 1325 vp2_out_lvds1: endpoint@1 { 1326 reg = <1>; 1327 remote-endpoint = <&lvds1_in_vp2>; 1328 }; 1329 1330 vp2_out_rgb: endpoint@2 { 1331 reg = <2>; 1332 remote-endpoint = <&rgb_in_vp2>; 1333 }; 1334 }; 1335 }; 1336 }; 1337 1338 vop_mmu: iommu@fe043e00 { 1339 compatible = "rockchip,iommu-v2"; 1340 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; 1341 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1342 interrupt-names = "vop_mmu"; 1343 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1344 clock-names = "aclk", "iface"; 1345 #iommu-cells = <0>; 1346 status = "disabled"; 1347 }; 1348 1349 dsi0: dsi@fe060000 { 1350 compatible = "rockchip,rk3568-mipi-dsi"; 1351 reg = <0x0 0xfe060000 0x0 0x10000>; 1352 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1353 clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&mipi_dphy0>; 1354 clock-names = "pclk", "hclk", "hs_clk"; 1355 resets = <&cru SRST_P_DSITX_0>; 1356 reset-names = "apb"; 1357 phys = <&mipi_dphy0>; 1358 phy-names = "mipi_dphy"; 1359 power-domains = <&power RK3568_PD_VO>; 1360 rockchip,grf = <&grf>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 status = "disabled"; 1364 1365 ports { 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 1369 dsi0_in: port@0 { 1370 reg = <0>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 1374 dsi0_in_vp0: endpoint@0 { 1375 reg = <0>; 1376 remote-endpoint = <&vp0_out_dsi0>; 1377 }; 1378 1379 dsi0_in_vp1: endpoint@1 { 1380 reg = <1>; 1381 remote-endpoint = <&vp1_out_dsi0>; 1382 }; 1383 }; 1384 }; 1385 }; 1386 1387 dsi1: dsi@fe070000 { 1388 compatible = "rockchip,rk3568-mipi-dsi"; 1389 reg = <0x0 0xfe070000 0x0 0x10000>; 1390 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1391 clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&mipi_dphy1>; 1392 clock-names = "pclk", "hclk", "hs_clk"; 1393 resets = <&cru SRST_P_DSITX_1>; 1394 reset-names = "apb"; 1395 phys = <&mipi_dphy1>; 1396 phy-names = "mipi_dphy"; 1397 power-domains = <&power RK3568_PD_VO>; 1398 rockchip,grf = <&grf>; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 status = "disabled"; 1402 1403 ports { 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 1407 dsi1_in: port@0 { 1408 reg = <0>; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 1412 dsi1_in_vp0: endpoint@0 { 1413 reg = <0>; 1414 remote-endpoint = <&vp0_out_dsi1>; 1415 }; 1416 1417 dsi1_in_vp1: endpoint@1 { 1418 reg = <1>; 1419 remote-endpoint = <&vp1_out_dsi1>; 1420 }; 1421 }; 1422 }; 1423 }; 1424 1425 hdmi: hdmi@fe0a0000 { 1426 compatible = "rockchip,rk3568-dw-hdmi"; 1427 reg = <0x0 0xfe0a0000 0x0 0x20000>; 1428 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1429 clocks = <&cru PCLK_HDMI_HOST>, 1430 <&cru CLK_HDMI_SFR>, 1431 <&cru CLK_HDMI_CEC>, 1432 <&pmucru PLL_HPLL>, 1433 <&cru HCLK_VOP>; 1434 clock-names = "iahb", "isfr", "cec", "ref", "hclk"; 1435 power-domains = <&power RK3568_PD_VO>; 1436 reg-io-width = <4>; 1437 rockchip,grf = <&grf>; 1438 #sound-dai-cells = <0>; 1439 pinctrl-names = "default"; 1440 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; 1441 status = "disabled"; 1442 1443 ports { 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 1447 hdmi_in: port { 1448 reg = <0>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 1452 hdmi_in_vp0: endpoint@0 { 1453 reg = <0>; 1454 remote-endpoint = <&vp0_out_hdmi>; 1455 }; 1456 hdmi_in_vp1: endpoint@1 { 1457 reg = <1>; 1458 remote-endpoint = <&vp1_out_hdmi>; 1459 }; 1460 }; 1461 }; 1462 }; 1463 1464 edp: edp@fe0c0000 { 1465 compatible = "rockchip,rk3568-edp"; 1466 reg = <0x0 0xfe0c0000 0x0 0x10000>; 1467 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1468 clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>, 1469 <&cru CLK_EDP_200M>, <&cru HCLK_VO>; 1470 clock-names = "dp", "pclk", "spdif", "hclk"; 1471 resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>; 1472 reset-names = "dp", "apb"; 1473 phys = <&edp_phy>; 1474 phy-names = "dp"; 1475 power-domains = <&power RK3568_PD_VO>; 1476 status = "disabled"; 1477 1478 ports { 1479 #address-cells = <1>; 1480 #size-cells = <0>; 1481 1482 edp_in: port@0 { 1483 reg = <0>; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 1487 edp_in_vp0: endpoint@0 { 1488 reg = <0>; 1489 remote-endpoint = <&vp0_out_edp>; 1490 }; 1491 1492 edp_in_vp1: endpoint@1 { 1493 reg = <1>; 1494 remote-endpoint = <&vp1_out_edp>; 1495 }; 1496 }; 1497 }; 1498 }; 1499 1500 qos_gpu: qos@fe128000 { 1501 compatible = "syscon"; 1502 reg = <0x0 0xfe128000 0x0 0x20>; 1503 }; 1504 1505 qos_rkvenc_rd_m0: qos@fe138080 { 1506 compatible = "syscon"; 1507 reg = <0x0 0xfe138080 0x0 0x20>; 1508 }; 1509 1510 qos_rkvenc_rd_m1: qos@fe138100 { 1511 compatible = "syscon"; 1512 reg = <0x0 0xfe138100 0x0 0x20>; 1513 }; 1514 1515 qos_rkvenc_wr_m0: qos@fe138180 { 1516 compatible = "syscon"; 1517 reg = <0x0 0xfe138180 0x0 0x20>; 1518 }; 1519 1520 qos_isp: qos@fe148000 { 1521 compatible = "syscon"; 1522 reg = <0x0 0xfe148000 0x0 0x20>; 1523 }; 1524 1525 qos_vicap0: qos@fe148080 { 1526 compatible = "syscon"; 1527 reg = <0x0 0xfe148080 0x0 0x20>; 1528 }; 1529 1530 qos_vicap1: qos@fe148100 { 1531 compatible = "syscon"; 1532 reg = <0x0 0xfe148100 0x0 0x20>; 1533 }; 1534 1535 qos_vpu: qos@fe150000 { 1536 compatible = "syscon"; 1537 reg = <0x0 0xfe150000 0x0 0x20>; 1538 }; 1539 1540 qos_ebc: qos@fe158000 { 1541 compatible = "syscon"; 1542 reg = <0x0 0xfe158000 0x0 0x20>; 1543 }; 1544 1545 qos_iep: qos@fe158100 { 1546 compatible = "syscon"; 1547 reg = <0x0 0xfe158100 0x0 0x20>; 1548 }; 1549 1550 qos_jpeg_dec: qos@fe158180 { 1551 compatible = "syscon"; 1552 reg = <0x0 0xfe158180 0x0 0x20>; 1553 }; 1554 1555 qos_jpeg_enc: qos@fe158200 { 1556 compatible = "syscon"; 1557 reg = <0x0 0xfe158200 0x0 0x20>; 1558 }; 1559 1560 qos_rga_rd: qos@fe158280 { 1561 compatible = "syscon"; 1562 reg = <0x0 0xfe158280 0x0 0x20>; 1563 }; 1564 1565 qos_rga_wr: qos@fe158300 { 1566 compatible = "syscon"; 1567 reg = <0x0 0xfe158300 0x0 0x20>; 1568 }; 1569 1570 qos_npu: qos@fe180000 { 1571 compatible = "syscon"; 1572 reg = <0x0 0xfe180000 0x0 0x20>; 1573 }; 1574 1575 qos_pcie2x1: qos@fe190000 { 1576 compatible = "syscon"; 1577 reg = <0x0 0xfe190000 0x0 0x20>; 1578 }; 1579 1580 qos_pcie3x1: qos@fe190080 { 1581 compatible = "syscon"; 1582 reg = <0x0 0xfe190080 0x0 0x20>; 1583 }; 1584 1585 qos_pcie3x2: qos@fe190100 { 1586 compatible = "syscon"; 1587 reg = <0x0 0xfe190100 0x0 0x20>; 1588 }; 1589 1590 qos_sata0: qos@fe190200 { 1591 compatible = "syscon"; 1592 reg = <0x0 0xfe190200 0x0 0x20>; 1593 }; 1594 1595 qos_sata1: qos@fe190280 { 1596 compatible = "syscon"; 1597 reg = <0x0 0xfe190280 0x0 0x20>; 1598 }; 1599 1600 qos_sata2: qos@fe190300 { 1601 compatible = "syscon"; 1602 reg = <0x0 0xfe190300 0x0 0x20>; 1603 }; 1604 1605 qos_usb3_0: qos@fe190380 { 1606 compatible = "syscon"; 1607 reg = <0x0 0xfe190380 0x0 0x20>; 1608 }; 1609 1610 qos_usb3_1: qos@fe190400 { 1611 compatible = "syscon"; 1612 reg = <0x0 0xfe190400 0x0 0x20>; 1613 }; 1614 1615 qos_rkvdec: qos@fe198000 { 1616 compatible = "syscon"; 1617 reg = <0x0 0xfe198000 0x0 0x20>; 1618 }; 1619 1620 qos_hdcp: qos@fe1a8000 { 1621 compatible = "syscon"; 1622 reg = <0x0 0xfe1a8000 0x0 0x20>; 1623 }; 1624 1625 qos_vop_m0: qos@fe1a8080 { 1626 compatible = "syscon"; 1627 reg = <0x0 0xfe1a8080 0x0 0x20>; 1628 }; 1629 1630 qos_vop_m1: qos@fe1a8100 { 1631 compatible = "syscon"; 1632 reg = <0x0 0xfe1a8100 0x0 0x20>; 1633 }; 1634 1635 sdmmc2: dwmmc@fe000000 { 1636 compatible = "rockchip,rk3568-dw-mshc", 1637 "rockchip,rk3288-dw-mshc"; 1638 reg = <0x0 0xfe000000 0x0 0x4000>; 1639 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1640 max-frequency = <150000000>; 1641 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 1642 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 1643 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1644 fifo-depth = <0x100>; 1645 resets = <&cru SRST_SDMMC2>; 1646 reset-names = "reset"; 1647 status = "disabled"; 1648 }; 1649 1650 pcie2x1: pcie@fe260000 { 1651 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; 1652 #address-cells = <3>; 1653 #size-cells = <2>; 1654 bus-range = <0x0 0x1f>; 1655 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 1656 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>; 1657 clock-names = "aclk_mst", "aclk_slv", 1658 "aclk_dbi", "pclk"; 1659 device_type = "pci"; 1660 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1665 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1666 linux,pci-domain = <0>; 1667 num-ib-windows = <6>; 1668 num-ob-windows = <2>; 1669 max-link-speed = <2>; 1670 msi-map = <0x0 &its 0x0 0x1000>; 1671 num-lanes = <1>; 1672 phys = <&combphy2_psq PHY_TYPE_PCIE>; 1673 phy-names = "pcie-phy"; 1674 power-domains = <&power RK3568_PD_PIPE>; 1675 ranges = <0x00000800 0x0 0x00000000 0x3 0x00000000 0x0 0x800000 1676 0x81000000 0x0 0x00800000 0x3 0x00800000 0x0 0x100000 1677 0x83000000 0x0 0x00900000 0x3 0x00900000 0x0 0x3f700000>; 1678 reg = <0x3 0xc0000000 0x0 0x400000>, 1679 <0x0 0xfe260000 0x0 0x10000>; 1680 reg-names = "pcie-dbi", "pcie-apb"; 1681 resets = <&cru SRST_PCIE20_POWERUP>; 1682 reset-names = "pipe"; 1683 status = "disabled"; 1684 }; 1685 1686 pcie3x1: pcie@fe270000 { 1687 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; 1688 #address-cells = <3>; 1689 #size-cells = <2>; 1690 bus-range = <0x0 0x1f>; 1691 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, 1692 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>; 1693 clock-names = "aclk_mst", "aclk_slv", 1694 "aclk_dbi", "pclk"; 1695 device_type = "pci"; 1696 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1701 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1702 linux,pci-domain = <1>; 1703 num-ib-windows = <6>; 1704 num-ob-windows = <2>; 1705 max-link-speed = <3>; 1706 msi-map = <0x0 &its 0x3000 0x1000>; 1707 num-lanes = <1>; 1708 phys = <&pcie30phy>; 1709 phy-names = "pcie-phy"; 1710 power-domains = <&power RK3568_PD_PIPE>; 1711 ranges = <0x00000800 0x0 0x40000000 0x3 0x40000000 0x0 0x800000 1712 0x81000000 0x0 0x40800000 0x3 0x40800000 0x0 0x100000 1713 0x83000000 0x0 0x40900000 0x3 0x40900000 0x0 0x3f700000>; 1714 reg = <0x3 0xc0400000 0x0 0x400000>, 1715 <0x0 0xfe270000 0x0 0x10000>; 1716 reg-names = "pcie-dbi", "pcie-apb"; 1717 resets = <&cru SRST_PCIE30X1_POWERUP>; 1718 reset-names = "pipe"; 1719 /* rockchip,bifurcation; lane1 when using 1+1 */ 1720 status = "disabled"; 1721 }; 1722 1723 pcie3x2: pcie@fe280000 { 1724 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; 1725 #address-cells = <3>; 1726 #size-cells = <2>; 1727 bus-range = <0x0 0x1f>; 1728 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, 1729 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>; 1730 clock-names = "aclk_mst", "aclk_slv", 1731 "aclk_dbi", "pclk"; 1732 device_type = "pci"; 1733 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1738 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1739 linux,pci-domain = <2>; 1740 num-ib-windows = <6>; 1741 num-ob-windows = <2>; 1742 max-link-speed = <3>; 1743 msi-map = <0x0 &its 0x2000 0x1000>; 1744 num-lanes = <2>; 1745 phys = <&pcie30phy>; 1746 phy-names = "pcie-phy"; 1747 power-domains = <&power RK3568_PD_PIPE>; 1748 ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000 1749 0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000 1750 0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>; 1751 reg = <0x3 0xc0800000 0x0 0x400000>, 1752 <0x0 0xfe280000 0x0 0x10000>; 1753 reg-names = "pcie-dbi", "pcie-apb"; 1754 resets = <&cru SRST_PCIE30X2_POWERUP>; 1755 reset-names = "pipe"; 1756 /* rockchip,bifurcation; lane0 when using 1+1 */ 1757 status = "disabled"; 1758 }; 1759 1760 gmac0: ethernet@fe2a0000 { 1761 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 1762 reg = <0x0 0xfe2a0000 0x0 0x10000>; 1763 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1765 interrupt-names = "macirq", "eth_wake_irq"; 1766 rockchip,grf = <&grf>; 1767 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, 1768 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, 1769 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, 1770 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; 1771 clock-names = "stmmaceth", "mac_clk_rx", 1772 "mac_clk_tx", "clk_mac_refout", 1773 "aclk_mac", "pclk_mac", 1774 "clk_mac_speed", "ptp_ref"; 1775 resets = <&cru SRST_A_GMAC0>; 1776 reset-names = "stmmaceth"; 1777 1778 snps,mixed-burst; 1779 snps,tso; 1780 1781 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1782 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1783 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1784 status = "disabled"; 1785 1786 mdio0: mdio { 1787 compatible = "snps,dwmac-mdio"; 1788 #address-cells = <0x1>; 1789 #size-cells = <0x0>; 1790 }; 1791 1792 gmac0_stmmac_axi_setup: stmmac-axi-config { 1793 snps,wr_osr_lmt = <4>; 1794 snps,rd_osr_lmt = <8>; 1795 snps,blen = <0 0 0 0 16 8 4>; 1796 }; 1797 1798 gmac0_mtl_rx_setup: rx-queues-config { 1799 snps,rx-queues-to-use = <1>; 1800 queue0 {}; 1801 }; 1802 1803 gmac0_mtl_tx_setup: tx-queues-config { 1804 snps,tx-queues-to-use = <1>; 1805 queue0 {}; 1806 }; 1807 }; 1808 1809 sdmmc0: dwmmc@fe2b0000 { 1810 compatible = "rockchip,rk3568-dw-mshc", 1811 "rockchip,rk3288-dw-mshc"; 1812 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1813 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1814 max-frequency = <150000000>; 1815 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 1816 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 1817 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1818 fifo-depth = <0x100>; 1819 resets = <&cru SRST_SDMMC0>; 1820 reset-names = "reset"; 1821 pinctrl-names = "default"; 1822 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; 1823 status = "disabled"; 1824 }; 1825 1826 sdmmc1: dwmmc@fe2c0000 { 1827 compatible = "rockchip,rk3568-dw-mshc", 1828 "rockchip,rk3288-dw-mshc"; 1829 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1830 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1831 max-frequency = <150000000>; 1832 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 1833 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1834 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1835 fifo-depth = <0x100>; 1836 resets = <&cru SRST_SDMMC1>; 1837 reset-names = "reset"; 1838 status = "disabled"; 1839 }; 1840 1841 sfc: sfc@fe300000 { 1842 compatible = "rockchip,sfc"; 1843 reg = <0x0 0xfe300000 0x0 0x4000>; 1844 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1845 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1846 clock-names = "clk_sfc", "hclk_sfc"; 1847 assigned-clocks = <&cru SCLK_SFC>; 1848 assigned-clock-rates = <100000000>; 1849 status = "disabled"; 1850 }; 1851 1852 sdhci: sdhci@fe310000 { 1853 compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci"; 1854 reg = <0x0 0xfe310000 0x0 0x10000>; 1855 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1856 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 1857 assigned-clock-rates = <200000000>, <24000000>; 1858 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1859 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1860 <&cru TCLK_EMMC>; 1861 clock-names = "core", "bus", "axi", "block", "timer"; 1862 status = "disabled"; 1863 }; 1864 1865 nandc0: nandc@fe330000 { 1866 compatible = "rockchip,rk-nandc"; 1867 reg = <0x0 0xfe330000 0x0 0x4000>; 1868 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1869 nandc_id = <0>; 1870 clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>; 1871 clock-names = "clk_nandc", "hclk_nandc"; 1872 status = "disabled"; 1873 }; 1874 1875 crypto: crypto@fe380000 { 1876 compatible = "rockchip,rk3568-crypto"; 1877 reg = <0x0 0xfe380000 0x0 0x4000>; 1878 clocks = <&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>; 1879 clock-names = "sclk_crypto", "apkclk_crypto"; 1880 clock-frequency = <150000000>, <300000000>; 1881 status = "disabled"; 1882 }; 1883 1884 secure_otp: secure_otp@fe3a0000 { 1885 compatible = "rockchip,rk3568-secure-otp"; 1886 reg = <0x0 0xfe3a0000 0x0 0x4000>; 1887 secure_conf = <0xfdd18008>; 1888 mask_addr = <0xfe880000>; 1889 cru_rst_addr = <0xfdd20470>; 1890 }; 1891 1892 i2s0_8ch: i2s@fe400000 { 1893 compatible = "rockchip,rk3568-i2s-tdm"; 1894 reg = <0x0 0xfe400000 0x0 0x1000>; 1895 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1896 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1897 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1898 dmas = <&dmac1 0>; 1899 dma-names = "tx"; 1900 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1901 reset-names = "tx-m", "rx-m"; 1902 rockchip,cru = <&cru>; 1903 rockchip,grf = <&grf>; 1904 rockchip,playback-only; 1905 #sound-dai-cells = <0>; 1906 status = "disabled"; 1907 }; 1908 1909 i2s1_8ch: i2s@fe410000 { 1910 compatible = "rockchip,rk3568-i2s-tdm"; 1911 reg = <0x0 0xfe410000 0x0 0x1000>; 1912 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1913 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1914 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1915 dmas = <&dmac1 2>, <&dmac1 3>; 1916 dma-names = "tx", "rx"; 1917 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1918 reset-names = "tx-m", "rx-m"; 1919 rockchip,cru = <&cru>; 1920 rockchip,grf = <&grf>; 1921 #sound-dai-cells = <0>; 1922 pinctrl-names = "default"; 1923 pinctrl-0 = <&i2s1sclktxm0 1924 &i2s1sclkrxm0 1925 &i2s1lrcktxm0 1926 &i2s1lrckrxm0 1927 &i2s1sdi0m0 1928 &i2s1sdi1m0 1929 &i2s1sdi2m0 1930 &i2s1sdi3m0 1931 &i2s1sdo0m0 1932 &i2s1sdo1m0 1933 &i2s1sdo2m0 1934 &i2s1sdo3m0>; 1935 status = "disabled"; 1936 }; 1937 1938 i2s2_2ch: i2s@fe420000 { 1939 compatible = "rockchip,rk3568-i2s-tdm"; 1940 reg = <0x0 0xfe420000 0x0 0x1000>; 1941 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1942 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1943 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1944 dmas = <&dmac1 4>, <&dmac1 5>; 1945 dma-names = "tx", "rx"; 1946 rockchip,cru = <&cru>; 1947 rockchip,grf = <&grf>; 1948 rockchip,clk-trcm = <1>; 1949 #sound-dai-cells = <0>; 1950 pinctrl-names = "default"; 1951 pinctrl-0 = <&i2s2sclktxm0 1952 &i2s2lrcktxm0 1953 &i2s2sdim0 1954 &i2s2sdom0>; 1955 status = "disabled"; 1956 }; 1957 1958 i2s3_2ch: i2s@fe430000 { 1959 compatible = "rockchip,rk3568-i2s-tdm"; 1960 reg = <0x0 0xfe430000 0x0 0x1000>; 1961 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1962 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>; 1963 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1964 dmas = <&dmac1 6>, <&dmac1 7>; 1965 dma-names = "tx", "rx"; 1966 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 1967 reset-names = "tx-m", "rx-m"; 1968 rockchip,cru = <&cru>; 1969 rockchip,grf = <&grf>; 1970 #sound-dai-cells = <0>; 1971 pinctrl-names = "default"; 1972 pinctrl-0 = <&i2s3sclkm0 1973 &i2s3lrckm0 1974 &i2s3sdim0 1975 &i2s3sdom0>; 1976 status = "disabled"; 1977 }; 1978 1979 pdm: pdm@fe440000 { 1980 compatible = "rockchip,rk3568-pdm", "rockchip,pdm"; 1981 reg = <0x0 0xfe440000 0x0 0x1000>; 1982 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1983 clock-names = "pdm_clk", "pdm_hclk"; 1984 dmas = <&dmac1 9>; 1985 dma-names = "rx"; 1986 #sound-dai-cells = <0>; 1987 status = "disabled"; 1988 }; 1989 1990 vad: vad@fe450000 { 1991 compatible = "rockchip,rk3568-vad"; 1992 reg = <0x0 0xfe450000 0x0 0x10000>; 1993 reg-names = "vad"; 1994 clocks = <&cru HCLK_VAD>; 1995 clock-names = "hclk"; 1996 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1997 rockchip,audio-src = <0>; 1998 rockchip,det-channel = <0>; 1999 rockchip,mode = <0>; 2000 #sound-dai-cells = <0>; 2001 status = "disabled"; 2002 }; 2003 2004 spdif_8ch: spdif@fe460000 { 2005 compatible = "rockchip,rk3568-spdif"; 2006 reg = <0x0 0xfe460000 0x0 0x1000>; 2007 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2008 dmas = <&dmac1 1>; 2009 dma-names = "tx"; 2010 clock-names = "mclk", "hclk"; 2011 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 2012 #sound-dai-cells = <0>; 2013 pinctrl-names = "default"; 2014 pinctrl-0 = <&spdifm0_pins>; 2015 status = "disabled"; 2016 }; 2017 2018 audpwm: audpwm@fe470000 { 2019 compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1"; 2020 reg = <0x0 0xfe470000 0x0 0x1000>; 2021 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>; 2022 clock-names = "clk", "hclk"; 2023 dmas = <&dmac1 8>; 2024 dma-names = "tx"; 2025 #sound-dai-cells = <0>; 2026 rockchip,sample-width-bits = <11>; 2027 rockchip,interpolat-points = <1>; 2028 status = "disabled"; 2029 }; 2030 2031 dig_acodec: codec-digital@fe478000 { 2032 compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1"; 2033 reg = <0x0 0xfe478000 0x0 0x1000>; 2034 clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, 2035 <&cru CLK_ACDCDIG_I2C>, <&cru HCLK_ACDCDIG>; 2036 clock-names = "adc", "dac", "i2c", "pclk"; 2037 pinctrl-names = "default"; 2038 pinctrl-0 = <&acodec_pins>; 2039 resets = <&cru SRST_ACDCDIG>; 2040 reset-names = "reset" ; 2041 rockchip,grf = <&grf>; 2042 #sound-dai-cells = <0>; 2043 status = "disabled"; 2044 }; 2045 2046 dmac0: dmac@fe530000 { 2047 compatible = "arm,pl330", "arm,primecell"; 2048 reg = <0x0 0xfe530000 0x0 0x4000>; 2049 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2051 clocks = <&cru ACLK_BUS>; 2052 clock-names = "apb_pclk"; 2053 #dma-cells = <1>; 2054 arm,pl330-periph-burst; 2055 }; 2056 2057 dmac1: dmac@fe550000 { 2058 compatible = "arm,pl330", "arm,primecell"; 2059 reg = <0x0 0xfe550000 0x0 0x4000>; 2060 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 2061 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 2062 clocks = <&cru ACLK_BUS>; 2063 clock-names = "apb_pclk"; 2064 #dma-cells = <1>; 2065 arm,pl330-periph-burst; 2066 }; 2067 2068 can0: can@fe570000 { 2069 compatible = "rockchip,canfd-1.0"; 2070 reg = <0x0 0xfe570000 0x0 0x1000>; 2071 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 2072 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 2073 clock-names = "baudclk", "apb_pclk"; 2074 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 2075 reset-names = "can", "can-apb"; 2076 tx-fifo-depth = <1>; 2077 rx-fifo-depth = <6>; 2078 status = "disabled"; 2079 }; 2080 2081 can1: can@fe580000 { 2082 compatible = "rockchip,canfd-1.0"; 2083 reg = <0x0 0xfe580000 0x0 0x1000>; 2084 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 2085 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 2086 clock-names = "baudclk", "apb_pclk"; 2087 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 2088 reset-names = "can", "can-apb"; 2089 tx-fifo-depth = <1>; 2090 rx-fifo-depth = <6>; 2091 status = "disabled"; 2092 }; 2093 2094 can2: can@fe590000 { 2095 compatible = "rockchip,canfd-1.0"; 2096 reg = <0x0 0xfe590000 0x0 0x1000>; 2097 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 2098 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 2099 clock-names = "baudclk", "apb_pclk"; 2100 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; 2101 reset-names = "can", "can-apb"; 2102 tx-fifo-depth = <1>; 2103 rx-fifo-depth = <6>; 2104 status = "disabled"; 2105 }; 2106 2107 i2c1: i2c@fe5a0000 { 2108 compatible = "rockchip,rk3399-i2c"; 2109 reg = <0x0 0xfe5a0000 0x0 0x1000>; 2110 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2111 clock-names = "i2c", "pclk"; 2112 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2113 pinctrl-names = "default"; 2114 pinctrl-0 = <&i2c1_xfer>; 2115 #address-cells = <1>; 2116 #size-cells = <0>; 2117 status = "disabled"; 2118 }; 2119 2120 i2c2: i2c@fe5b0000 { 2121 compatible = "rockchip,rk3399-i2c"; 2122 reg = <0x0 0xfe5b0000 0x0 0x1000>; 2123 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2124 clock-names = "i2c", "pclk"; 2125 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 2126 pinctrl-names = "default"; 2127 pinctrl-0 = <&i2c2m0_xfer>; 2128 #address-cells = <1>; 2129 #size-cells = <0>; 2130 status = "disabled"; 2131 }; 2132 2133 i2c3: i2c@fe5c0000 { 2134 compatible = "rockchip,rk3399-i2c"; 2135 reg = <0x0 0xfe5c0000 0x0 0x1000>; 2136 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2137 clock-names = "i2c", "pclk"; 2138 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2139 pinctrl-names = "default"; 2140 pinctrl-0 = <&i2c3m0_xfer>; 2141 #address-cells = <1>; 2142 #size-cells = <0>; 2143 status = "disabled"; 2144 }; 2145 2146 i2c4: i2c@fe5d0000 { 2147 compatible = "rockchip,rk3399-i2c"; 2148 reg = <0x0 0xfe5d0000 0x0 0x1000>; 2149 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2150 clock-names = "i2c", "pclk"; 2151 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 2152 pinctrl-names = "default"; 2153 pinctrl-0 = <&i2c4m0_xfer>; 2154 #address-cells = <1>; 2155 #size-cells = <0>; 2156 status = "disabled"; 2157 }; 2158 2159 i2c5: i2c@fe5e0000 { 2160 compatible = "rockchip,rk3399-i2c"; 2161 reg = <0x0 0xfe5e0000 0x0 0x1000>; 2162 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2163 clock-names = "i2c", "pclk"; 2164 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2165 pinctrl-names = "default"; 2166 pinctrl-0 = <&i2c5m0_xfer>; 2167 #address-cells = <1>; 2168 #size-cells = <0>; 2169 status = "disabled"; 2170 }; 2171 2172 wdt: watchdog@fe600000 { 2173 compatible = "snps,dw-wdt"; 2174 reg = <0x0 0xfe600000 0x0 0x100>; 2175 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 2176 clock-names = "tclk", "pclk"; 2177 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 2178 resets = <&cru SRST_T_WDT_NS>; 2179 reset-names = "reset"; 2180 status = "okay"; 2181 }; 2182 2183 spi0: spi@fe610000 { 2184 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 2185 reg = <0x0 0xfe610000 0x0 0x1000>; 2186 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2187 #address-cells = <1>; 2188 #size-cells = <0>; 2189 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2190 clock-names = "spiclk", "apb_pclk"; 2191 dmas = <&dmac0 20>, <&dmac0 21>; 2192 dma-names = "tx", "rx"; 2193 pinctrl-names = "default", "high_speed"; 2194 pinctrl-0 = <&spi0clkm0 &spi0cs0m0 &spi0cs1m0 &spi0misom0 &spi0mosim0>; 2195 pinctrl-1 = <&spi0clkm0_hs &spi0cs0m0 &spi0cs1m0 &spi0misom0_hs &spi0mosim0_hs>; 2196 status = "disabled"; 2197 }; 2198 2199 spi1: spi@fe620000 { 2200 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 2201 reg = <0x0 0xfe620000 0x0 0x1000>; 2202 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2203 #address-cells = <1>; 2204 #size-cells = <0>; 2205 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2206 clock-names = "spiclk", "apb_pclk"; 2207 dmas = <&dmac0 22>, <&dmac0 23>; 2208 dma-names = "tx", "rx"; 2209 pinctrl-names = "default", "high_speed"; 2210 pinctrl-0 = <&spi1clkm0 &spi1cs0m0 &spi1cs1m0 &spi1misom0 &spi1mosim0>; 2211 pinctrl-1 = <&spi1clkm0_hs &spi1cs0m0 &spi1cs1m0 &spi1misom0_hs &spi1mosim0_hs>; 2212 status = "disabled"; 2213 }; 2214 2215 spi2: spi@fe630000 { 2216 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 2217 reg = <0x0 0xfe630000 0x0 0x1000>; 2218 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2219 #address-cells = <1>; 2220 #size-cells = <0>; 2221 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2222 clock-names = "spiclk", "apb_pclk"; 2223 dmas = <&dmac0 24>, <&dmac0 25>; 2224 dma-names = "tx", "rx"; 2225 pinctrl-names = "default", "high_speed"; 2226 pinctrl-0 = <&spi2clkm0 &spi2cs0m0 &spi2cs1m0 &spi2misom0 &spi2mosim0>; 2227 pinctrl-1 = <&spi2clkm0_hs &spi2cs0m0 &spi2cs1m0 &spi2misom0_hs &spi2mosim0_hs>; 2228 status = "disabled"; 2229 }; 2230 2231 spi3: spi@fe640000 { 2232 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 2233 reg = <0x0 0xfe640000 0x0 0x1000>; 2234 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2235 #address-cells = <1>; 2236 #size-cells = <0>; 2237 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2238 clock-names = "spiclk", "apb_pclk"; 2239 dmas = <&dmac0 26>, <&dmac0 27>; 2240 dma-names = "tx", "rx"; 2241 pinctrl-names = "default", "high_speed"; 2242 pinctrl-0 = <&spi3clkm0 &spi3cs0m0 &spi3cs1m0 &spi3misom0 &spi3mosim0>; 2243 pinctrl-1 = <&spi3clkm0_hs &spi3cs0m0 &spi3cs1m0 &spi3misom0_hs &spi3mosim0_hs>; 2244 status = "disabled"; 2245 }; 2246 2247 uart1: serial@fe650000 { 2248 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2249 reg = <0x0 0xfe650000 0x0 0x100>; 2250 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2251 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 2252 clock-names = "baudclk", "apb_pclk"; 2253 reg-shift = <2>; 2254 reg-io-width = <4>; 2255 dmas = <&dmac0 2>, <&dmac0 3>; 2256 pinctrl-names = "default"; 2257 pinctrl-0 = <&uart1m0_xfer>; 2258 status = "disabled"; 2259 }; 2260 2261 uart2: serial@fe660000 { 2262 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2263 reg = <0x0 0xfe660000 0x0 0x100>; 2264 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2265 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2266 clock-names = "baudclk", "apb_pclk"; 2267 reg-shift = <2>; 2268 reg-io-width = <4>; 2269 dmas = <&dmac0 4>, <&dmac0 5>; 2270 pinctrl-names = "default"; 2271 pinctrl-0 = <&uart2m0_xfer>; 2272 status = "disabled"; 2273 }; 2274 2275 uart3: serial@fe670000 { 2276 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2277 reg = <0x0 0xfe670000 0x0 0x100>; 2278 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2279 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2280 clock-names = "baudclk", "apb_pclk"; 2281 reg-shift = <2>; 2282 reg-io-width = <4>; 2283 dmas = <&dmac0 6>, <&dmac0 7>; 2284 pinctrl-names = "default"; 2285 pinctrl-0 = <&uart3m0_xfer>; 2286 status = "disabled"; 2287 }; 2288 2289 uart4: serial@fe680000 { 2290 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2291 reg = <0x0 0xfe680000 0x0 0x100>; 2292 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 2293 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2294 clock-names = "baudclk", "apb_pclk"; 2295 reg-shift = <2>; 2296 reg-io-width = <4>; 2297 dmas = <&dmac0 8>, <&dmac0 9>; 2298 pinctrl-names = "default"; 2299 pinctrl-0 = <&uart4m0_xfer>; 2300 status = "disabled"; 2301 }; 2302 2303 uart5: serial@fe690000 { 2304 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2305 reg = <0x0 0xfe690000 0x0 0x100>; 2306 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 2307 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2308 clock-names = "baudclk", "apb_pclk"; 2309 reg-shift = <2>; 2310 reg-io-width = <4>; 2311 dmas = <&dmac0 10>, <&dmac0 11>; 2312 pinctrl-names = "default"; 2313 pinctrl-0 = <&uart5m0_xfer>; 2314 status = "disabled"; 2315 }; 2316 2317 uart6: serial@fe6a0000 { 2318 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2319 reg = <0x0 0xfe6a0000 0x0 0x100>; 2320 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 2321 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2322 clock-names = "baudclk", "apb_pclk"; 2323 reg-shift = <2>; 2324 reg-io-width = <4>; 2325 dmas = <&dmac0 12>, <&dmac0 13>; 2326 pinctrl-names = "default"; 2327 pinctrl-0 = <&uart6m0_xfer>; 2328 status = "disabled"; 2329 }; 2330 2331 uart7: serial@fe6b0000 { 2332 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2333 reg = <0x0 0xfe6b0000 0x0 0x100>; 2334 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2335 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2336 clock-names = "baudclk", "apb_pclk"; 2337 reg-shift = <2>; 2338 reg-io-width = <4>; 2339 dmas = <&dmac0 14>, <&dmac0 15>; 2340 pinctrl-names = "default"; 2341 pinctrl-0 = <&uart7m0_xfer>; 2342 status = "disabled"; 2343 }; 2344 2345 uart8: serial@fe6c0000 { 2346 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2347 reg = <0x0 0xfe6c0000 0x0 0x100>; 2348 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 2349 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2350 clock-names = "baudclk", "apb_pclk"; 2351 reg-shift = <2>; 2352 reg-io-width = <4>; 2353 dmas = <&dmac0 16>, <&dmac0 17>; 2354 pinctrl-names = "default"; 2355 pinctrl-0 = <&uart8m0_xfer>; 2356 status = "disabled"; 2357 }; 2358 2359 uart9: serial@fe6d0000 { 2360 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2361 reg = <0x0 0xfe6d0000 0x0 0x100>; 2362 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2363 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2364 clock-names = "baudclk", "apb_pclk"; 2365 reg-shift = <2>; 2366 reg-io-width = <4>; 2367 dmas = <&dmac0 18>, <&dmac0 19>; 2368 pinctrl-names = "default"; 2369 pinctrl-0 = <&uart9m0_xfer>; 2370 status = "disabled"; 2371 }; 2372 2373 pwm4: pwm@fe6e0000 { 2374 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2375 reg = <0x0 0xfe6e0000 0x0 0x10>; 2376 #pwm-cells = <3>; 2377 pinctrl-names = "active"; 2378 pinctrl-0 = <&pwm4_pins>; 2379 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2380 clock-names = "pwm", "pclk"; 2381 status = "disabled"; 2382 }; 2383 2384 pwm5: pwm@fe6e0010 { 2385 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2386 reg = <0x0 0xfe6e0010 0x0 0x10>; 2387 #pwm-cells = <3>; 2388 pinctrl-names = "active"; 2389 pinctrl-0 = <&pwm5_pins>; 2390 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2391 clock-names = "pwm", "pclk"; 2392 status = "disabled"; 2393 }; 2394 2395 pwm6: pwm@fe6e0020 { 2396 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2397 reg = <0x0 0xfe6e0020 0x0 0x10>; 2398 #pwm-cells = <3>; 2399 pinctrl-names = "active"; 2400 pinctrl-0 = <&pwm6_pins>; 2401 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2402 clock-names = "pwm", "pclk"; 2403 status = "disabled"; 2404 }; 2405 2406 pwm7: pwm@fe6e0030 { 2407 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2408 reg = <0x0 0xfe6e0030 0x0 0x10>; 2409 #pwm-cells = <3>; 2410 pinctrl-names = "active"; 2411 pinctrl-0 = <&pwm7_pins>; 2412 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2413 clock-names = "pwm", "pclk"; 2414 status = "disabled"; 2415 }; 2416 2417 pwm8: pwm@fe6f0000 { 2418 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2419 reg = <0x0 0xfe6f0000 0x0 0x10>; 2420 #pwm-cells = <3>; 2421 pinctrl-names = "active"; 2422 pinctrl-0 = <&pwm8m0_pins>; 2423 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2424 clock-names = "pwm", "pclk"; 2425 status = "disabled"; 2426 }; 2427 2428 pwm9: pwm@fe6f0010 { 2429 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2430 reg = <0x0 0xfe6f0010 0x0 0x10>; 2431 #pwm-cells = <3>; 2432 pinctrl-names = "active"; 2433 pinctrl-0 = <&pwm9m0_pins>; 2434 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2435 clock-names = "pwm", "pclk"; 2436 status = "disabled"; 2437 }; 2438 2439 pwm10: pwm@fe6f0020 { 2440 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2441 reg = <0x0 0xfe6f0020 0x0 0x10>; 2442 #pwm-cells = <3>; 2443 pinctrl-names = "active"; 2444 pinctrl-0 = <&pwm10m0_pins>; 2445 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2446 clock-names = "pwm", "pclk"; 2447 status = "disabled"; 2448 }; 2449 2450 pwm11: pwm@fe6f0030 { 2451 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2452 reg = <0x0 0xfe6f0030 0x0 0x10>; 2453 #pwm-cells = <3>; 2454 pinctrl-names = "active"; 2455 pinctrl-0 = <&pwm11m0_pins>; 2456 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2457 clock-names = "pwm", "pclk"; 2458 status = "disabled"; 2459 }; 2460 2461 pwm12: pwm@fe700000 { 2462 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2463 reg = <0x0 0xfe700000 0x0 0x10>; 2464 #pwm-cells = <3>; 2465 pinctrl-names = "active"; 2466 pinctrl-0 = <&pwm12m0_pins>; 2467 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2468 clock-names = "pwm", "pclk"; 2469 status = "disabled"; 2470 }; 2471 2472 pwm13: pwm@fe700010 { 2473 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2474 reg = <0x0 0xfe700010 0x0 0x10>; 2475 #pwm-cells = <3>; 2476 pinctrl-names = "active"; 2477 pinctrl-0 = <&pwm13m0_pins>; 2478 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2479 clock-names = "pwm", "pclk"; 2480 status = "disabled"; 2481 }; 2482 2483 pwm14: pwm@fe700020 { 2484 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2485 reg = <0x0 0xfe700020 0x0 0x10>; 2486 #pwm-cells = <3>; 2487 pinctrl-names = "active"; 2488 pinctrl-0 = <&pwm14m0_pins>; 2489 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2490 clock-names = "pwm", "pclk"; 2491 status = "disabled"; 2492 }; 2493 2494 pwm15: pwm@fe700030 { 2495 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2496 reg = <0x0 0xfe700030 0x0 0x10>; 2497 #pwm-cells = <3>; 2498 pinctrl-names = "active"; 2499 pinctrl-0 = <&pwm15m0_pins>; 2500 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2501 clock-names = "pwm", "pclk"; 2502 status = "disabled"; 2503 }; 2504 2505 tsadc: tsadc@fe710000 { 2506 compatible = "rockchip,rk3568-tsadc"; 2507 reg = <0x0 0xfe710000 0x0 0x100>; 2508 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 2509 rockchip,grf = <&grf>; 2510 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2511 clock-names = "tsadc", "apb_pclk"; 2512 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 2513 assigned-clock-rates = <17000000>, <700000>; 2514 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, 2515 <&cru SRST_TSADCPHY>; 2516 reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; 2517 #thermal-sensor-cells = <1>; 2518 rockchip,hw-tshut-temp = <120000>; 2519 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 2520 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2521 pinctrl-names = "gpio", "otpout"; 2522 pinctrl-0 = <&tsadc_gpio>; 2523 pinctrl-1 = <&tsadc_shutorg>; 2524 status = "disabled"; 2525 }; 2526 2527 saradc: saradc@fe720000 { 2528 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 2529 reg = <0x0 0xfe720000 0x0 0x100>; 2530 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 2531 #io-channel-cells = <1>; 2532 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2533 clock-names = "saradc", "apb_pclk"; 2534 resets = <&cru SRST_P_SARADC>; 2535 reset-names = "saradc-apb"; 2536 status = "disabled"; 2537 }; 2538 2539 mailbox: mailbox@fe780000 { 2540 compatible = "rockchip,rk3568-mailbox", 2541 "rockchip,rk3368-mailbox"; 2542 reg = <0x0 0xfe780000 0x0 0x1000>; 2543 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2544 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2545 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2546 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2547 clocks = <&cru PCLK_MAILBOX>; 2548 clock-names = "pclk_mailbox"; 2549 #mbox-cells = <1>; 2550 status = "disabled"; 2551 }; 2552 2553 combphy0_us: phy@fe820000 { 2554 compatible = "rockchip,rk3568-naneng-combphy"; 2555 reg = <0x0 0xfe820000 0x0 0x100>; 2556 #phy-cells = <1>; 2557 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>; 2558 clock-names = "refclk", "apbclk"; 2559 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; 2560 assigned-clock-rates = <24000000>; 2561 resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; 2562 reset-names = "combphy-apb", "combphy"; 2563 rockchip,pipe-grf = <&pipegrf>; 2564 rockchip,pipe-phy-grf = <&pipe_phy_grf0>; 2565 status = "disabled"; 2566 }; 2567 2568 combphy1_usq: phy@fe830000 { 2569 compatible = "rockchip,rk3568-naneng-combphy"; 2570 reg = <0x0 0xfe830000 0x0 0x100>; 2571 #phy-cells = <1>; 2572 clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>; 2573 clock-names = "refclk", "apbclk"; 2574 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 2575 assigned-clock-rates = <24000000>; 2576 resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; 2577 reset-names = "combphy-apb", "combphy"; 2578 rockchip,pipe-grf = <&pipegrf>; 2579 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 2580 status = "disabled"; 2581 }; 2582 2583 combphy2_psq: phy@fe840000 { 2584 compatible = "rockchip,rk3568-naneng-combphy"; 2585 reg = <0x0 0xfe840000 0x0 0x100>; 2586 #phy-cells = <1>; 2587 clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>; 2588 clock-names = "refclk", "apbclk"; 2589 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 2590 assigned-clock-rates = <24000000>; 2591 resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; 2592 reset-names = "combphy-apb", "combphy"; 2593 rockchip,pipe-grf = <&pipegrf>; 2594 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 2595 status = "disabled"; 2596 }; 2597 2598 mipi_dphy0: mipi-dphy@fe850000 { 2599 compatible = "rockchip,rk3568-mipi-dphy"; 2600 reg = <0x0 0xfe850000 0x0 0x10000>; 2601 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; 2602 clock-names = "ref", "pclk"; 2603 clock-output-names = "mipi_dphy_pll"; 2604 #clock-cells = <0>; 2605 resets = <&cru SRST_P_MIPIDSIPHY0>; 2606 reset-names = "apb"; 2607 power-domains = <&power RK3568_PD_VO>; 2608 #phy-cells = <0>; 2609 rockchip,grf = <&grf>; 2610 status = "disabled"; 2611 }; 2612 2613 video_phy0: video-phy@fe850000 { 2614 compatible = "rockchip,rk3568-video-phy"; 2615 reg = <0x0 0xfe850000 0x0 0x10000>, 2616 <0x0 0xfe060000 0x0 0x10000>; 2617 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, 2618 <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>; 2619 clock-names = "ref", "pclk_phy", "pclk_host"; 2620 #clock-cells = <0>; 2621 resets = <&cru SRST_P_MIPIDSIPHY0>; 2622 reset-names = "rst"; 2623 power-domains = <&power RK3568_PD_VO>; 2624 #phy-cells = <0>; 2625 status = "disabled"; 2626 }; 2627 2628 mipi_dphy1: mipi-dphy@fe860000 { 2629 compatible = "rockchip,rk3568-mipi-dphy"; 2630 reg = <0x0 0xfe860000 0x0 0x10000>; 2631 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; 2632 clock-names = "ref", "pclk"; 2633 clock-output-names = "mipi_dphy1_pll"; 2634 #clock-cells = <0>; 2635 resets = <&cru SRST_P_MIPIDSIPHY1>; 2636 reset-names = "apb"; 2637 power-domains = <&power RK3568_PD_VO>; 2638 #phy-cells = <0>; 2639 rockchip,grf = <&grf>; 2640 status = "disabled"; 2641 }; 2642 2643 video_phy1: video-phy@fe860000 { 2644 compatible = "rockchip,rk3568-video-phy"; 2645 reg = <0x0 0xfe860000 0x0 0x10000>, 2646 <0x0 0xfe070000 0x0 0x10000>; 2647 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, 2648 <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>; 2649 clock-names = "ref", "pclk_phy", "pclk_host"; 2650 #clock-cells = <0>; 2651 resets = <&cru SRST_P_MIPIDSIPHY1>; 2652 reset-names = "rst"; 2653 power-domains = <&power RK3568_PD_VO>; 2654 #phy-cells = <0>; 2655 status = "disabled"; 2656 }; 2657 2658 csi_dphy: csi-dphy@fe870000 { 2659 compatible = "rockchip,rk3568-csi-dphy"; 2660 reg = <0x0 0xfe870000 0x0 0x1000>; 2661 clocks = <&cru PCLK_MIPICSIPHY>; 2662 clock-names = "pclk"; 2663 rockchip,grf = <&grf>; 2664 status = "disabled"; 2665 }; 2666 2667 usb2phy0: usb2-phy@fe8a0000 { 2668 compatible = "rockchip,rk3568-usb2phy"; 2669 reg = <0x0 0xfe8a0000 0x0 0x10000>; 2670 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 2671 clocks = <&pmucru CLK_USBPHY0_REF>; 2672 clock-names = "phyclk"; 2673 #clock-cells = <0>; 2674 assigned-clocks = <&cru USB480M>; 2675 assigned-clock-parents = <&usb2phy0>; 2676 clock-output-names = "usb480m_phy"; 2677 rockchip,usbgrf = <&usb2phy0_grf>; 2678 status = "disabled"; 2679 2680 u2phy0_host: host-port { 2681 #phy-cells = <0>; 2682 status = "disabled"; 2683 }; 2684 2685 u2phy0_otg: otg-port { 2686 #phy-cells = <0>; 2687 status = "disabled"; 2688 }; 2689 }; 2690 2691 usb2phy1: usb2-phy@fe8b0000 { 2692 compatible = "rockchip,rk3568-usb2phy"; 2693 reg = <0x0 0xfe8b0000 0x0 0x10000>; 2694 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 2695 clocks = <&pmucru CLK_USBPHY1_REF>; 2696 clock-names = "phyclk"; 2697 #clock-cells = <0>; 2698 rockchip,usbgrf = <&usb2phy1_grf>; 2699 status = "disabled"; 2700 2701 u2phy1_host: host-port { 2702 #phy-cells = <0>; 2703 status = "disabled"; 2704 }; 2705 2706 u2phy1_otg: otg-port { 2707 #phy-cells = <0>; 2708 status = "disabled"; 2709 }; 2710 }; 2711 2712 pcie30phy: phy@fe8c0000 { 2713 compatible = "rockchip,rk3568-pcie3-phy"; 2714 reg = <0x0 0xfe8c0000 0x0 0x20000>; 2715 #phy-cells = <0>; 2716 clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, 2717 <&cru PCLK_PCIE30PHY>; 2718 clock-names = "refclk_m", "refclk_n", "pclk"; 2719 resets = <&cru SRST_PCIE30PHY>; 2720 reset-names = "phy"; 2721 rockchip,phy-grf = <&pcie30_phy_grf>; 2722 status = "disabled"; 2723 }; 2724 2725 pinctrl: pinctrl { 2726 compatible = "rockchip,rk3568-pinctrl"; 2727 rockchip,grf = <&grf>; 2728 rockchip,pmu = <&pmugrf>; 2729 #address-cells = <2>; 2730 #size-cells = <2>; 2731 ranges; 2732 2733 gpio0: gpio@fdd60000 { 2734 compatible = "rockchip,gpio-bank"; 2735 reg = <0x0 0xfdd60000 0x0 0x100>; 2736 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2737 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 2738 2739 gpio-controller; 2740 #gpio-cells = <2>; 2741 gpio-ranges = <&pinctrl 0 0 32>; 2742 interrupt-controller; 2743 #interrupt-cells = <2>; 2744 }; 2745 2746 gpio1: gpio@fe740000 { 2747 compatible = "rockchip,gpio-bank"; 2748 reg = <0x0 0xfe740000 0x0 0x100>; 2749 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 2750 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2751 2752 gpio-controller; 2753 #gpio-cells = <2>; 2754 gpio-ranges = <&pinctrl 0 32 32>; 2755 interrupt-controller; 2756 #interrupt-cells = <2>; 2757 }; 2758 2759 gpio2: gpio@fe750000 { 2760 compatible = "rockchip,gpio-bank"; 2761 reg = <0x0 0xfe750000 0x0 0x100>; 2762 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2763 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2764 2765 gpio-controller; 2766 #gpio-cells = <2>; 2767 gpio-ranges = <&pinctrl 0 64 32>; 2768 interrupt-controller; 2769 #interrupt-cells = <2>; 2770 }; 2771 2772 gpio3: gpio@fe760000 { 2773 compatible = "rockchip,gpio-bank"; 2774 reg = <0x0 0xfe760000 0x0 0x100>; 2775 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2776 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2777 2778 gpio-controller; 2779 #gpio-cells = <2>; 2780 gpio-ranges = <&pinctrl 0 96 32>; 2781 interrupt-controller; 2782 #interrupt-cells = <2>; 2783 }; 2784 2785 gpio4: gpio@fe770000 { 2786 compatible = "rockchip,gpio-bank"; 2787 reg = <0x0 0xfe770000 0x0 0x100>; 2788 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2789 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2790 2791 gpio-controller; 2792 #gpio-cells = <2>; 2793 gpio-ranges = <&pinctrl 0 128 32>; 2794 interrupt-controller; 2795 #interrupt-cells = <2>; 2796 }; 2797 }; 2798}; 2799 2800#include "rk3568-pinctrl.dtsi" 2801