xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3568-spi-nand.dts (revision f2e13b14c7d5f7bee7ce4e450f96b3b293c4264c)

/*
 * SPDX-License-Identifier:     GPL-2.0+
 *
 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
 */

/dts-v1/;
#include "rk3568.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Rockchip RK3568 Evaluation Board";
	compatible = "rockchip,rk3568-evb", "rockchip,rk3568";

	aliases {
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		mmc0 = &sdhci;
		mmc1 = &sdmmc0;
		mmc2 = &sdmmc1;
	};

	chosen {
		stdout-path = &uart2;
		u-boot,spl-boot-order = &spi_nand;
	};

	adc-keys {
		compatible = "adc-keys";
		io-channels = <&saradc 0>;
		io-channel-names = "buttons";
		keyup-threshold-microvolt = <1800000>;
		u-boot,dm-spl;
		status = "okay";

		volumeup-key {
			u-boot,dm-spl;
			linux,code = <KEY_VOLUMEUP>;
			label = "volume up";
			press-threshold-microvolt = <9>;
		};
	};
};

&crypto {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&uart2 {
	clock-frequency = <24000000>;
	u-boot,dm-spl;
	/delete-property/ pinctrl-names;
	/delete-property/ pinctrl-0;
	status = "okay";
};

&grf {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&pmugrf {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usb2phy0_grf {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usbdrd30 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usbdrd_dwc3 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usbhost30 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usbhost_dwc3 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usb2phy0 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&u2phy0_otg {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&u2phy0_host {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&cru {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&pmucru {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&gmac0_clkin{
	u-boot,dm-pre-reloc;
};

&gmac1_clkin {
	u-boot,dm-pre-reloc;
};

&gmac0 {
	u-boot,dm-pre-reloc;
	phy-mode = "rgmii";
	clock_in_out = "output";

	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	/* Reset time is 20ms, 100ms for rtl8211f */
	snps,reset-delays-us = <0 20000 100000>;
	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
	assigned-clock-rates = <0>, <125000000>;

	pinctrl-names = "default";
	pinctrl-0 = <&gmac0_miim
		     &gmac0_tx_bus2
		     &gmac0_rx_bus2
		     &gmac0_rgmii_clk
		     &gmac0_rgmii_bus>;

	tx_delay = <0x3c>;
	rx_delay = <0x2f>;

	phy-handle = <&rgmii_phy0>;
	status = "disabled";
};

&gmac1 {
	u-boot,dm-pre-reloc;
	phy-mode = "rgmii";
	clock_in_out = "output";

	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	/* Reset time is 20ms, 100ms for rtl8211f */
	snps,reset-delays-us = <0 20000 100000>;

	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
	assigned-clock-rates = <0>, <125000000>;

	pinctrl-names = "default";
	pinctrl-0 = <&gmac1m1_miim
		     &gmac1m1_tx_bus2
		     &gmac1m1_rx_bus2
		     &gmac1m1_rgmii_clk
		     &gmac1m1_rgmii_bus>;

	tx_delay = <0x4f>;
	rx_delay = <0x26>;

	phy-handle = <&rgmii_phy1>;
	status = "disabled";
};

&gmac0_stmmac_axi_setup {
	u-boot,dm-pre-reloc;
};

&gmac0_mtl_rx_setup {
	u-boot,dm-pre-reloc;
	queue0 {
		u-boot,dm-pre-reloc;
	};
};

&gmac0_mtl_tx_setup {
	u-boot,dm-pre-reloc;
	queue0 {
		u-boot,dm-pre-reloc;
	};
};

&gmac1_stmmac_axi_setup {
	u-boot,dm-pre-reloc;
};

&gmac1_mtl_rx_setup {
	u-boot,dm-pre-reloc;
	queue0 {
		u-boot,dm-pre-reloc;
	};
};

&gmac1_mtl_tx_setup {
	u-boot,dm-pre-reloc;
	queue0 {
		u-boot,dm-pre-reloc;
	};
};

&mdio0 {
	u-boot,dm-pre-reloc;
	rgmii_phy0: phy@0 {
		compatible = "ethernet-phy-ieee802.3-c22";
		u-boot,dm-pre-reloc;
		reg = <0x0>;
	};
};

&mdio1 {
	u-boot,dm-pre-reloc;
	rgmii_phy1: phy@0 {
		compatible = "ethernet-phy-ieee802.3-c22";
		u-boot,dm-pre-reloc;
		reg = <0x0>;
	};
};

&gmac0_miim {
	u-boot,dm-pre-reloc;
};

&gmac0_clkinout {
	u-boot,dm-pre-reloc;
};

&gmac0_rx_bus2 {
	u-boot,dm-pre-reloc;
};

&gmac0_tx_bus2 {
	u-boot,dm-pre-reloc;
};

&gmac0_rgmii_clk {
	u-boot,dm-pre-reloc;
};

&gmac0_rgmii_bus {
	u-boot,dm-pre-reloc;
};

&gmac1m1_miim {
	u-boot,dm-pre-reloc;
};

&gmac1m1_clkinout {
	u-boot,dm-pre-reloc;
};

&gmac1m1_rx_bus2 {
	u-boot,dm-pre-reloc;
};

&gmac1m1_tx_bus2 {
	u-boot,dm-pre-reloc;
};

&gmac1m1_rgmii_clk {
	u-boot,dm-pre-reloc;
};

&gmac1m1_rgmii_bus {
	u-boot,dm-pre-reloc;
};

&eth0_clkout_pins {
	u-boot,dm-pre-reloc;
};

&eth1m1_clkout_pins {
	u-boot,dm-pre-reloc;
};

&pinctrl {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&gpio2 {
	u-boot,dm-pre-reloc;
};

&pcfg_pull_none_drv_level_1 {
	u-boot,dm-pre-reloc;
};

&pcfg_pull_none_drv_level_2 {
	u-boot,dm-pre-reloc;
};

&pcfg_pull_none {
	u-boot,dm-pre-reloc;
};

&wdt {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&sfc {
	u-boot,dm-spl;
	/delete-property/ pinctrl-names;
	/delete-property/ pinctrl-0;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-rates;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;
	spi_nand: flash@0 {
		u-boot,dm-spl;
		compatible = "spi-nand";
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <96000000>;
	};
};

&saradc {
	u-boot,dm-spl;
	status = "okay";
};