xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3562-u-boot.dtsi (revision fa4ecc325d8e45d11840ff3dd2f7ea3ac5bfb58a) 
1/*
2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		mmc0 = &sdhci;
10		mmc1 = &sdmmc0;
11	};
12
13	chosen {
14		stdout-path = &uart2;
15		u-boot,spl-boot-order = &sdmmc0, &sdhci, &spi_nand, &spi_nor;
16	};
17};
18
19&sys_grf {
20	u-boot,dm-spl;
21	status = "okay";
22};
23
24&ioc_grf {
25	u-boot,dm-spl;
26	status = "okay";
27};
28
29&pmu_grf {
30	u-boot,dm-spl;
31	status = "okay";
32};
33
34&usbphy_grf {
35	u-boot,dm-pre-reloc;
36	status = "okay";
37};
38
39&firmware {
40	u-boot,dm-spl;
41};
42
43&scmi {
44	u-boot,dm-spl;
45};
46
47&scmi_clk {
48	u-boot,dm-spl;
49};
50
51&scmi_shmem {
52	u-boot,dm-spl;
53};
54
55&cru {
56	u-boot,dm-spl;
57	status = "okay";
58};
59
60&crypto {
61	clocks = <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>;
62	clock-names = "sclk", "pka";
63	clock-frequency = <200000000>, <300000000>;
64	u-boot,dm-spl;
65	status = "okay";
66};
67
68&rng {
69	u-boot,dm-pre-reloc;
70	status = "okay";
71};
72
73&uart2 {
74	clock-frequency = <24000000>;
75	u-boot,dm-spl;
76	status = "okay";
77};
78
79&saradc0 {
80	u-boot,dm-pre-reloc;
81	status = "okay";
82};
83
84&psci {
85	u-boot,dm-pre-reloc;
86	status = "okay";
87};
88
89&sdhci {
90	bus-width = <8>;
91	u-boot,dm-spl;
92	/delete-property/ pinctrl-names;
93	/delete-property/ pinctrl-0;
94	mmc-hs400-1_8v;
95	mmc-hs400-enhanced-strobe;
96	fixed-emmc-driver-type = <1>;
97	status = "okay";
98};
99
100&sdmmc0 {
101	u-boot,dm-spl;
102	pinctrl-names = "default";
103	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
104	status = "okay";
105};
106
107&sdmmc0_pins {
108	u-boot,dm-spl;
109};
110
111&sdmmc0_bus4 {
112	u-boot,dm-spl;
113};
114
115&sdmmc0_clk {
116	u-boot,dm-spl;
117};
118
119&sdmmc0_cmd {
120	u-boot,dm-spl;
121};
122
123&sdmmc0_det {
124	u-boot,dm-spl;
125};
126
127&sfc {
128	u-boot,dm-spl;
129	status = "okay";
130
131	#address-cells = <1>;
132	#size-cells = <0>;
133	spi_nand: flash@0 {
134		u-boot,dm-spl;
135		compatible = "spi-nand";
136		reg = <0>;
137		spi-tx-bus-width = <1>;
138		spi-rx-bus-width = <4>;
139		spi-max-frequency = <80000000>;
140	};
141
142	spi_nor: flash@1 {
143		u-boot,dm-spl;
144		compatible = "jedec,spi-nor";
145		label = "sfc_nor";
146		reg = <0>;
147		spi-tx-bus-width = <1>;
148		spi-rx-bus-width = <4>;
149		spi-max-frequency = <80000000>;
150	};
151};
152
153&pinctrl {
154	u-boot,dm-spl;
155	status = "okay";
156};
157
158&gpio0 {
159	u-boot,dm-pre-reloc;
160};
161
162&gpio1 {
163	u-boot,dm-pre-reloc;
164};
165
166&gpio2 {
167	u-boot,dm-pre-reloc;
168};
169
170&gpio3 {
171	u-boot,dm-pre-reloc;
172};
173
174&gpio4 {
175	u-boot,dm-pre-reloc;
176};
177
178&pcfg_pull_up_drv_level_2 {
179	u-boot,dm-spl;
180	status = "okay";
181};
182
183&pcfg_pull_up {
184	u-boot,dm-spl;
185	status = "okay";
186};
187
188&u2phy {
189	u-boot,dm-pre-reloc;
190	status = "okay";
191};
192
193&u2phy_otg {
194	u-boot,dm-pre-reloc;
195	status = "okay";
196};
197