1/* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &sdhci; 10 mmc1 = &sdmmc0; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc0, &sdhci, &spi_nand, &spi_nor; 16 }; 17 18 secure-otp@ff920000 { 19 compatible = "rockchip,rk3562-secure-otp"; 20 reg = <0x0 0xff920000 0x0 0x4000>; 21 secure_conf = <0xff020034>; 22 mask_addr = <0x0>; 23 cru_rst_addr = <0xff130438>; 24 u-boot,dm-spl; 25 status = "okay"; 26 }; 27}; 28 29&sys_grf { 30 u-boot,dm-spl; 31 status = "okay"; 32}; 33 34&ioc_grf { 35 u-boot,dm-spl; 36 status = "okay"; 37}; 38 39&pmu_grf { 40 u-boot,dm-spl; 41 status = "okay"; 42}; 43 44&usbphy_grf { 45 u-boot,dm-pre-reloc; 46 status = "okay"; 47}; 48 49&firmware { 50 u-boot,dm-spl; 51}; 52 53&scmi { 54 u-boot,dm-spl; 55}; 56 57&scmi_clk { 58 u-boot,dm-spl; 59}; 60 61&scmi_shmem { 62 u-boot,dm-spl; 63}; 64 65&cru { 66 u-boot,dm-spl; 67 status = "okay"; 68}; 69 70&crypto { 71 clocks = <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>; 72 clock-names = "sclk", "pka"; 73 clock-frequency = <200000000>, <300000000>; 74 u-boot,dm-spl; 75 status = "okay"; 76}; 77 78&rng { 79 u-boot,dm-pre-reloc; 80 status = "okay"; 81}; 82 83&uart2 { 84 clock-frequency = <24000000>; 85 u-boot,dm-spl; 86 status = "okay"; 87}; 88 89&saradc0 { 90 u-boot,dm-pre-reloc; 91 status = "okay"; 92}; 93 94&psci { 95 u-boot,dm-pre-reloc; 96 status = "okay"; 97}; 98 99&sdhci { 100 bus-width = <8>; 101 u-boot,dm-spl; 102 /delete-property/ pinctrl-names; 103 /delete-property/ pinctrl-0; 104 mmc-hs400-1_8v; 105 mmc-hs400-enhanced-strobe; 106 fixed-emmc-driver-type = <1>; 107 status = "okay"; 108}; 109 110&sdmmc0 { 111 u-boot,dm-spl; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; 114 status = "okay"; 115}; 116 117&sdmmc0_pins { 118 u-boot,dm-spl; 119}; 120 121&sdmmc0_bus4 { 122 u-boot,dm-spl; 123}; 124 125&sdmmc0_clk { 126 u-boot,dm-spl; 127}; 128 129&sdmmc0_cmd { 130 u-boot,dm-spl; 131}; 132 133&sdmmc0_det { 134 u-boot,dm-spl; 135}; 136 137&sfc { 138 u-boot,dm-spl; 139 status = "okay"; 140 141 #address-cells = <1>; 142 #size-cells = <0>; 143 spi_nand: flash@0 { 144 u-boot,dm-spl; 145 compatible = "spi-nand"; 146 reg = <0>; 147 spi-tx-bus-width = <1>; 148 spi-rx-bus-width = <4>; 149 spi-max-frequency = <80000000>; 150 }; 151 152 spi_nor: flash@1 { 153 u-boot,dm-spl; 154 compatible = "jedec,spi-nor"; 155 label = "sfc_nor"; 156 reg = <0>; 157 spi-tx-bus-width = <1>; 158 spi-rx-bus-width = <4>; 159 spi-max-frequency = <80000000>; 160 }; 161}; 162 163&pinctrl { 164 u-boot,dm-spl; 165 status = "okay"; 166}; 167 168&gpio0 { 169 u-boot,dm-pre-reloc; 170}; 171 172&gpio1 { 173 u-boot,dm-pre-reloc; 174}; 175 176&gpio2 { 177 u-boot,dm-pre-reloc; 178}; 179 180&gpio3 { 181 u-boot,dm-pre-reloc; 182}; 183 184&gpio4 { 185 u-boot,dm-pre-reloc; 186}; 187 188&pcfg_pull_up_drv_level_2 { 189 u-boot,dm-spl; 190 status = "okay"; 191}; 192 193&pcfg_pull_up { 194 u-boot,dm-spl; 195 status = "okay"; 196}; 197 198&u2phy { 199 u-boot,dm-pre-reloc; 200 status = "okay"; 201}; 202 203&u2phy_otg { 204 u-boot,dm-pre-reloc; 205 status = "okay"; 206}; 207