1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3528-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3528-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/soc/rockchip-system-status.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 compatible = "rockchip,rk3528"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ethernet0 = &gmac0; 25 ethernet1 = &gmac1; 26 gpio0 = &gpio0; 27 gpio1 = &gpio1; 28 gpio2 = &gpio2; 29 gpio3 = &gpio3; 30 gpio4 = &gpio4; 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 serial0 = &uart0; 40 serial1 = &uart1; 41 serial2 = &uart2; 42 serial3 = &uart3; 43 serial4 = &uart4; 44 serial5 = &uart5; 45 serial6 = &uart6; 46 serial7 = &uart7; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi2 = &sfc; 50 }; 51 52 cpus { 53 #address-cells = <2>; 54 #size-cells = <0>; 55 56 cpu-map { 57 cluster0 { 58 core0 { 59 cpu = <&cpu0>; 60 }; 61 core1 { 62 cpu = <&cpu1>; 63 }; 64 core2 { 65 cpu = <&cpu2>; 66 }; 67 core3 { 68 cpu = <&cpu3>; 69 }; 70 }; 71 }; 72 73 cpu0: cpu@0 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x0 0x0>; 77 enable-method = "psci"; 78 }; 79 80 cpu1: cpu@1 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 reg = <0x0 0x1>; 84 enable-method = "psci"; 85 }; 86 87 cpu2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x0 0x2>; 91 enable-method = "psci"; 92 }; 93 94 cpu3: cpu@3 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53"; 97 reg = <0x0 0x3>; 98 enable-method = "psci"; 99 }; 100 }; 101 102 arm-pmu { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 109 }; 110 111 cpuinfo { 112 compatible = "rockchip,cpuinfo"; 113 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 114 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 115 }; 116 117 display_subsystem: display-subsystem { 118 compatible = "rockchip,display-subsystem"; 119 ports = <&vop_out>; 120 status = "disabled"; 121 }; 122 123 firmware { 124 scmi: scmi { 125 compatible = "arm,scmi-smc"; 126 shmem = <&scmi_shmem>; 127 arm,smc-id = <0x82000010>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 131 scmi_clk: protocol@14 { 132 reg = <0x14>; 133 #clock-cells = <1>; 134 }; 135 }; 136 }; 137 138 mpp_srv: mpp-srv { 139 compatible = "rockchip,mpp-service"; 140 rockchip,taskqueue-count = <5>; 141 rockchip,resetgroup-count = <5>; 142 status = "disabled"; 143 }; 144 145 psci: psci { 146 compatible = "arm,psci-1.0"; 147 method = "smc"; 148 }; 149 150 thermal_zones: thermal-zones { 151 soc_thermal: soc-thermal { 152 polling-delay-passive = <20>; /* milliseconds */ 153 polling-delay = <1000>; /* milliseconds */ 154 155 thermal-sensors = <&tsadc 0>; 156 trips { 157 soc_crit: soc-crit { 158 /* millicelsius */ 159 temperature = <115000>; 160 /* millicelsius */ 161 hysteresis = <2000>; 162 type = "critical"; 163 }; 164 }; 165 }; 166 }; 167 168 timer { 169 compatible = "arm,armv8-timer"; 170 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 171 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 172 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 173 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 174 }; 175 176 xin24m: xin24m { 177 compatible = "fixed-clock"; 178 #clock-cells = <0>; 179 clock-frequency = <24000000>; 180 clock-output-names = "xin24m"; 181 }; 182 183 xin32k: xin32k { 184 compatible = "fixed-clock"; 185 #clock-cells = <0>; 186 clock-frequency = <32768>; 187 clock-output-names = "xin32k"; 188 }; 189 190 scmi_shmem: scmi-shmem@10f000 { 191 compatible = "arm,scmi-shmem"; 192 reg = <0x0 0x0010f000 0x0 0x100>; 193 }; 194 195 pcie2x1: pcie@fe4f0000 { 196 compatible = "rockchip,rk3528-pcie", "snps,dw-pcie"; 197 #address-cells = <3>; 198 #size-cells = <2>; 199 bus-range = <0x0 0xff>; 200 clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>, 201 <&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>, 202 <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>, 203 <&cru CLK_PCIE_PIPE_PHY>; 204 clock-names = "aclk", "hclk_slv", 205 "hclk_dbi", "pclk_cru", 206 "aux", "pclk", 207 "pipe"; 208 device_type = "pci"; 209 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 214 interrupt-names = "pmc", "sys", "legacy", "msg", "err"; 215 #interrupt-cells = <1>; 216 interrupt-map-mask = <0 0 0 7>; 217 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, 218 <0 0 0 2 &pcie2x1_intc 1>, 219 <0 0 0 3 &pcie2x1_intc 2>, 220 <0 0 0 4 &pcie2x1_intc 3>; 221 linux,pci-domain = <0>; 222 num-ib-windows = <8>; 223 num-ob-windows = <8>; 224 num-viewport = <4>; 225 max-link-speed = <2>; 226 num-lanes = <1>; 227 phys = <&combphy_pu PHY_TYPE_PCIE>; 228 phy-names = "pcie-phy"; 229 ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000 230 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 231 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 232 0xc3000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>; 233 reg = <0x0 0xfe4f0000 0x0 0x10000>, 234 <0x1 0x40000000 0x0 0x400000>; 235 reg-names = "pcie-apb", "pcie-dbi"; 236 resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>, 237 <&cru SRST_PRESETN_CRU_PCIE>; 238 reset-names = "pcie", "periph", "preset_cru"; 239 status = "disabled"; 240 241 pcie2x1_intc: legacy-interrupt-controller { 242 interrupt-controller; 243 #address-cells = <0>; 244 #interrupt-cells = <1>; 245 interrupt-parent = <&gic>; 246 interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>; 247 }; 248 }; 249 250 usbdrd30: usbdrd { 251 compatible = "rockchip,rk3528-dwc3", "rockchip,rk3399-dwc3"; 252 clocks = <&cru CLK_REF_USB3OTG>, <&cru CLK_SUSPEND_USB3OTG>, 253 <&cru ACLK_USB3OTG>; 254 clock-names = "ref_clk", "suspend_clk", 255 "bus_clk"; 256 #address-cells = <2>; 257 #size-cells = <2>; 258 ranges; 259 status = "disabled"; 260 261 usbdrd_dwc3: dwc3@fe500000 { 262 compatible = "snps,dwc3"; 263 reg = <0x0 0xfe500000 0x0 0x400000>; 264 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 265 dr_mode = "otg"; 266 phy_type = "utmi_wide"; 267 resets = <&cru SRST_ARESETN_USB3OTG>; 268 reset-names = "usb3-otg"; 269 snps,dis_enblslpm_quirk; 270 snps,dis-u1u2-quirk; 271 snps,dis-u2-freeclk-exists-quirk; 272 snps,dis-del-phy-power-chg-quirk; 273 snps,dis-tx-ipgap-linecheck-quirk; 274 snps,xhci-trb-ent-quirk; 275 status = "disabled"; 276 }; 277 }; 278 279 gic: interrupt-controller@fed01000 { 280 compatible = "arm,gic-400"; 281 #interrupt-cells = <3>; 282 #address-cells = <0>; 283 interrupt-controller; 284 reg = <0x0 0xfed01000 0 0x1000>, 285 <0x0 0xfed02000 0 0x2000>, 286 <0x0 0xfed04000 0 0x2000>, 287 <0x0 0xfed06000 0 0x2000>; 288 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 289 }; 290 291 usb_host0_ehci: usb@ff100000 { 292 compatible = "generic-ehci"; 293 reg = <0x0 0xff100000 0x0 0x40000>; 294 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>; 296 clock-names = "usbhost", "arbiter"; 297 status = "disabled"; 298 }; 299 300 usb_host0_ohci: usb@ff140000 { 301 compatible = "generic-ohci"; 302 reg = <0x0 0xff140000 0x0 0x40000>; 303 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>; 305 clock-names = "usbhost", "arbiter"; 306 status = "disabled"; 307 }; 308 309 qos_crypto_a: qos@ff200000 { 310 compatible = "syscon"; 311 reg = <0x0 0xff200000 0x0 0x20>; 312 }; 313 314 qos_crypto_p: qos@ff200080 { 315 compatible = "syscon"; 316 reg = <0x0 0xff200080 0x0 0x20>; 317 }; 318 319 qos_dcf: qos@ff200100 { 320 compatible = "syscon"; 321 reg = <0x0 0xff200100 0x0 0x20>; 322 }; 323 324 qos_dft2apb: qos@ff200200 { 325 compatible = "syscon"; 326 reg = <0x0 0xff200200 0x0 0x20>; 327 }; 328 329 qos_dma2ddr: qos@ff200280 { 330 compatible = "syscon"; 331 reg = <0x0 0xff200280 0x0 0x20>; 332 }; 333 334 qos_dmac: qos@ff200300 { 335 compatible = "syscon"; 336 reg = <0x0 0xff200300 0x0 0x20>; 337 }; 338 339 qos_keyreader: qos@ff200380 { 340 compatible = "syscon"; 341 reg = <0x0 0xff200380 0x0 0x20>; 342 }; 343 344 qos_cpu: qos@ff210000 { 345 compatible = "syscon"; 346 reg = <0x0 0xff210000 0x0 0x20>; 347 }; 348 349 qos_debug: qos@ff210080 { 350 compatible = "syscon"; 351 reg = <0x0 0xff210080 0x0 0x20>; 352 }; 353 354 qos_gpu_m0: qos@ff220000 { 355 compatible = "syscon"; 356 reg = <0x0 0xff220000 0x0 0x20>; 357 }; 358 359 qos_gpu_m1: qos@ff220080 { 360 compatible = "syscon"; 361 reg = <0x0 0xff220080 0x0 0x20>; 362 }; 363 364 qos_pmu_mcu: qos@ff240000 { 365 compatible = "syscon"; 366 reg = <0x0 0xff240000 0x0 0x20>; 367 }; 368 369 qos_rkvdec: qos@ff250000 { 370 compatible = "syscon"; 371 reg = <0x0 0xff250000 0x0 0x20>; 372 }; 373 374 qos_rkvenc: qos@ff260000 { 375 compatible = "syscon"; 376 reg = <0x0 0xff260000 0x0 0x20>; 377 }; 378 379 qos_gmac0: qos@ff270000 { 380 compatible = "syscon"; 381 reg = <0x0 0xff270000 0x0 0x20>; 382 }; 383 384 qos_hdcp: qos@ff270080 { 385 compatible = "syscon"; 386 reg = <0x0 0xff270080 0x0 0x20>; 387 }; 388 389 qos_jpegdec: qos@ff270100 { 390 compatible = "syscon"; 391 reg = <0x0 0xff270100 0x0 0x20>; 392 }; 393 394 qos_rga2_m0ro: qos@ff270200 { 395 compatible = "syscon"; 396 reg = <0x0 0xff270200 0x0 0x20>; 397 }; 398 399 qos_rga2_m0wo: qos@ff270280 { 400 compatible = "syscon"; 401 reg = <0x0 0xff270280 0x0 0x20>; 402 }; 403 404 qos_sdmmc0: qos@ff270300 { 405 compatible = "syscon"; 406 reg = <0x0 0xff270300 0x0 0x20>; 407 }; 408 409 qos_usb2host: qos@ff270380 { 410 compatible = "syscon"; 411 reg = <0x0 0xff270380 0x0 0x20>; 412 }; 413 414 qos_vdpp: qos@ff270480 { 415 compatible = "syscon"; 416 reg = <0x0 0xff270480 0x0 0x20>; 417 }; 418 419 qos_vop: qos@ff270500 { 420 compatible = "syscon"; 421 reg = <0x0 0xff270500 0x0 0x20>; 422 }; 423 424 qos_emmc: qos@ff280000 { 425 compatible = "syscon"; 426 reg = <0x0 0xff280000 0x0 0x20>; 427 }; 428 429 qos_fspi: qos@ff280080 { 430 compatible = "syscon"; 431 reg = <0x0 0xff280080 0x0 0x20>; 432 }; 433 434 qos_gmac1: qos@ff280100 { 435 compatible = "syscon"; 436 reg = <0x0 0xff280100 0x0 0x20>; 437 }; 438 439 qos_pcie: qos@ff280180 { 440 compatible = "syscon"; 441 reg = <0x0 0xff280180 0x0 0x20>; 442 }; 443 444 qos_sdio0: qos@ff280200 { 445 compatible = "syscon"; 446 reg = <0x0 0xff280200 0x0 0x20>; 447 }; 448 449 qos_sdio1: qos@ff280280 { 450 compatible = "syscon"; 451 reg = <0x0 0xff280280 0x0 0x20>; 452 }; 453 454 qos_tsp: qos@ff280300 { 455 compatible = "syscon"; 456 reg = <0x0 0xff280300 0x0 0x20>; 457 }; 458 459 qos_usb3otg: qos@ff280380 { 460 compatible = "syscon"; 461 reg = <0x0 0xff280380 0x0 0x20>; 462 }; 463 464 qos_vpu: qos@ff280400 { 465 compatible = "syscon"; 466 reg = <0x0 0xff280400 0x0 0x20>; 467 }; 468 469 /* 470 * Merge all GRF, each independent GRF offset is shown as bellow: 471 * CORE_GRF: 0xff300000 472 * GPU_GRF: 0xff310000 473 * RKVENC_GRF: 0xff320000 474 * DDR_GRF: 0xff330000 475 * VPU_GRF: 0xff340000 476 * COMBO_PIPE_PHY_GRF: 0xff348000 477 * RKVDEC_GRF: 0xff350000 478 * VO_GRF: 0xff360000 479 * PMU_GRF: 0xff370000 480 * SYS_GRF: 0xff380000 481 */ 482 grf: syscon@ff300000 { 483 compatible = "rockchip,rk3528-grf", "syscon", "simple-mfd"; 484 reg = <0x0 0xff300000 0x0 0x90000>; 485 486 grf_cru: grf-clock-controller { 487 compatible = "rockchip,rk3528-grf-cru"; 488 #clock-cells = <1>; 489 }; 490 }; 491 492 cru: clock-controller@ff4a0000 { 493 compatible = "rockchip,rk3528-cru"; 494 reg = <0x0 0xff4a0000 0x0 0x30000>; 495 rockchip,grf = <&grf>; 496 #clock-cells = <1>; 497 #reset-cells = <1>; 498 499 assigned-clocks = 500 <&cru XIN_OSC0_DIV>, 501 <&cru PLL_GPLL>, 502 <&cru PLL_PPLL>, 503 <&cru PLL_CPLL>, 504 <&cru ARMCLK>, 505 <&cru CLK_MATRIX_250M_SRC>, 506 <&cru CLK_MATRIX_500M_SRC>, 507 <&cru CLK_MATRIX_50M_SRC>, 508 <&cru CLK_MATRIX_100M_SRC>, 509 <&cru CLK_MATRIX_150M_SRC>, 510 <&cru CLK_MATRIX_200M_SRC>, 511 <&cru CLK_MATRIX_300M_SRC>, 512 <&cru CLK_MATRIX_339M_SRC>, 513 <&cru CLK_MATRIX_400M_SRC>, 514 <&cru CLK_MATRIX_600M_SRC>, 515 <&cru CLK_PPLL_50M_MATRIX>, 516 <&cru CLK_PPLL_100M_MATRIX>, 517 <&cru CLK_PPLL_125M_MATRIX>, 518 <&cru ACLK_BUS_VOPGL_ROOT>; 519 520 assigned-clock-rates = 521 <32768>, 522 <1188000000>, 523 <1000000000>, 524 <996000000>, 525 <408000000>, 526 <250000000>, 527 <500000000>, 528 <50000000>, 529 <100000000>, 530 <150000000>, 531 <200000000>, 532 <300000000>, 533 <340000000>, 534 <400000000>, 535 <600000000>, 536 <50000000>, 537 <100000000>, 538 <125000000>, 539 <500000000>; 540 }; 541 542 ioc_grf: syscon@ff540000 { 543 compatible = "rockchip,rk3528-ioc-grf", "syscon"; 544 reg = <0x0 0xff540000 0x0 0x40000>; 545 }; 546 547 pmu: power-management@ff600000 { 548 compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd"; 549 reg = <0x0 0xff600000 0x0 0x2000>; 550 551 power: power-controller { 552 compatible = "rockchip,rk3528-power-controller"; 553 #power-domain-cells = <1>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "okay"; 557 558 /* These power domains are grouped by VD_GPU */ 559 pd_gpu@RK3528_PD_GPU { 560 reg = <RK3528_PD_GPU>; 561 clocks = <&cru ACLK_GPU_MALI>, 562 <&cru PCLK_GPU_ROOT>; 563 pm_qos = <&qos_gpu_m0>, 564 <&qos_gpu_m1>; 565 }; 566 /* These power domains are grouped by VD_LOGIC */ 567 pd_rkvdec@RK3528_PD_RKVDEC { 568 reg = <RK3528_PD_RKVDEC>; 569 }; 570 pd_rkvenc@RK3528_PD_RKVENC { 571 reg = <RK3528_PD_RKVENC>; 572 }; 573 pd_vo@RK3528_PD_VO { 574 reg = <RK3528_PD_VO>; 575 }; 576 pd_vpu@RK3528_PD_VPU { 577 reg = <RK3528_PD_VPU>; 578 }; 579 }; 580 }; 581 582 mailbox: mailbox@ff630000 { 583 compatible = "rockchip,rk3528-mailbox", 584 "rockchip,rk3368-mailbox"; 585 reg = <0x0 0xff630000 0x0 0x200>; 586 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&cru PCLK_PMU_MAILBOX>; 588 clock-names = "pclk_mailbox"; 589 #mbox-cells = <1>; 590 status = "disabled"; 591 }; 592 593 gpu: gpu@ff700000 { 594 compatible = "arm,mali-450"; 595 reg = <0x0 0xff700000 0x0 0x40000>; 596 597 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 604 interrupt-names = "Mali_GP_IRQ", 605 "Mali_GP_MMU_IRQ", 606 "IRQPP", 607 "Mali_PP0_IRQ", 608 "Mali_PP0_MMU_IRQ", 609 "Mali_PP1_IRQ", 610 "Mali_PP1_MMU_IRQ"; 611 power-domains = <&power RK3528_PD_GPU>; 612 status = "disabled"; 613 614 gpu_power_model: power_model { 615 compatible = "arm,mali-simple-power-model"; 616 voltage = <900>; 617 frequency = <500>; 618 static-power = <300>; 619 dynamic-power = <396>; 620 ts = <32000 4700 (-80) 2>; 621 thermal-zone = "soc-thermal"; 622 }; 623 }; 624 625 rkvdec: rkvdec@ff740100 { 626 compatible = "rockchip,rkv-decoder-v2"; 627 reg = <0x0 0xff740100 0x0 0x400>, <0x0 0xff740000 0x0 0x100>; 628 reg-names = "regs", "link"; 629 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 630 interrupt-names = "irq_dec"; 631 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; 632 clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac"; 633 rockchip,normal-rates = <340000000>, <0>, <600000000>; 634 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; 635 assigned-clock-rates = <340000000>, <600000000>; 636 resets = <&cru SRST_ARESETN_RKVDEC>, <&cru SRST_HRESETN_RKVDEC>, 637 <&cru SRST_RESETN_HEVC_CA_RKVDEC>; 638 reset-names = "video_a", "video_h", "video_hevc_cabac"; 639 power-domains = <&power RK3528_PD_RKVDEC>; 640 iommus = <&rkvdec_mmu>; 641 rockchip,srv = <&mpp_srv>; 642 rockchip,taskqueue-node = <0>; 643 rockchip,resetgroup-node = <0>; 644 rockchip,task-capacity = <16>; 645 status = "disabled"; 646 }; 647 648 rkvdec_mmu: iommu@ff740800 { 649 compatible = "rockchip,iommu-v2"; 650 reg = <0x0 0xff740800 0x0 0x40>, <0x0 0xff740900 0x0 0x40>; 651 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 652 interrupt-names = "rkvdec_mmu"; 653 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 654 clock-names = "aclk", "iface"; 655 power-domains = <&power RK3528_PD_RKVDEC>; 656 #iommu-cells = <0>; 657 status = "disabled"; 658 }; 659 660 rkvenc: rkvenc@ff780000 { 661 compatible = "rockchip,rkv-encoder-v2"; 662 reg = <0x0 0xff780000 0x0 0x6000>; 663 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 664 interrupt-names = "irq_rkvenc"; 665 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_CORE_RKVENC>; 666 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 667 rockchip,normal-rates = <300000000>, <0>, <300000000>; 668 resets = <&cru SRST_ARESETN_RKVENC>, <&cru SRST_HRESETN_RKVENC>, 669 <&cru SRST_RESETN_CORE_RKVENC>; 670 reset-names = "video_a", "video_h", "video_core"; 671 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_CORE_RKVENC>; 672 assigned-clock-rates = <300000000>, <300000000>; 673 power-domains = <&power RK3528_PD_RKVENC>; 674 iommus = <&rkvenc_mmu>; 675 rockchip,srv = <&mpp_srv>; 676 rockchip,taskqueue-node = <1>; 677 rockchip,resetgroup-node = <1>; 678 status = "disabled"; 679 }; 680 681 rkvenc_mmu: iommu@ff78f000 { 682 compatible = "rockchip,iommu-v2"; 683 reg = <0x0 0xff78f000 0x0 0x40>; 684 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 685 interrupt-names = "rkvenc_mmu"; 686 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; 687 clock-names = "aclk", "iface"; 688 power-domains = <&power RK3528_PD_RKVENC>; 689 #iommu-cells = <0>; 690 status = "disabled"; 691 }; 692 693 vdpu: vdpu@ff7c0400 { 694 compatible = "rockchip,vpu-decoder-v2"; 695 reg = <0x0 0xff7c0400 0x0 0x400>; 696 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 697 interrupt-names = "irq_dec"; 698 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 699 clock-names = "aclk_vcodec", "hclk_vcodec"; 700 resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>; 701 reset-names = "video_a", "video_h"; 702 power-domains = <&power RK3528_PD_VPU>; 703 iommus = <&vdpu_mmu>; 704 rockchip,srv = <&mpp_srv>; 705 rockchip,taskqueue-node = <2>; 706 rockchip,resetgroup-node = <2>; 707 status = "disabled"; 708 }; 709 710 vdpu_mmu: iommu@ff7c0800 { 711 compatible = "rockchip,iommu-v2"; 712 reg = <0x0 0xff7c0800 0x0 0x40>; 713 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 714 interrupt-names = "vdpu_mmu"; 715 clock-names = "aclk", "iface"; 716 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 717 power-domains = <&power RK3528_PD_VPU>; 718 #iommu-cells = <0>; 719 status = "disabled"; 720 }; 721 722 vop: vop@ff840000 { 723 compatible = "rockchip,rk3528-vop"; 724 reg = <0x0 0xff840000 0x0 0x3000>, 725 <0x0 0xff845000 0x0 0x1000>, 726 <0x0 0xff846400 0x0 0x800>; 727 reg-names = "regs", 728 "gamma_lut", 729 "acm_regs"; 730 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&cru ACLK_VOP>, 732 <&cru HCLK_VOP>, 733 <&cru DCLK_VOP0>, 734 <&cru DCLK_VOP1>; 735 clock-names = "aclk_vop", 736 "hclk_vop", 737 "dclk_vp0", 738 "dclk_vp1"; 739 assigned-clocks = <&cru DCLK_VOP0>; 740 assigned-clock-parents = <&hdmiphy>; 741 iommus = <&vop_mmu>; 742 rockchip,grf = <&grf>; 743 status = "disabled"; 744 745 vop_out: ports { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 749 port@0 { 750 #address-cells = <1>; 751 #size-cells = <0>; 752 reg = <0>; 753 754 vp0_out_hdmi: endpoint@0 { 755 reg = <0>; 756 remote-endpoint = <&hdmi_in_vp0>; 757 }; 758 }; 759 760 port@1 { 761 #address-cells = <1>; 762 #size-cells = <0>; 763 reg = <1>; 764 765 vp1_out_tve: endpoint@0 { 766 reg = <0>; 767 remote-endpoint = <&tve_in_vp1>; 768 }; 769 }; 770 }; 771 }; 772 773 vop_mmu: iommu@ff847e00 { 774 compatible = "rockchip,iommu-v2"; 775 reg = <0x0 0xff847e00 0x0 0x100>; 776 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 777 interrupt-names = "vop_mmu"; 778 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 779 clock-names = "aclk", "iface"; 780 #iommu-cells = <0>; 781 rockchip,disable-device-link-resume; 782 rockchip,shootdown-entire; 783 status = "disabled"; 784 }; 785 786 rga2: rga@ff850000 { 787 compatible = "rockchip,rga2_core0"; 788 reg = <0x0 0xff850000 0x0 0x1000>; 789 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 790 interrupt-names = "rga2_irq"; 791 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>; 792 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; 793 iommus = <&rga2_mmu>; 794 status = "disabled"; 795 }; 796 797 rga2_mmu: iommu@ff850f00 { 798 compatible = "rockchip,iommu-v2"; 799 reg = <0x0 0xff850f00 0x0 0x100>; 800 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 801 interrupt-names = "rga2_mmu"; 802 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>; 803 clock-names = "aclk", "iface"; 804 #iommu-cells = <0>; 805 status = "disabled"; 806 }; 807 808 iep: iep@ff860000 { 809 compatible = "rockchip,iep-v2"; 810 reg = <0x0 0xff860000 0x0 0x500>; 811 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>; 813 clock-names = "aclk", "hclk", "sclk"; 814 resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>, 815 <&cru SRST_RESETN_CORE_VDPP>; 816 reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s"; 817 rockchip,srv = <&mpp_srv>; 818 rockchip,taskqueue-node = <3>; 819 rockchip,resetgroup-node = <3>; 820 iommus = <&iep_mmu>; 821 status = "disabled"; 822 }; 823 824 iep_mmu: iommu@ff860800 { 825 compatible = "rockchip,iommu-v2"; 826 reg = <0x0 0xff860800 0x0 0x100>; 827 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 828 interrupt-names = "iep_mmu"; 829 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>; 830 clock-names = "aclk", "iface"; 831 #iommu-cells = <0>; 832 status = "disabled"; 833 }; 834 835 vdpp: vdpp@ff861000 { 836 compatible = "rockchip,vdpp-v1"; 837 reg = <0x0 0xff861000 0x0 0x100>, <0x0 0xff862000 0x0 0x900>; 838 reg-names = "vdpp_regs", "zme_regs"; 839 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>; 841 clock-names = "aclk", "hclk", "sclk"; 842 resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>, 843 <&cru SRST_RESETN_CORE_VDPP>; 844 reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s"; 845 rockchip,srv = <&mpp_srv>; 846 rockchip,taskqueue-node = <3>; 847 rockchip,resetgroup-node = <3>; 848 power-domains = <&power RK3528_PD_VO>; 849 iommus = <&iep_mmu>; 850 status = "disabled"; 851 }; 852 853 jpegd: jpegd@ff870000 { 854 compatible = "rockchip,rkv-jpeg-decoder-v1"; 855 reg = <0x0 0xff870000 0x0 0x400>; 856 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 858 clock-names = "aclk_vcodec", "hclk_vcodec"; 859 rockchip,disable-auto-freq; 860 resets = <&cru SRST_ARESETN_JPEG_DECODER>, <&cru SRST_HRESETN_JPEG_DECODER>; 861 reset-names = "video_a", "video_h"; 862 power-domains = <&power RK3528_PD_VO>; 863 iommus = <&jpegd_mmu>; 864 rockchip,srv = <&mpp_srv>; 865 rockchip,taskqueue-node = <4>; 866 rockchip,resetgroup-node = <4>; 867 status = "disabled"; 868 }; 869 870 jpegd_mmu: iommu@ff870480 { 871 compatible = "rockchip,iommu-v2"; 872 reg = <0x0 0xff870480 0x0 0x40>; 873 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 874 interrupt-names = "jpegd_mmu"; 875 clock-names = "aclk", "iface"; 876 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 877 power-domains = <&power RK3528_PD_VO>; 878 #iommu-cells = <0>; 879 status = "disabled"; 880 }; 881 882 tve: tve@ff880000 { 883 compatible = "rockchip,rk3528-tve"; 884 reg = <0x0 0xff880000 0x0 0x4000>; 885 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&cru HCLK_CVBS>, <&cru DCLK_CVBS>, <&cru DCLK_4X_CVBS>; 887 clock-names = "hclk", "dclk", "dclk_4x"; 888 rockchip,lumafilter0 = <0x000a0ffa>; 889 rockchip,lumafilter1 = <0x0ff4001a>; 890 rockchip,lumafilter2 = <0x00110fd2>; 891 rockchip,lumafilter3 = <0x0fe80051>; 892 rockchip,lumafilter4 = <0x001a0f74>; 893 rockchip,lumafilter5 = <0x0fe600ec>; 894 rockchip,lumafilter6 = <0x0ffa0e43>; 895 rockchip,lumafilter7 = <0x08200527>; 896 rockchip,tve-upsample = <0>; 897 rockchip,grf = <&grf>; 898 status = "disabled"; 899 900 ports { 901 #address-cells = <1>; 902 #size-cells = <0>; 903 904 port@0 { 905 reg = <0>; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 909 tve_in_vp1: endpoint@0 { 910 reg = <0>; 911 remote-endpoint = <&vp1_out_tve>; 912 status = "disabled"; 913 }; 914 }; 915 }; 916 }; 917 918 hdcp2: hdcp2@ff8c0000 { 919 compatible = "rockchip,rk3528-hdmi-hdcp2"; 920 reg = <0x0 0xff8c0000 0x0 0x2000>; 921 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&cru ACLK_HDCP>, <&cru PCLK_HDCP>, 923 <&cru HCLK_HDCP>; 924 clock-names ="aclk_hdcp2", "pclk_hdcp2", "hdcp2_clk_hdmi"; 925 status = "disabled"; 926 }; 927 928 hdmi: hdmi@ff8d0000 { 929 compatible = "rockchip,rk3528-dw-hdmi"; 930 reg = <0x0 0xff8d0000 0x0 0x20000>; 931 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&cru PCLK_HDMI>, 934 <&cru CLK_SFR_HDMI>, 935 <&cru CLK_CEC_HDMI>; 936 clock-names = "iahb", "isfr", "cec"; 937 reg-io-width = <4>; 938 rockchip,grf = <&grf>; 939 pinctrl-names = "default"; 940 pinctrl-0 = <&hdmi_pins>; 941 phys = <&hdmiphy>; 942 phy-names = "hdmi"; 943 #sound-dai-cells = <0>; 944 status = "disabled"; 945 946 ports { 947 #address-cells = <1>; 948 #size-cells = <0>; 949 950 port@0 { 951 reg = <0>; 952 #address-cells = <1>; 953 #size-cells = <0>; 954 955 hdmi_in_vp0: endpoint@0 { 956 reg = <0>; 957 remote-endpoint = <&vp0_out_hdmi>; 958 status = "disabled"; 959 }; 960 }; 961 }; 962 }; 963 964 can0: can@ff960000 { 965 compatible = "rockchip,rk3528-can"; 966 reg = <0x0 0xff960000 0x0 0x100>; 967 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 968 assigned-clocks = <&cru CLK_CAN0>; 969 assigned-clock-rates = <200000000>; 970 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 971 clock-names = "baudclk", "apb_pclk"; 972 resets = <&cru SRST_PRESETN_CAN0>, <&cru SRST_PRESETN_CAN0>; 973 reset-names = "can", "can-apb"; 974 status = "disabled"; 975 }; 976 977 can1: can@ff970000 { 978 compatible = "rockchip,rk3528-can"; 979 reg = <0x0 0xff970000 0x0 0x100>; 980 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 981 assigned-clocks = <&cru CLK_CAN1>; 982 assigned-clock-rates = <200000000>; 983 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 984 clock-names = "baudclk", "apb_pclk"; 985 resets = <&cru SRST_RESETN_CAN1>, <&cru SRST_PRESETN_CAN1>; 986 reset-names = "can", "can-apb"; 987 status = "disabled"; 988 }; 989 990 can2: can@ff980000 { 991 compatible = "rockchip,rk3528-can"; 992 reg = <0x0 0xff980000 0x0 0x100>; 993 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 994 assigned-clocks = <&cru CLK_CAN2>; 995 assigned-clock-rates = <200000000>; 996 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 997 clock-names = "baudclk", "apb_pclk"; 998 resets = <&cru SRST_RESETN_CAN2>, <&cru SRST_PRESETN_CAN2>; 999 reset-names = "can", "can-apb"; 1000 status = "disabled"; 1001 }; 1002 1003 can3: can@ff990000 { 1004 compatible = "rockchip,rk3528-can"; 1005 reg = <0x0 0xff990000 0x0 0x100>; 1006 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1007 assigned-clocks = <&cru CLK_CAN3>; 1008 assigned-clock-rates = <200000000>; 1009 clocks = <&cru CLK_CAN3>, <&cru PCLK_CAN3>; 1010 clock-names = "baudclk", "apb_pclk"; 1011 resets = <&cru SRST_RESETN_CAN3>, <&cru SRST_PRESETN_CAN3>; 1012 reset-names = "can", "can-apb"; 1013 status = "disabled"; 1014 }; 1015 1016 spi0: spi@ff9c0000 { 1017 compatible = "rockchip,rk3066-spi"; 1018 reg = <0x0 0xff9c0000 0x0 0x1000>; 1019 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1023 clock-names = "spiclk", "apb_pclk"; 1024 dmas = <&dmac 25>, <&dmac 24>; 1025 dma-names = "tx", "rx"; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&spi0_csn0 &spi0_csn1 &spi0_pins>; 1028 status = "disabled"; 1029 }; 1030 1031 spi1: spi@ff9d0000 { 1032 compatible = "rockchip,rk3066-spi"; 1033 reg = <0x0 0xff9d0000 0x0 0x1000>; 1034 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1038 clock-names = "spiclk", "apb_pclk"; 1039 dmas = <&dmac 31>, <&dmac 30>; 1040 dma-names = "tx", "rx"; 1041 pinctrl-names = "default"; 1042 pinctrl-0 = <&spi1_csn0 &spi1_csn1 &spi1_pins>; 1043 status = "disabled"; 1044 }; 1045 1046 uart0: serial@ff9f0000 { 1047 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1048 reg = <0x0 0xff9f0000 0x0 0x100>; 1049 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 1051 clock-names = "baudclk", "apb_pclk"; 1052 reg-shift = <2>; 1053 reg-io-width = <4>; 1054 dmas = <&dmac 8>, <&dmac 9>; 1055 status = "disabled"; 1056 }; 1057 1058 uart1: serial@ff9f8000 { 1059 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1060 reg = <0x0 0xff9f8000 0x0 0x100>; 1061 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1063 clock-names = "baudclk", "apb_pclk"; 1064 reg-shift = <2>; 1065 reg-io-width = <4>; 1066 dmas = <&dmac 10>, <&dmac 11>; 1067 status = "disabled"; 1068 }; 1069 1070 uart2: serial@ffa00000 { 1071 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1072 reg = <0x0 0xffa00000 0x0 0x100>; 1073 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1075 clock-names = "baudclk", "apb_pclk"; 1076 reg-shift = <2>; 1077 reg-io-width = <4>; 1078 dmas = <&dmac 12>, <&dmac 13>; 1079 status = "disabled"; 1080 }; 1081 1082 uart3: serial@ffa08000 { 1083 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1084 reg = <0x0 0xffa08000 0x0 0x100>; 1085 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1087 clock-names = "baudclk", "apb_pclk"; 1088 reg-shift = <2>; 1089 reg-io-width = <4>; 1090 dmas = <&dmac 14>, <&dmac 15>; 1091 status = "disabled"; 1092 }; 1093 1094 uart4: serial@ffa10000 { 1095 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1096 reg = <0x0 0xffa10000 0x0 0x100>; 1097 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1099 clock-names = "baudclk", "apb_pclk"; 1100 reg-shift = <2>; 1101 reg-io-width = <4>; 1102 dmas = <&dmac 16>, <&dmac 17>; 1103 status = "disabled"; 1104 }; 1105 1106 uart5: serial@ffa18000 { 1107 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1108 reg = <0x0 0xffa18000 0x0 0x100>; 1109 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1111 clock-names = "baudclk", "apb_pclk"; 1112 reg-shift = <2>; 1113 reg-io-width = <4>; 1114 dmas = <&dmac 18>, <&dmac 19>; 1115 status = "disabled"; 1116 }; 1117 1118 uart6: serial@ffa20000 { 1119 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1120 reg = <0x0 0xffa20000 0x0 0x100>; 1121 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1123 clock-names = "baudclk", "apb_pclk"; 1124 reg-shift = <2>; 1125 reg-io-width = <4>; 1126 dmas = <&dmac 20>, <&dmac 21>; 1127 status = "disabled"; 1128 }; 1129 1130 uart7: serial@ffa28000 { 1131 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1132 reg = <0x0 0xffa28000 0x0 0x100>; 1133 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1135 clock-names = "baudclk", "apb_pclk"; 1136 reg-shift = <2>; 1137 reg-io-width = <4>; 1138 dmas = <&dmac 22>, <&dmac 23>; 1139 status = "disabled"; 1140 }; 1141 1142 i2c0: i2c@ffa50000 { 1143 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1144 reg = <0x0 0xffa50000 0x0 0x1000>; 1145 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 1146 clock-names = "i2c", "pclk"; 1147 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 status = "disabled"; 1151 }; 1152 1153 i2c1: i2c@ffa58000 { 1154 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1155 reg = <0x0 0xffa58000 0x0 0x1000>; 1156 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1157 clock-names = "i2c", "pclk"; 1158 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 status = "disabled"; 1162 }; 1163 1164 i2c2: i2c@ffa60000 { 1165 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1166 reg = <0x0 0xffa60000 0x0 0x1000>; 1167 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1168 clock-names = "i2c", "pclk"; 1169 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 status = "disabled"; 1173 }; 1174 1175 i2c3: i2c@ffa68000 { 1176 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1177 reg = <0x0 0xffa68000 0x0 0x1000>; 1178 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1179 clock-names = "i2c", "pclk"; 1180 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 status = "disabled"; 1184 }; 1185 1186 i2c4: i2c@ffa70000 { 1187 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1188 reg = <0x0 0xffa70000 0x0 0x1000>; 1189 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1190 clock-names = "i2c", "pclk"; 1191 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 status = "disabled"; 1195 }; 1196 1197 i2c5: i2c@ffa78000 { 1198 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1199 reg = <0x0 0xffa78000 0x0 0x1000>; 1200 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1201 clock-names = "i2c", "pclk"; 1202 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 status = "disabled"; 1206 }; 1207 1208 i2c6: i2c@ffa80000 { 1209 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1210 reg = <0x0 0xffa80000 0x0 0x1000>; 1211 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 1212 clock-names = "i2c", "pclk"; 1213 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 status = "disabled"; 1217 }; 1218 1219 i2c7: i2c@ffa88000 { 1220 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1221 reg = <0x0 0xffa88000 0x0 0x1000>; 1222 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 1223 clock-names = "i2c", "pclk"; 1224 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1225 #address-cells = <1>; 1226 #size-cells = <0>; 1227 status = "disabled"; 1228 }; 1229 1230 pwm0: pwm@ffa90000 { 1231 compatible = "rockchip,rv3528-pwm", "rockchip,rk3328-pwm"; 1232 reg = <0x0 0xffa90000 0x0 0x10>; 1233 #pwm-cells = <3>; 1234 pinctrl-names = "active"; 1235 pinctrl-0 = <&pwm0m0_pins>; 1236 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1237 clock-names = "pwm", "pclk"; 1238 status = "disabled"; 1239 }; 1240 1241 pwm1: pwm@ffa90010 { 1242 compatible = "rockchip,rv3528-pwm", "rockchip,rk3328-pwm"; 1243 reg = <0x0 0xffa90010 0x0 0x10>; 1244 #pwm-cells = <3>; 1245 pinctrl-names = "active"; 1246 pinctrl-0 = <&pwm1m0_pins>; 1247 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1248 clock-names = "pwm", "pclk"; 1249 status = "disabled"; 1250 }; 1251 1252 pwm2: pwm@ffa90020 { 1253 compatible = "rockchip,rv3528-pwm", "rockchip,rk3328-pwm"; 1254 reg = <0x0 0xffa90020 0x0 0x10>; 1255 #pwm-cells = <3>; 1256 pinctrl-names = "active"; 1257 pinctrl-0 = <&pwm2m0_pins>; 1258 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1259 clock-names = "pwm", "pclk"; 1260 status = "disabled"; 1261 }; 1262 1263 pwm3: pwm@ffa90030 { 1264 compatible = "rockchip,rv3528-pwm", "rockchip,rk3328-pwm"; 1265 reg = <0x0 0xffa90030 0x0 0x10>; 1266 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1268 #pwm-cells = <3>; 1269 pinctrl-names = "active"; 1270 pinctrl-0 = <&pwm3m0_pins>; 1271 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1272 clock-names = "pwm", "pclk"; 1273 status = "disabled"; 1274 }; 1275 1276 pwm4: pwm@ffa98000 { 1277 compatible = "rockchip,rv3528-pwm", "rockchip,rk3328-pwm"; 1278 reg = <0x0 0xffa98000 0x0 0x10>; 1279 #pwm-cells = <3>; 1280 pinctrl-names = "active"; 1281 pinctrl-0 = <&pwm4m0_pins>; 1282 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1283 clock-names = "pwm", "pclk"; 1284 status = "disabled"; 1285 }; 1286 1287 pwm5: pwm@ffa98010 { 1288 compatible = "rockchip,rv3528-pwm", "rockchip,rk3328-pwm"; 1289 reg = <0x0 0xffa98010 0x0 0x10>; 1290 #pwm-cells = <3>; 1291 pinctrl-names = "active"; 1292 pinctrl-0 = <&pwm5m0_pins>; 1293 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1294 clock-names = "pwm", "pclk"; 1295 status = "disabled"; 1296 }; 1297 1298 pwm6: pwm@ffa98020 { 1299 compatible = "rockchip,rv3528-pwm", "rockchip,rk3328-pwm"; 1300 reg = <0x0 0xffa98020 0x0 0x10>; 1301 #pwm-cells = <3>; 1302 pinctrl-names = "active"; 1303 pinctrl-0 = <&pwm6m0_pins>; 1304 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1305 clock-names = "pwm", "pclk"; 1306 status = "disabled"; 1307 }; 1308 1309 pwm7: pwm@ffa98030 { 1310 compatible = "rockchip,rv3528-pwm", "rockchip,rk3328-pwm"; 1311 reg = <0x0 0xffa98030 0x0 0x10>; 1312 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1314 #pwm-cells = <3>; 1315 pinctrl-names = "active"; 1316 pinctrl-0 = <&pwm7m0_pins>; 1317 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1318 clock-names = "pwm", "pclk"; 1319 status = "disabled"; 1320 }; 1321 1322 wdt: watchdog@ffac0000 { 1323 compatible = "snps,dw-wdt"; 1324 reg = <0x0 0xffac0000 0x0 0x100>; 1325 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1326 clock-names = "tclk", "pclk"; 1327 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1328 status = "disabled"; 1329 }; 1330 1331 tsadc: tsadc@ffad0000 { 1332 compatible = "rockchip,rk3528-tsadc"; 1333 reg = <0x0 0xffad0000 0x0 0x400>; 1334 rockchip,grf = <&grf>; 1335 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1336 clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>; 1337 clock-names = "tsadc", "tsadc_tsen", "apb_pclk"; 1338 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; 1339 assigned-clock-rates = <1200000>, <12000000>; 1340 resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>; 1341 reset-names = "tsadc", "tsadc-apb"; 1342 #thermal-sensor-cells = <1>; 1343 rockchip,hw-tshut-temp = <120000>; 1344 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 1345 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 1346 status = "disabled"; 1347 }; 1348 1349 saradc: saradc@ffae0000 { 1350 compatible = "rockchip,rk3528-saradc"; 1351 reg = <0x0 0xffae0000 0x0 0x10000>; 1352 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1353 #io-channel-cells = <1>; 1354 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1355 clock-names = "saradc", "apb_pclk"; 1356 resets = <&cru SRST_PRESETN_SARADC>; 1357 reset-names = "saradc-apb"; 1358 status = "disabled"; 1359 }; 1360 1361 sai3: sai@ffb70000 { 1362 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; 1363 reg = <0x0 0xffb70000 0x0 0x1000>; 1364 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1365 clocks = <&cru MCLK_SAI_I2S3>, <&cru HCLK_SAI_I2S3>; 1366 clock-names = "mclk", "hclk"; 1367 dmas = <&dmac 5>; 1368 dma-names = "tx"; 1369 resets = <&cru SRST_MRESETN_SAI_I2S3>, <&cru SRST_HRESETN_SAI_I2S3>; 1370 reset-names = "m", "h"; 1371 #sound-dai-cells = <0>; 1372 status = "disabled"; 1373 }; 1374 1375 sai0: sai@ffb80000 { 1376 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; 1377 reg = <0x0 0xffb80000 0x0 0x1000>; 1378 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1379 clocks = <&cru MCLK_SAI_I2S0>, <&cru HCLK_SAI_I2S0>; 1380 clock-names = "mclk", "hclk"; 1381 dmas = <&dmac 1>, <&dmac 0>; 1382 dma-names = "tx", "rx"; 1383 resets = <&cru SRST_MRESETN_SAI_I2S0>, <&cru SRST_HRESETN_SAI_I2S0>; 1384 reset-names = "m", "h"; 1385 pinctrl-names = "default"; 1386 pinctrl-0 = <&i2s0m0_pins>; 1387 #sound-dai-cells = <0>; 1388 status = "disabled"; 1389 }; 1390 1391 sai2: sai@ffb90000 { 1392 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; 1393 reg = <0x0 0xffb90000 0x0 0x1000>; 1394 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1395 clocks = <&cru MCLK_SAI_I2S2>, <&cru HCLK_SAI_I2S2>; 1396 clock-names = "mclk", "hclk"; 1397 dmas = <&dmac 4>; 1398 dma-names = "tx"; 1399 resets = <&cru SRST_MRESETN_SAI_I2S2>, <&cru SRST_HRESETN_SAI_I2S2>; 1400 reset-names = "m", "h"; 1401 #sound-dai-cells = <0>; 1402 status = "disabled"; 1403 }; 1404 1405 sai1: sai@ffba0000 { 1406 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; 1407 reg = <0x0 0xffba0000 0x0 0x1000>; 1408 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1409 clocks = <&cru MCLK_SAI_I2S1>, <&cru HCLK_SAI_I2S1>; 1410 clock-names = "mclk", "hclk"; 1411 dmas = <&dmac 3>, <&dmac 2>; 1412 dma-names = "tx", "rx"; 1413 resets = <&cru SRST_MRESETN_SAI_I2S1>, <&cru SRST_HRESETN_SAI_I2S1>; 1414 reset-names = "m", "h"; 1415 pinctrl-names = "default"; 1416 pinctrl-0 = <&i2s1_pins>; 1417 #sound-dai-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 pdm: pdm@ffbb0000 { 1422 compatible = "rockchip,rk3528-pdm", "rockchip,rk3568-pdm"; 1423 reg = <0x0 0xffbb0000 0x0 0x1000>; 1424 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1425 clock-names = "pdm_clk", "pdm_hclk"; 1426 dmas = <&dmac 6>; 1427 dma-names = "rx"; 1428 pinctrl-names = "default"; 1429 pinctrl-0 = <&pdm_clk0 1430 &pdm_clk1 1431 &pdm_sdi0 1432 &pdm_sdi1 1433 &pdm_sdi2 1434 &pdm_sdi3>; 1435 #sound-dai-cells = <0>; 1436 status = "disabled"; 1437 }; 1438 1439 spdif_8ch: spdif@ffbc0000 { 1440 compatible = "rockchip,rk3528-spdif", "rockchip,rk3568-spdif"; 1441 reg = <0x0 0xffbc0000 0x0 0x1000>; 1442 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 1443 dmas = <&dmac 7>; 1444 dma-names = "tx"; 1445 clock-names = "mclk", "hclk"; 1446 clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>; 1447 #sound-dai-cells = <0>; 1448 pinctrl-names = "default"; 1449 pinctrl-0 = <&spdifm0_pins>; 1450 status = "disabled"; 1451 }; 1452 1453 gmac0: ethernet@ffbd0000 { 1454 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 1455 reg = <0x0 0xffbd0000 0x0 0x10000>; 1456 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1458 interrupt-names = "macirq", "eth_wake_irq"; 1459 rockchip,grf = <&grf>; 1460 clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>, 1461 <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>, 1462 <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>; 1463 clock-names = "stmmaceth", "clk_mac_ref", 1464 "mac_clk_rx", "mac_clk_tx", 1465 "pclk_mac", "aclk_mac"; 1466 resets = <&cru SRST_ARESETN_MAC_VO>; 1467 reset-names = "stmmaceth"; 1468 1469 snps,mixed-burst; 1470 snps,tso; 1471 1472 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1473 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1474 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1475 1476 phy-mode = "rmii"; 1477 clock_in_out = "input"; 1478 phy-handle = <&rmii0_phy>; 1479 1480 status = "disabled"; 1481 1482 mdio0: mdio { 1483 compatible = "snps,dwmac-mdio"; 1484 #address-cells = <0x1>; 1485 #size-cells = <0x0>; 1486 rmii0_phy: ethernet-phy@2 { 1487 compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22"; 1488 reg = <2>; 1489 clocks = <&cru CLK_MACPHY>; 1490 resets = <&cru SRST_RESETN_MACPHY>; 1491 phy-is-integrated; 1492 }; 1493 }; 1494 1495 gmac0_stmmac_axi_setup: stmmac-axi-config { 1496 snps,wr_osr_lmt = <4>; 1497 snps,rd_osr_lmt = <8>; 1498 snps,blen = <0 0 0 0 16 8 4>; 1499 }; 1500 1501 gmac0_mtl_rx_setup: rx-queues-config { 1502 snps,rx-queues-to-use = <1>; 1503 queue0 {}; 1504 }; 1505 1506 gmac0_mtl_tx_setup: tx-queues-config { 1507 snps,tx-queues-to-use = <1>; 1508 queue0 {}; 1509 }; 1510 }; 1511 1512 gmac1: ethernet@ffbe0000 { 1513 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 1514 reg = <0x0 0xffbe0000 0x0 0x10000>; 1515 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1517 interrupt-names = "macirq", "eth_wake_irq"; 1518 rockchip,grf = <&grf>; 1519 clocks = <&cru CLK_GMAC1_SRC_VPU>, <&cru CLK_GMAC1_RMII_VPU>, 1520 <&cru PCLK_MAC_VPU>, <&cru ACLK_MAC_VPU>; 1521 clock-names = "stmmaceth", "clk_mac_ref", 1522 "pclk_mac", "aclk_mac"; 1523 resets = <&cru SRST_ARESETN_MAC>; 1524 reset-names = "stmmaceth"; 1525 1526 snps,mixed-burst; 1527 snps,tso; 1528 1529 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1530 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1531 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1532 1533 status = "disabled"; 1534 1535 mdio1: mdio { 1536 compatible = "snps,dwmac-mdio"; 1537 #address-cells = <0x1>; 1538 #size-cells = <0x0>; 1539 }; 1540 1541 gmac1_stmmac_axi_setup: stmmac-axi-config { 1542 snps,wr_osr_lmt = <4>; 1543 snps,rd_osr_lmt = <8>; 1544 snps,blen = <0 0 0 0 16 8 4>; 1545 }; 1546 1547 gmac1_mtl_rx_setup: rx-queues-config { 1548 snps,rx-queues-to-use = <1>; 1549 queue0 {}; 1550 }; 1551 1552 gmac1_mtl_tx_setup: tx-queues-config { 1553 snps,tx-queues-to-use = <1>; 1554 queue0 {}; 1555 }; 1556 }; 1557 1558 sdhci: mmc@ffbf0000 { 1559 compatible = "rockchip,rk3528-dwcmshc"; 1560 reg = <0x0 0xffbf0000 0x0 0x10000>; 1561 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1562 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; 1563 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1564 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 1565 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1566 <&cru TCLK_EMMC>; 1567 clock-names = "core", "bus", "axi", "block", "timer"; 1568 resets = <&cru SRST_CRESETN_EMMC>, <&cru SRST_HRESETN_EMMC>, 1569 <&cru SRST_ARESETN_EMMC>, <&cru SRST_BRESETN_EMMC>, 1570 <&cru SRST_TRESETN_EMMC>; 1571 reset-names = "core", "bus", "axi", "block", "timer"; 1572 max-frequency = <200000000>; 1573 status = "disabled"; 1574 }; 1575 1576 sfc: spi@ffc00000 { 1577 compatible = "rockchip,sfc"; 1578 reg = <0x0 0xffc00000 0x0 0x4000>; 1579 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1580 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1581 clock-names = "clk_sfc", "hclk_sfc"; 1582 assigned-clocks = <&cru SCLK_SFC>; 1583 assigned-clock-rates = <100000000>; 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 status = "disabled"; 1587 }; 1588 1589 sdio0: mmc@ffc10000 { 1590 compatible = "rockchip,rk3528-dw-mshc", 1591 "rockchip,rk3288-dw-mshc"; 1592 reg = <0x0 0xffc10000 0x0 0x4000>; 1593 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1594 max-frequency = <150000000>; 1595 clocks = <&cru HCLK_SDIO0>, <&cru CCLK_SRC_SDIO0>, 1596 <&grf_cru SCLK_SDIO0_DRV>, <&grf_cru SCLK_SDIO0_SAMPLE>; 1597 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1598 fifo-depth = <0x100>; 1599 resets = <&cru SRST_HRESETN_SDIO0>; 1600 reset-names = "reset"; 1601 status = "disabled"; 1602 }; 1603 1604 sdio1: mmc@ffc20000 { 1605 compatible = "rockchip,rk3528-dw-mshc", 1606 "rockchip,rk3288-dw-mshc"; 1607 reg = <0x0 0xffc20000 0x0 0x4000>; 1608 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1609 max-frequency = <150000000>; 1610 clocks = <&cru HCLK_SDIO1>, <&cru CCLK_SRC_SDIO1>, 1611 <&grf_cru SCLK_SDIO1_DRV>, <&grf_cru SCLK_SDIO1_SAMPLE>; 1612 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1613 fifo-depth = <0x100>; 1614 resets = <&cru SRST_HRESETN_SDIO1>; 1615 reset-names = "reset"; 1616 status = "disabled"; 1617 }; 1618 1619 sdmmc: mmc@ffc30000 { 1620 compatible = "rockchip,rk3528-dw-mshc", 1621 "rockchip,rk3288-dw-mshc"; 1622 reg = <0x0 0xffc30000 0x0 0x4000>; 1623 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1624 max-frequency = <150000000>; 1625 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>, 1626 <&grf_cru SCLK_SDMMC_DRV>, <&grf_cru SCLK_SDMMC_SAMPLE>; 1627 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1628 fifo-depth = <0x100>; 1629 resets = <&cru SRST_HRESETN_SDMMC0>; 1630 reset-names = "reset"; 1631 status = "disabled"; 1632 }; 1633 1634 crypto: crypto@ffc40000 { 1635 compatible = "rockchip,crypto-v4"; 1636 reg = <0x0 0xffc40000 0x0 0x2000>; 1637 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1638 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 1639 <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 1640 clock-names = "aclk", "hclk", "sclk", "pka"; 1641 assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 1642 assigned-clock-rates = <300000000>, <300000000>; 1643 resets = <&cru SRST_RESETN_CORE_CRYPTO>; 1644 reset-names = "crypto-rst"; 1645 status = "disabled"; 1646 }; 1647 1648 rng: rng@ffc50000 { 1649 compatible = "rockchip,trngv2"; 1650 reg = <0x0 0xffc50000 0x0 0x200>; 1651 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1652 clocks = <&cru HCLK_TRNG_NS>; 1653 clock-names = "hclk_trng"; 1654 resets = <&cru SRST_HRESETN_TRNG_NS>; 1655 reset-names = "reset"; 1656 status = "disabled"; 1657 }; 1658 1659 otp: otp@ffce0000 { 1660 compatible = "rockchip,rk3528-otp"; 1661 reg = <0x0 0xffce0000 0x0 0x4000>; 1662 #address-cells = <1>; 1663 #size-cells = <1>; 1664 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, 1665 <&cru PCLK_OTPC_NS>; 1666 clock-names = "usr", "sbpi", "apb"; 1667 resets = <&cru SRST_RESETN_USER_OTPC_NS>, 1668 <&cru SRST_RESETN_SBPI_OTPC_NS>, 1669 <&cru SRST_PRESETN_OTPC_NS>; 1670 reset-names = "usr", "sbpi", "apb"; 1671 1672 /* Data cells */ 1673 cpu_code: cpu-code@2 { 1674 reg = <0x02 0x2>; 1675 }; 1676 otp_cpu_version: cpu-version@8 { 1677 reg = <0x08 0x1>; 1678 bits = <3 3>; 1679 }; 1680 otp_id: id@a { 1681 reg = <0x0a 0x10>; 1682 }; 1683 cpu_leakage: cpu-leakage@1a { 1684 reg = <0x1a 0x1>; 1685 }; 1686 log_leakage: log-leakage@1b { 1687 reg = <0x1b 0x1>; 1688 }; 1689 gpu_leakage: gpu-leakage@1c { 1690 reg = <0x1c 0x1>; 1691 }; 1692 }; 1693 1694 dmac: dma-controller@ffd60000 { 1695 compatible = "arm,pl330", "arm,primecell"; 1696 reg = <0x0 0xffd60000 0x0 0x4000>; 1697 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1706 clocks = <&xin24m>; 1707 clock-names = "apb_pclk"; 1708 #dma-cells = <1>; 1709 arm,pl330-periph-burst; 1710 }; 1711 1712 hwlock: hwspinlock@ffd70000 { 1713 compatible = "rockchip,hwspinlock"; 1714 reg = <0x0 0xffd70000 0x0 0x100>; 1715 #hwlock-cells = <1>; 1716 status = "disabled"; 1717 }; 1718 1719 combphy_pu: phy@ffdc0000 { 1720 compatible = "rockchip,rk3528-naneng-combphy"; 1721 reg = <0x0 0xffdc0000 0x0 0x10000>; 1722 #phy-cells = <1>; 1723 clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>, <&cru PCLK_PIPE_GRF>; 1724 clock-names = "refclk", "apbclk", "pipe_clk"; 1725 assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>; 1726 assigned-clock-rates = <100000000>; 1727 resets = <&cru SRST_PRESETN_PCIE_PHY>, <&cru SRST_RESETN_PCIE_PIPE_PHY>; 1728 reset-names = "combphy-apb", "combphy"; 1729 rockchip,pipe-grf = <&grf>; 1730 rockchip,pipe-phy-grf = <&grf>; 1731 status = "disabled"; 1732 }; 1733 1734 usb2phy: usb2-phy@ffdf0000 { 1735 compatible = "rockchip,rk3528-usb2phy"; 1736 reg = <0x0 0xffdf0000 0x0 0x10000>; 1737 clocks = <&cru CLK_REF_USBPHY>; 1738 clock-names = "phyclk"; 1739 #clock-cells = <0>; 1740 rockchip,usbgrf = <&grf>; 1741 status = "disabled"; 1742 1743 u2phy_otg: otg-port { 1744 #phy-cells = <0>; 1745 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1748 interrupt-names = "otg-bvalid", 1749 "otg-id", 1750 "linestate"; 1751 status = "disabled"; 1752 }; 1753 1754 u2phy_host: host-port { 1755 #phy-cells = <0>; 1756 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1757 interrupt-names = "linestate"; 1758 status = "disabled"; 1759 }; 1760 }; 1761 1762 hdmiphy: hdmiphy@ffe00000 { 1763 compatible = "rockchip,rk3528-hdmi-phy"; 1764 reg = <0x0 0xffe00000 0x0 0x10000>; 1765 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1766 #phy-cells = <0>; 1767 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>; 1768 clock-names = "sysclk", "refclk"; 1769 #clock-cells = <0>; 1770 clock-output-names = "clk_hdmiphy_pixel_io"; 1771 status = "disabled"; 1772 }; 1773 1774 pinctrl: pinctrl { 1775 compatible = "rockchip,rk3528-pinctrl"; 1776 rockchip,grf = <&ioc_grf>; 1777 #address-cells = <2>; 1778 #size-cells = <2>; 1779 ranges; 1780 1781 gpio0: gpio@ff610000 { 1782 compatible = "rockchip,gpio-bank"; 1783 reg = <0x0 0xff610000 0x0 0x200>; 1784 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1785 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 1786 gpio-controller; 1787 #gpio-cells = <2>; 1788 gpio-ranges = <&pinctrl 0 0 32>; 1789 interrupt-controller; 1790 #interrupt-cells = <2>; 1791 }; 1792 1793 gpio1: gpio@ffaf0000 { 1794 compatible = "rockchip,gpio-bank"; 1795 reg = <0x0 0xffaf0000 0x0 0x200>; 1796 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1797 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1798 gpio-controller; 1799 #gpio-cells = <2>; 1800 gpio-ranges = <&pinctrl 0 32 32>; 1801 interrupt-controller; 1802 #interrupt-cells = <2>; 1803 }; 1804 1805 gpio2: gpio@ffb00000 { 1806 compatible = "rockchip,gpio-bank"; 1807 reg = <0x0 0xffb00000 0x0 0x200>; 1808 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1809 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1810 gpio-controller; 1811 #gpio-cells = <2>; 1812 gpio-ranges = <&pinctrl 0 64 32>; 1813 interrupt-controller; 1814 #interrupt-cells = <2>; 1815 }; 1816 1817 gpio3: gpio@ffb10000 { 1818 compatible = "rockchip,gpio-bank"; 1819 reg = <0x0 0xffb10000 0x0 0x200>; 1820 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1821 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1822 gpio-controller; 1823 #gpio-cells = <2>; 1824 gpio-ranges = <&pinctrl 0 96 32>; 1825 interrupt-controller; 1826 #interrupt-cells = <2>; 1827 }; 1828 1829 gpio4: gpio@ffb20000 { 1830 compatible = "rockchip,gpio-bank"; 1831 reg = <0x0 0xffb20000 0x0 0x200>; 1832 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1833 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1834 gpio-controller; 1835 #gpio-cells = <2>; 1836 gpio-ranges = <&pinctrl 0 128 32>; 1837 interrupt-controller; 1838 #interrupt-cells = <2>; 1839 }; 1840 }; 1841}; 1842 1843#include "rk3528-pinctrl.dtsi" 1844