1/* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &sdhci; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor; 16 }; 17}; 18 19&grf { 20 u-boot,dm-spl; 21 status = "okay"; 22}; 23 24&ioc_grf { 25 u-boot,dm-spl; 26 status = "okay"; 27}; 28 29&cru { 30 u-boot,dm-spl; 31 status = "okay"; 32}; 33 34&crypto { 35 clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 36 clock-names = "sclk_crypto", "apkclk_crypto"; 37 clock-frequency = <200000000>, <300000000>; 38 u-boot,dm-spl; 39 status = "okay"; 40}; 41 42&rng { 43 u-boot,dm-pre-reloc; 44 status = "okay"; 45}; 46 47&psci { 48 u-boot,dm-pre-reloc; 49 status = "okay"; 50}; 51 52&uart2 { 53 clock-frequency = <24000000>; 54 u-boot,dm-spl; 55 status = "okay"; 56}; 57 58&sfc { 59 u-boot,dm-spl; 60 /delete-property/ pinctrl-names; 61 /delete-property/ pinctrl-0; 62 /delete-property/ assigned-clocks; 63 /delete-property/ assigned-clock-rates; 64 status = "okay"; 65 66 #address-cells = <1>; 67 #size-cells = <0>; 68 spi_nand: flash@0 { 69 u-boot,dm-spl; 70 compatible = "spi-nand"; 71 reg = <0>; 72 spi-tx-bus-width = <1>; 73 spi-rx-bus-width = <4>; 74 spi-max-frequency = <75000000>; 75 }; 76 77 spi_nor: flash@1 { 78 u-boot,dm-spl; 79 compatible = "jedec,spi-nor"; 80 label = "sfc_nor"; 81 reg = <0>; 82 spi-tx-bus-width = <1>; 83 spi-rx-bus-width = <4>; 84 spi-max-frequency = <100000000>; 85 }; 86}; 87 88&sdhci { 89 bus-width = <8>; 90 u-boot,dm-spl; 91 /delete-property/ pinctrl-names; 92 /delete-property/ pinctrl-0; 93 mmc-hs200-1_8v; 94 status = "okay"; 95}; 96 97&sdmmc { 98 u-boot,dm-spl; 99 status = "okay"; 100}; 101 102&saradc { 103 u-boot,dm-spl; 104 status = "okay"; 105}; 106 107&u2phy_otg { 108 u-boot,dm-pre-reloc; 109 status = "okay"; 110}; 111 112&usb2phy { 113 u-boot,dm-pre-reloc; 114 status = "okay"; 115}; 116