xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3528-u-boot.dtsi (revision 8268688cdfecc7ece36d7c13a37db7952ae37ecd) 
1/*
2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		mmc0 = &sdhci;
10		mmc1 = &sdmmc;
11	};
12
13	chosen {
14		stdout-path = &uart2;
15		u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor;
16	};
17};
18
19&grf {
20	u-boot,dm-spl;
21	status = "okay";
22};
23
24&rng {
25	u-boot,dm-spl;
26	status = "okay";
27};
28
29&ioc_grf {
30	u-boot,dm-spl;
31	status = "okay";
32};
33
34&cru {
35	u-boot,dm-spl;
36	status = "okay";
37};
38
39&crypto {
40	clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
41	clock-names = "sclk_crypto", "apkclk_crypto";
42	clock-frequency = <200000000>, <300000000>;
43	u-boot,dm-spl;
44	status = "okay";
45};
46
47&rng {
48	u-boot,dm-pre-reloc;
49	status = "okay";
50};
51
52&psci {
53	u-boot,dm-pre-reloc;
54	status = "okay";
55};
56
57&uart2 {
58	clock-frequency = <24000000>;
59	u-boot,dm-spl;
60	status = "okay";
61};
62
63&sfc {
64	u-boot,dm-spl;
65	/delete-property/ pinctrl-names;
66	/delete-property/ pinctrl-0;
67	/delete-property/ assigned-clocks;
68	/delete-property/ assigned-clock-rates;
69	status = "okay";
70
71	#address-cells = <1>;
72	#size-cells = <0>;
73	spi_nand: flash@0 {
74		u-boot,dm-spl;
75		compatible = "spi-nand";
76		reg = <0>;
77		spi-tx-bus-width = <1>;
78		spi-rx-bus-width = <4>;
79		spi-max-frequency = <75000000>;
80	};
81
82	spi_nor: flash@1 {
83		u-boot,dm-spl;
84		compatible = "jedec,spi-nor";
85		label = "sfc_nor";
86		reg = <0>;
87		spi-tx-bus-width = <1>;
88		spi-rx-bus-width = <4>;
89		spi-max-frequency = <100000000>;
90	};
91};
92
93&sdhci {
94	bus-width = <8>;
95	u-boot,dm-spl;
96	/delete-property/ pinctrl-names;
97	/delete-property/ pinctrl-0;
98	mmc-hs400-1_8v;
99	mmc-hs400-enhanced-strobe;
100	fixed-emmc-driver-type = <1>;
101	status = "okay";
102};
103
104&sdmmc {
105	u-boot,dm-spl;
106	status = "okay";
107};
108
109&saradc {
110	u-boot,dm-spl;
111	status = "okay";
112};
113
114&u2phy_otg {
115	u-boot,dm-pre-reloc;
116	status = "okay";
117};
118
119&usb2phy {
120	u-boot,dm-pre-reloc;
121	status = "okay";
122};
123
124&firmware {
125	u-boot,dm-pre-reloc;
126};
127
128&scmi {
129	u-boot,dm-pre-reloc;
130};
131
132&scmi_clk {
133	u-boot,dm-pre-reloc;
134};
135
136&scmi_shmem {
137	u-boot,dm-pre-reloc;
138};
139
140&pinctrl {
141	u-boot,dm-pre-reloc;
142	status = "okay";
143};
144
145&gpio0 {
146	u-boot,dm-spl;
147};
148
149&gpio1 {
150	u-boot,dm-spl;
151};
152
153&gpio2 {
154	u-boot,dm-pre-reloc;
155};
156
157&pcfg_pull_none_drv_level_1 {
158	u-boot,dm-pre-reloc;
159};
160
161&pcfg_pull_none_drv_level_2 {
162	u-boot,dm-pre-reloc;
163};
164
165&pcfg_pull_up_drv_level_1 {
166	u-boot,dm-spl;
167};
168
169&pcfg_pull_up_drv_level_2 {
170	u-boot,dm-spl;
171};
172
173&pcfg_pull_up {
174	u-boot,dm-spl;
175};
176
177&pcfg_pull_none {
178	u-boot,dm-pre-reloc;
179};
180
181&sdmmc_pins {
182	u-boot,dm-spl;
183};
184
185&sdmmc_bus4 {
186	u-boot,dm-spl;
187};
188
189&sdmmc_clk {
190	u-boot,dm-spl;
191};
192
193&sdmmc_cmd {
194	u-boot,dm-spl;
195};
196
197&sdmmc_det {
198	u-boot,dm-spl;
199};
200
201&sdmmc_pwren {
202	u-boot,dm-spl;
203};
204
205&secure_otp {
206	u-boot,dm-spl;
207	status = "okay";
208};
209