1/* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &sdhci; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor; 16 }; 17 18 secure-otp@ffcd0000 { 19 compatible = "rockchip,rk3528-secure-otp"; 20 reg = <0x0 0xffcd0000 0x0 0x4000>; 21 secure_conf = <0xff4500c0>; 22 mask_addr = <0x0>; 23 cru_rst_addr = <0xff4a8080>; 24 u-boot,dm-spl; 25 status = "okay"; 26 }; 27 28}; 29 30&grf { 31 u-boot,dm-spl; 32 status = "okay"; 33}; 34 35&ioc_grf { 36 u-boot,dm-spl; 37 status = "okay"; 38}; 39 40&cru { 41 u-boot,dm-spl; 42 status = "okay"; 43}; 44 45&crypto { 46 u-boot,dm-spl; 47 status = "okay"; 48}; 49 50&rng { 51 u-boot,dm-pre-reloc; 52 status = "okay"; 53}; 54 55&psci { 56 u-boot,dm-pre-reloc; 57 status = "okay"; 58}; 59 60&uart2 { 61 clock-frequency = <24000000>; 62 u-boot,dm-spl; 63 status = "okay"; 64}; 65 66&sfc { 67 u-boot,dm-spl; 68 /delete-property/ pinctrl-names; 69 /delete-property/ pinctrl-0; 70 /delete-property/ assigned-clocks; 71 /delete-property/ assigned-clock-rates; 72 status = "okay"; 73 74 #address-cells = <1>; 75 #size-cells = <0>; 76 spi_nand: flash@0 { 77 u-boot,dm-spl; 78 compatible = "spi-nand"; 79 reg = <0>; 80 spi-tx-bus-width = <1>; 81 spi-rx-bus-width = <4>; 82 spi-max-frequency = <75000000>; 83 }; 84 85 spi_nor: flash@1 { 86 u-boot,dm-spl; 87 compatible = "jedec,spi-nor"; 88 label = "sfc_nor"; 89 reg = <0>; 90 spi-tx-bus-width = <1>; 91 spi-rx-bus-width = <4>; 92 spi-max-frequency = <100000000>; 93 }; 94}; 95 96&sdhci { 97 bus-width = <8>; 98 u-boot,dm-spl; 99 /delete-property/ pinctrl-names; 100 /delete-property/ pinctrl-0; 101 mmc-hs400-1_8v; 102 mmc-hs400-enhanced-strobe; 103 fixed-emmc-driver-type = <1>; 104 status = "okay"; 105}; 106 107&sdmmc { 108 u-boot,dm-spl; 109 status = "okay"; 110}; 111 112&saradc { 113 u-boot,dm-pre-reloc; 114 status = "okay"; 115}; 116 117&u2phy_otg { 118 u-boot,dm-pre-reloc; 119 status = "okay"; 120}; 121 122&usb2phy { 123 u-boot,dm-pre-reloc; 124 status = "okay"; 125}; 126 127&firmware { 128 u-boot,dm-spl; 129}; 130 131&scmi { 132 u-boot,dm-spl; 133}; 134 135&scmi_clk { 136 u-boot,dm-spl; 137}; 138 139&scmi_shmem { 140 u-boot,dm-spl; 141}; 142 143&pinctrl { 144 u-boot,dm-spl; 145 status = "okay"; 146}; 147 148&gpio0 { 149 u-boot,dm-spl; 150}; 151 152&gpio1 { 153 u-boot,dm-spl; 154}; 155 156&gpio2 { 157 u-boot,dm-spl; 158}; 159 160&pcfg_pull_none_drv_level_1 { 161 u-boot,dm-spl; 162}; 163 164&pcfg_pull_none_drv_level_2 { 165 u-boot,dm-spl; 166}; 167 168&pcfg_pull_up_drv_level_1 { 169 u-boot,dm-spl; 170}; 171 172&pcfg_pull_up_drv_level_2 { 173 u-boot,dm-spl; 174}; 175 176&pcfg_pull_up { 177 u-boot,dm-spl; 178}; 179 180&pcfg_pull_none { 181 u-boot,dm-spl; 182}; 183 184&sdmmc_pins { 185 u-boot,dm-spl; 186}; 187 188&sdmmc_bus4 { 189 u-boot,dm-spl; 190}; 191 192&sdmmc_clk { 193 u-boot,dm-spl; 194}; 195 196&sdmmc_cmd { 197 u-boot,dm-spl; 198}; 199 200&sdmmc_det { 201 u-boot,dm-spl; 202}; 203