1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3399-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3399"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 serial3 = &uart3; 25 serial4 = &uart4; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu-map { 33 cluster0 { 34 core0 { 35 cpu = <&cpu_l0>; 36 }; 37 core1 { 38 cpu = <&cpu_l1>; 39 }; 40 core2 { 41 cpu = <&cpu_l2>; 42 }; 43 core3 { 44 cpu = <&cpu_l3>; 45 }; 46 }; 47 48 cluster1 { 49 core0 { 50 cpu = <&cpu_b0>; 51 }; 52 core1 { 53 cpu = <&cpu_b1>; 54 }; 55 }; 56 }; 57 58 cpu_l0: cpu@0 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53", "arm,armv8"; 61 reg = <0x0 0x0>; 62 enable-method = "psci"; 63 #cooling-cells = <2>; /* min followed by max */ 64 clocks = <&cru ARMCLKL>; 65 }; 66 67 cpu_l1: cpu@1 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53", "arm,armv8"; 70 reg = <0x0 0x1>; 71 enable-method = "psci"; 72 clocks = <&cru ARMCLKL>; 73 }; 74 75 cpu_l2: cpu@2 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53", "arm,armv8"; 78 reg = <0x0 0x2>; 79 enable-method = "psci"; 80 clocks = <&cru ARMCLKL>; 81 }; 82 83 cpu_l3: cpu@3 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a53", "arm,armv8"; 86 reg = <0x0 0x3>; 87 enable-method = "psci"; 88 clocks = <&cru ARMCLKL>; 89 }; 90 91 cpu_b0: cpu@100 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a72", "arm,armv8"; 94 reg = <0x0 0x100>; 95 enable-method = "psci"; 96 #cooling-cells = <2>; /* min followed by max */ 97 clocks = <&cru ARMCLKB>; 98 }; 99 100 cpu_b1: cpu@101 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a72", "arm,armv8"; 103 reg = <0x0 0x101>; 104 enable-method = "psci"; 105 clocks = <&cru ARMCLKB>; 106 }; 107 }; 108 109 psci { 110 compatible = "arm,psci-1.0"; 111 method = "smc"; 112 }; 113 114 timer { 115 compatible = "arm,armv8-timer"; 116 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 117 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 118 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 119 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 120 }; 121 122 xin24m: xin24m { 123 compatible = "fixed-clock"; 124 clock-frequency = <24000000>; 125 clock-output-names = "xin24m"; 126 #clock-cells = <0>; 127 }; 128 129 amba { 130 compatible = "simple-bus"; 131 #address-cells = <2>; 132 #size-cells = <2>; 133 ranges; 134 135 dmac_bus: dma-controller@ff6d0000 { 136 compatible = "arm,pl330", "arm,primecell"; 137 reg = <0x0 0xff6d0000 0x0 0x4000>; 138 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 140 #dma-cells = <1>; 141 clocks = <&cru ACLK_DMAC0_PERILP>; 142 clock-names = "apb_pclk"; 143 }; 144 145 dmac_peri: dma-controller@ff6e0000 { 146 compatible = "arm,pl330", "arm,primecell"; 147 reg = <0x0 0xff6e0000 0x0 0x4000>; 148 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 150 #dma-cells = <1>; 151 clocks = <&cru ACLK_DMAC1_PERILP>; 152 clock-names = "apb_pclk"; 153 }; 154 }; 155 156 sdio0: dwmmc@fe310000 { 157 compatible = "rockchip,rk3399-dw-mshc", 158 "rockchip,rk3288-dw-mshc"; 159 reg = <0x0 0xfe310000 0x0 0x4000>; 160 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 161 clock-freq-min-max = <400000 150000000>; 162 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 163 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 164 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 165 fifo-depth = <0x100>; 166 status = "disabled"; 167 }; 168 169 sdmmc: dwmmc@fe320000 { 170 compatible = "rockchip,rk3399-dw-mshc", 171 "rockchip,rk3288-dw-mshc"; 172 reg = <0x0 0xfe320000 0x0 0x4000>; 173 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 174 clock-freq-min-max = <400000 150000000>; 175 clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>, 176 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 177 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&sdmmc_clk>; 180 fifo-depth = <0x100>; 181 status = "disabled"; 182 }; 183 184 sdhci: sdhci@fe330000 { 185 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 186 reg = <0x0 0xfe330000 0x0 0x10000>; 187 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 188 assigned-clocks = <&cru SCLK_EMMC>; 189 assigned-clock-rates = <200000000>; 190 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 191 clock-names = "clk_xin", "clk_ahb"; 192 phys = <&emmc_phy>; 193 phy-names = "phy_arasan"; 194 status = "disabled"; 195 }; 196 197 usb_host0_ehci: usb@fe380000 { 198 compatible = "generic-ehci"; 199 reg = <0x0 0xfe380000 0x0 0x20000>; 200 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 201 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 202 clock-names = "hclk_host0", "hclk_host0_arb"; 203 status = "disabled"; 204 }; 205 206 usb_host0_ohci: usb@fe3a0000 { 207 compatible = "generic-ohci"; 208 reg = <0x0 0xfe3a0000 0x0 0x20000>; 209 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 211 clock-names = "hclk_host0", "hclk_host0_arb"; 212 status = "disabled"; 213 }; 214 215 usb_host1_ehci: usb@fe3c0000 { 216 compatible = "generic-ehci"; 217 reg = <0x0 0xfe3c0000 0x0 0x20000>; 218 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 220 clock-names = "hclk_host1", "hclk_host1_arb"; 221 status = "disabled"; 222 }; 223 224 usb_host1_ohci: usb@fe3e0000 { 225 compatible = "generic-ohci"; 226 reg = <0x0 0xfe3e0000 0x0 0x20000>; 227 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 229 clock-names = "hclk_host1", "hclk_host1_arb"; 230 status = "disabled"; 231 }; 232 233 gic: interrupt-controller@fee00000 { 234 compatible = "arm,gic-v3"; 235 #interrupt-cells = <3>; 236 #address-cells = <2>; 237 #size-cells = <2>; 238 ranges; 239 interrupt-controller; 240 241 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 242 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 243 <0x0 0xfff00000 0 0x10000>, /* GICC */ 244 <0x0 0xfff10000 0 0x10000>, /* GICH */ 245 <0x0 0xfff20000 0 0x10000>; /* GICV */ 246 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 247 its: interrupt-controller@fee20000 { 248 compatible = "arm,gic-v3-its"; 249 msi-controller; 250 reg = <0x0 0xfee20000 0x0 0x20000>; 251 }; 252 }; 253 254 uart0: serial@ff180000 { 255 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 256 reg = <0x0 0xff180000 0x0 0x100>; 257 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 258 clock-names = "baudclk", "apb_pclk"; 259 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 260 reg-shift = <2>; 261 reg-io-width = <4>; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&uart0_xfer>; 264 status = "disabled"; 265 }; 266 267 uart1: serial@ff190000 { 268 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 269 reg = <0x0 0xff190000 0x0 0x100>; 270 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 271 clock-names = "baudclk", "apb_pclk"; 272 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 273 reg-shift = <2>; 274 reg-io-width = <4>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&uart1_xfer>; 277 status = "disabled"; 278 }; 279 280 uart2: serial@ff1a0000 { 281 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 282 reg = <0x0 0xff1a0000 0x0 0x100>; 283 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 284 clock-names = "baudclk", "apb_pclk"; 285 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 286 clock-frequency = <24000000>; 287 reg-shift = <2>; 288 reg-io-width = <4>; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&uart2c_xfer>; 291 status = "disabled"; 292 }; 293 294 uart3: serial@ff1b0000 { 295 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 296 reg = <0x0 0xff1b0000 0x0 0x100>; 297 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 298 clock-names = "baudclk", "apb_pclk"; 299 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 300 reg-shift = <2>; 301 reg-io-width = <4>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&uart3_xfer>; 304 status = "disabled"; 305 }; 306 307 spi0: spi@ff1c0000 { 308 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 309 reg = <0x0 0xff1c0000 0x0 0x1000>; 310 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 311 clock-names = "spiclk", "apb_pclk"; 312 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 status = "disabled"; 318 }; 319 320 spi1: spi@ff1d0000 { 321 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 322 reg = <0x0 0xff1d0000 0x0 0x1000>; 323 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 324 clock-names = "spiclk", "apb_pclk"; 325 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 326 pinctrl-names = "default"; 327 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 status = "disabled"; 331 }; 332 333 spi2: spi@ff1e0000 { 334 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 335 reg = <0x0 0xff1e0000 0x0 0x1000>; 336 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 337 clock-names = "spiclk", "apb_pclk"; 338 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 status = "disabled"; 344 }; 345 346 spi4: spi@ff1f0000 { 347 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 348 reg = <0x0 0xff1f0000 0x0 0x1000>; 349 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 350 clock-names = "spiclk", "apb_pclk"; 351 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 status = "disabled"; 357 }; 358 359 spi5: spi@ff200000 { 360 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 361 reg = <0x0 0xff200000 0x0 0x1000>; 362 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 363 clock-names = "spiclk", "apb_pclk"; 364 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 365 pinctrl-names = "default"; 366 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 status = "disabled"; 370 }; 371 372 pmugrf: syscon@ff320000 { 373 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 374 reg = <0x0 0xff320000 0x0 0x1000>; 375 #address-cells = <1>; 376 #size-cells = <1>; 377 378 pmu_io_domains: io-domains { 379 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 380 status = "disabled"; 381 }; 382 }; 383 384 spi3: spi@ff350000 { 385 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 386 reg = <0x0 0xff350000 0x0 0x1000>; 387 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 388 clock-names = "spiclk", "apb_pclk"; 389 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 397 uart4: serial@ff370000 { 398 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 399 reg = <0x0 0xff370000 0x0 0x100>; 400 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 401 clock-names = "baudclk", "apb_pclk"; 402 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 403 reg-shift = <2>; 404 reg-io-width = <4>; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&uart4_xfer>; 407 status = "disabled"; 408 }; 409 410 pwm0: pwm@ff420000 { 411 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 412 reg = <0x0 0xff420000 0x0 0x10>; 413 #pwm-cells = <3>; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&pwm0_pin>; 416 clocks = <&pmucru PCLK_RKPWM_PMU>; 417 clock-names = "pwm"; 418 status = "disabled"; 419 }; 420 421 pwm1: pwm@ff420010 { 422 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 423 reg = <0x0 0xff420010 0x0 0x10>; 424 #pwm-cells = <3>; 425 pinctrl-names = "default"; 426 pinctrl-0 = <&pwm1_pin>; 427 clocks = <&pmucru PCLK_RKPWM_PMU>; 428 clock-names = "pwm"; 429 status = "disabled"; 430 }; 431 432 pwm2: pwm@ff420020 { 433 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 434 reg = <0x0 0xff420020 0x0 0x10>; 435 #pwm-cells = <3>; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&pwm2_pin>; 438 clocks = <&pmucru PCLK_RKPWM_PMU>; 439 clock-names = "pwm"; 440 status = "disabled"; 441 }; 442 443 pwm3: pwm@ff420030 { 444 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 445 reg = <0x0 0xff420030 0x0 0x10>; 446 #pwm-cells = <3>; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&pwm3a_pin>; 449 clocks = <&pmucru PCLK_RKPWM_PMU>; 450 clock-names = "pwm"; 451 status = "disabled"; 452 }; 453 454 pmucru: pmu-clock-controller@ff750000 { 455 compatible = "rockchip,rk3399-pmucru"; 456 reg = <0x0 0xff750000 0x0 0x1000>; 457 #clock-cells = <1>; 458 #reset-cells = <1>; 459 assigned-clocks = <&pmucru PLL_PPLL>; 460 assigned-clock-rates = <676000000>; 461 }; 462 463 cru: clock-controller@ff760000 { 464 compatible = "rockchip,rk3399-cru"; 465 reg = <0x0 0xff760000 0x0 0x1000>; 466 #clock-cells = <1>; 467 #reset-cells = <1>; 468 assigned-clocks = 469 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 470 <&cru PLL_NPLL>, 471 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 472 <&cru PCLK_PERIHP>, 473 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 474 <&cru PCLK_PERILP0>, 475 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 476 assigned-clock-rates = 477 <594000000>, <800000000>, 478 <1000000000>, 479 <150000000>, <75000000>, 480 <37500000>, 481 <100000000>, <100000000>, 482 <50000000>, 483 <100000000>, <50000000>; 484 }; 485 486 grf: syscon@ff770000 { 487 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 488 reg = <0x0 0xff770000 0x0 0x10000>; 489 #address-cells = <1>; 490 #size-cells = <1>; 491 492 io_domains: io-domains { 493 compatible = "rockchip,rk3399-io-voltage-domain"; 494 status = "disabled"; 495 }; 496 497 emmc_phy: phy@f780 { 498 compatible = "rockchip,rk3399-emmc-phy"; 499 reg = <0xf780 0x24>; 500 #phy-cells = <0>; 501 status = "disabled"; 502 }; 503 }; 504 505 watchdog@ff840000 { 506 compatible = "snps,dw-wdt"; 507 reg = <0x0 0xff840000 0x0 0x100>; 508 clocks = <&cru PCLK_WDT>; 509 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 510 }; 511 512 spdif: spdif@ff870000 { 513 compatible = "rockchip,rk3399-spdif"; 514 reg = <0x0 0xff870000 0x0 0x1000>; 515 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 516 dmas = <&dmac_bus 7>; 517 dma-names = "tx"; 518 clock-names = "mclk", "hclk"; 519 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&spdif_bus>; 522 status = "disabled"; 523 }; 524 525 i2s0: i2s@ff880000 { 526 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 527 reg = <0x0 0xff880000 0x0 0x1000>; 528 rockchip,grf = <&grf>; 529 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 530 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 531 dma-names = "tx", "rx"; 532 clock-names = "i2s_clk", "i2s_hclk"; 533 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&i2s0_8ch_bus>; 536 status = "disabled"; 537 }; 538 539 i2s1: i2s@ff890000 { 540 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 541 reg = <0x0 0xff890000 0x0 0x1000>; 542 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 543 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 544 dma-names = "tx", "rx"; 545 clock-names = "i2s_clk", "i2s_hclk"; 546 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&i2s1_2ch_bus>; 549 status = "disabled"; 550 }; 551 552 i2s2: i2s@ff8a0000 { 553 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 554 reg = <0x0 0xff8a0000 0x0 0x1000>; 555 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 556 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 557 dma-names = "tx", "rx"; 558 clock-names = "i2s_clk", "i2s_hclk"; 559 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 560 status = "disabled"; 561 }; 562 563 pinctrl: pinctrl { 564 compatible = "rockchip,rk3399-pinctrl"; 565 rockchip,grf = <&grf>; 566 rockchip,pmu = <&pmugrf>; 567 #address-cells = <2>; 568 #size-cells = <2>; 569 ranges; 570 571 gpio0: gpio0@ff720000 { 572 compatible = "rockchip,gpio-bank"; 573 reg = <0x0 0xff720000 0x0 0x100>; 574 clocks = <&pmucru PCLK_GPIO0_PMU>; 575 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 576 577 gpio-controller; 578 #gpio-cells = <0x2>; 579 580 interrupt-controller; 581 #interrupt-cells = <0x2>; 582 }; 583 584 gpio1: gpio1@ff730000 { 585 compatible = "rockchip,gpio-bank"; 586 reg = <0x0 0xff730000 0x0 0x100>; 587 clocks = <&pmucru PCLK_GPIO1_PMU>; 588 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 589 590 gpio-controller; 591 #gpio-cells = <0x2>; 592 593 interrupt-controller; 594 #interrupt-cells = <0x2>; 595 }; 596 597 gpio2: gpio2@ff780000 { 598 compatible = "rockchip,gpio-bank"; 599 reg = <0x0 0xff780000 0x0 0x100>; 600 clocks = <&cru PCLK_GPIO2>; 601 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 602 603 gpio-controller; 604 #gpio-cells = <0x2>; 605 606 interrupt-controller; 607 #interrupt-cells = <0x2>; 608 }; 609 610 gpio3: gpio3@ff788000 { 611 compatible = "rockchip,gpio-bank"; 612 reg = <0x0 0xff788000 0x0 0x100>; 613 clocks = <&cru PCLK_GPIO3>; 614 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 615 616 gpio-controller; 617 #gpio-cells = <0x2>; 618 619 interrupt-controller; 620 #interrupt-cells = <0x2>; 621 }; 622 623 gpio4: gpio4@ff790000 { 624 compatible = "rockchip,gpio-bank"; 625 reg = <0x0 0xff790000 0x0 0x100>; 626 clocks = <&cru PCLK_GPIO4>; 627 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 628 629 gpio-controller; 630 #gpio-cells = <0x2>; 631 632 interrupt-controller; 633 #interrupt-cells = <0x2>; 634 }; 635 636 pcfg_pull_up: pcfg-pull-up { 637 bias-pull-up; 638 }; 639 640 pcfg_pull_down: pcfg-pull-down { 641 bias-pull-down; 642 }; 643 644 pcfg_pull_none: pcfg-pull-none { 645 bias-disable; 646 }; 647 648 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 649 bias-disable; 650 drive-strength = <12>; 651 }; 652 653 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 654 bias-pull-up; 655 drive-strength = <8>; 656 }; 657 658 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 659 bias-pull-down; 660 drive-strength = <4>; 661 }; 662 663 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 664 bias-pull-up; 665 drive-strength = <2>; 666 }; 667 668 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 669 bias-pull-down; 670 drive-strength = <12>; 671 }; 672 673 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 674 bias-disable; 675 drive-strength = <13>; 676 }; 677 678 i2c0 { 679 i2c0_xfer: i2c0-xfer { 680 rockchip,pins = 681 <1 15 RK_FUNC_2 &pcfg_pull_none>, 682 <1 16 RK_FUNC_2 &pcfg_pull_none>; 683 }; 684 }; 685 686 i2c1 { 687 i2c1_xfer: i2c1-xfer { 688 rockchip,pins = 689 <4 2 RK_FUNC_1 &pcfg_pull_none>, 690 <4 1 RK_FUNC_1 &pcfg_pull_none>; 691 }; 692 }; 693 694 i2c2 { 695 i2c2_xfer: i2c2-xfer { 696 rockchip,pins = 697 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 698 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 699 }; 700 }; 701 702 i2c3 { 703 i2c3_xfer: i2c3-xfer { 704 rockchip,pins = 705 <4 17 RK_FUNC_1 &pcfg_pull_none>, 706 <4 16 RK_FUNC_1 &pcfg_pull_none>; 707 }; 708 }; 709 710 i2c4 { 711 i2c4_xfer: i2c4-xfer { 712 rockchip,pins = 713 <1 12 RK_FUNC_1 &pcfg_pull_none>, 714 <1 11 RK_FUNC_1 &pcfg_pull_none>; 715 }; 716 }; 717 718 i2c5 { 719 i2c5_xfer: i2c5-xfer { 720 rockchip,pins = 721 <3 11 RK_FUNC_2 &pcfg_pull_none>, 722 <3 10 RK_FUNC_2 &pcfg_pull_none>; 723 }; 724 }; 725 726 i2c6 { 727 i2c6_xfer: i2c6-xfer { 728 rockchip,pins = 729 <2 10 RK_FUNC_2 &pcfg_pull_none>, 730 <2 9 RK_FUNC_2 &pcfg_pull_none>; 731 }; 732 }; 733 734 i2c7 { 735 i2c7_xfer: i2c7-xfer { 736 rockchip,pins = 737 <2 8 RK_FUNC_2 &pcfg_pull_none>, 738 <2 7 RK_FUNC_2 &pcfg_pull_none>; 739 }; 740 }; 741 742 i2c8 { 743 i2c8_xfer: i2c8-xfer { 744 rockchip,pins = 745 <1 21 RK_FUNC_1 &pcfg_pull_none>, 746 <1 20 RK_FUNC_1 &pcfg_pull_none>; 747 }; 748 }; 749 750 i2s0 { 751 i2s0_8ch_bus: i2s0-8ch-bus { 752 rockchip,pins = 753 <3 24 RK_FUNC_1 &pcfg_pull_none>, 754 <3 25 RK_FUNC_1 &pcfg_pull_none>, 755 <3 26 RK_FUNC_1 &pcfg_pull_none>, 756 <3 27 RK_FUNC_1 &pcfg_pull_none>, 757 <3 28 RK_FUNC_1 &pcfg_pull_none>, 758 <3 29 RK_FUNC_1 &pcfg_pull_none>, 759 <3 30 RK_FUNC_1 &pcfg_pull_none>, 760 <3 31 RK_FUNC_1 &pcfg_pull_none>, 761 <4 0 RK_FUNC_1 &pcfg_pull_none>; 762 }; 763 }; 764 765 i2s1 { 766 i2s1_2ch_bus: i2s1-2ch-bus { 767 rockchip,pins = 768 <4 3 RK_FUNC_1 &pcfg_pull_none>, 769 <4 4 RK_FUNC_1 &pcfg_pull_none>, 770 <4 5 RK_FUNC_1 &pcfg_pull_none>, 771 <4 6 RK_FUNC_1 &pcfg_pull_none>, 772 <4 7 RK_FUNC_1 &pcfg_pull_none>; 773 }; 774 }; 775 776 sdmmc { 777 sdmmc_bus1: sdmmc-bus1 { 778 rockchip,pins = 779 <4 8 RK_FUNC_1 &pcfg_pull_up>; 780 }; 781 782 sdmmc_bus4: sdmmc-bus4 { 783 rockchip,pins = 784 <4 8 RK_FUNC_1 &pcfg_pull_up>, 785 <4 9 RK_FUNC_1 &pcfg_pull_up>, 786 <4 10 RK_FUNC_1 &pcfg_pull_up>, 787 <4 11 RK_FUNC_1 &pcfg_pull_up>; 788 }; 789 790 sdmmc_clk: sdmmc-clk { 791 rockchip,pins = 792 <4 12 RK_FUNC_1 &pcfg_pull_none>; 793 }; 794 795 sdmmc_cmd: sdmmc-cmd { 796 rockchip,pins = 797 <4 13 RK_FUNC_1 &pcfg_pull_up>; 798 }; 799 800 sdmmc_cd: sdmcc-cd { 801 rockchip,pins = 802 <0 7 RK_FUNC_1 &pcfg_pull_up>; 803 }; 804 805 sdmmc_wp: sdmmc-wp { 806 rockchip,pins = 807 <0 8 RK_FUNC_1 &pcfg_pull_up>; 808 }; 809 }; 810 811 spdif { 812 spdif_bus: spdif-bus { 813 rockchip,pins = 814 <4 21 RK_FUNC_1 &pcfg_pull_none>; 815 }; 816 }; 817 818 spi0 { 819 spi0_clk: spi0-clk { 820 rockchip,pins = 821 <3 6 RK_FUNC_2 &pcfg_pull_up>; 822 }; 823 spi0_cs0: spi0-cs0 { 824 rockchip,pins = 825 <3 7 RK_FUNC_2 &pcfg_pull_up>; 826 }; 827 spi0_cs1: spi0-cs1 { 828 rockchip,pins = 829 <3 8 RK_FUNC_2 &pcfg_pull_up>; 830 }; 831 spi0_tx: spi0-tx { 832 rockchip,pins = 833 <3 5 RK_FUNC_2 &pcfg_pull_up>; 834 }; 835 spi0_rx: spi0-rx { 836 rockchip,pins = 837 <3 4 RK_FUNC_2 &pcfg_pull_up>; 838 }; 839 }; 840 841 spi1 { 842 spi1_clk: spi1-clk { 843 rockchip,pins = 844 <1 9 RK_FUNC_2 &pcfg_pull_up>; 845 }; 846 spi1_cs0: spi1-cs0 { 847 rockchip,pins = 848 <1 10 RK_FUNC_2 &pcfg_pull_up>; 849 }; 850 spi1_rx: spi1-rx { 851 rockchip,pins = 852 <1 7 RK_FUNC_2 &pcfg_pull_up>; 853 }; 854 spi1_tx: spi1-tx { 855 rockchip,pins = 856 <1 8 RK_FUNC_2 &pcfg_pull_up>; 857 }; 858 }; 859 860 spi2 { 861 spi2_clk: spi2-clk { 862 rockchip,pins = 863 <2 11 RK_FUNC_1 &pcfg_pull_up>; 864 }; 865 spi2_cs0: spi2-cs0 { 866 rockchip,pins = 867 <2 12 RK_FUNC_1 &pcfg_pull_up>; 868 }; 869 spi2_rx: spi2-rx { 870 rockchip,pins = 871 <2 9 RK_FUNC_1 &pcfg_pull_up>; 872 }; 873 spi2_tx: spi2-tx { 874 rockchip,pins = 875 <2 10 RK_FUNC_1 &pcfg_pull_up>; 876 }; 877 }; 878 879 spi3 { 880 spi3_clk: spi3-clk { 881 rockchip,pins = 882 <1 17 RK_FUNC_1 &pcfg_pull_up>; 883 }; 884 spi3_cs0: spi3-cs0 { 885 rockchip,pins = 886 <1 18 RK_FUNC_1 &pcfg_pull_up>; 887 }; 888 spi3_rx: spi3-rx { 889 rockchip,pins = 890 <1 15 RK_FUNC_1 &pcfg_pull_up>; 891 }; 892 spi3_tx: spi3-tx { 893 rockchip,pins = 894 <1 16 RK_FUNC_1 &pcfg_pull_up>; 895 }; 896 }; 897 898 spi4 { 899 spi4_clk: spi4-clk { 900 rockchip,pins = 901 <3 2 RK_FUNC_2 &pcfg_pull_up>; 902 }; 903 spi4_cs0: spi4-cs0 { 904 rockchip,pins = 905 <3 3 RK_FUNC_2 &pcfg_pull_up>; 906 }; 907 spi4_rx: spi4-rx { 908 rockchip,pins = 909 <3 0 RK_FUNC_2 &pcfg_pull_up>; 910 }; 911 spi4_tx: spi4-tx { 912 rockchip,pins = 913 <3 1 RK_FUNC_2 &pcfg_pull_up>; 914 }; 915 }; 916 917 spi5 { 918 spi5_clk: spi5-clk { 919 rockchip,pins = 920 <2 22 RK_FUNC_2 &pcfg_pull_up>; 921 }; 922 spi5_cs0: spi5-cs0 { 923 rockchip,pins = 924 <2 23 RK_FUNC_2 &pcfg_pull_up>; 925 }; 926 spi5_rx: spi5-rx { 927 rockchip,pins = 928 <2 20 RK_FUNC_2 &pcfg_pull_up>; 929 }; 930 spi5_tx: spi5-tx { 931 rockchip,pins = 932 <2 21 RK_FUNC_2 &pcfg_pull_up>; 933 }; 934 }; 935 936 uart0 { 937 uart0_xfer: uart0-xfer { 938 rockchip,pins = 939 <2 16 RK_FUNC_1 &pcfg_pull_up>, 940 <2 17 RK_FUNC_1 &pcfg_pull_none>; 941 }; 942 943 uart0_cts: uart0-cts { 944 rockchip,pins = 945 <2 18 RK_FUNC_1 &pcfg_pull_none>; 946 }; 947 948 uart0_rts: uart0-rts { 949 rockchip,pins = 950 <2 19 RK_FUNC_1 &pcfg_pull_none>; 951 }; 952 }; 953 954 uart1 { 955 uart1_xfer: uart1-xfer { 956 rockchip,pins = 957 <3 12 RK_FUNC_2 &pcfg_pull_up>, 958 <3 13 RK_FUNC_2 &pcfg_pull_none>; 959 }; 960 }; 961 962 uart2a { 963 uart2a_xfer: uart2a-xfer { 964 rockchip,pins = 965 <4 8 RK_FUNC_2 &pcfg_pull_up>, 966 <4 9 RK_FUNC_2 &pcfg_pull_none>; 967 }; 968 }; 969 970 uart2b { 971 uart2b_xfer: uart2b-xfer { 972 rockchip,pins = 973 <4 16 RK_FUNC_2 &pcfg_pull_up>, 974 <4 17 RK_FUNC_2 &pcfg_pull_none>; 975 }; 976 }; 977 978 uart2c { 979 uart2c_xfer: uart2c-xfer { 980 rockchip,pins = 981 <4 19 RK_FUNC_1 &pcfg_pull_up>, 982 <4 20 RK_FUNC_1 &pcfg_pull_none>; 983 }; 984 }; 985 986 uart3 { 987 uart3_xfer: uart3-xfer { 988 rockchip,pins = 989 <3 14 RK_FUNC_2 &pcfg_pull_up>, 990 <3 15 RK_FUNC_2 &pcfg_pull_none>; 991 }; 992 993 uart3_cts: uart3-cts { 994 rockchip,pins = 995 <3 18 RK_FUNC_2 &pcfg_pull_none>; 996 }; 997 998 uart3_rts: uart3-rts { 999 rockchip,pins = 1000 <3 19 RK_FUNC_2 &pcfg_pull_none>; 1001 }; 1002 }; 1003 1004 uart4 { 1005 uart4_xfer: uart4-xfer { 1006 rockchip,pins = 1007 <1 7 RK_FUNC_1 &pcfg_pull_up>, 1008 <1 8 RK_FUNC_1 &pcfg_pull_none>; 1009 }; 1010 }; 1011 1012 uarthdcp { 1013 uarthdcp_xfer: uarthdcp-xfer { 1014 rockchip,pins = 1015 <4 21 RK_FUNC_2 &pcfg_pull_up>, 1016 <4 22 RK_FUNC_2 &pcfg_pull_none>; 1017 }; 1018 }; 1019 1020 pwm0 { 1021 pwm0_pin: pwm0-pin { 1022 rockchip,pins = 1023 <4 18 RK_FUNC_1 &pcfg_pull_none>; 1024 }; 1025 1026 vop0_pwm_pin: vop0-pwm-pin { 1027 rockchip,pins = 1028 <4 18 RK_FUNC_2 &pcfg_pull_none>; 1029 }; 1030 }; 1031 1032 pwm1 { 1033 pwm1_pin: pwm1-pin { 1034 rockchip,pins = 1035 <4 22 RK_FUNC_1 &pcfg_pull_none>; 1036 }; 1037 1038 vop1_pwm_pin: vop1-pwm-pin { 1039 rockchip,pins = 1040 <4 18 RK_FUNC_3 &pcfg_pull_none>; 1041 }; 1042 }; 1043 1044 pwm2 { 1045 pwm2_pin: pwm2-pin { 1046 rockchip,pins = 1047 <1 19 RK_FUNC_1 &pcfg_pull_none>; 1048 }; 1049 }; 1050 1051 pwm3a { 1052 pwm3a_pin: pwm3a-pin { 1053 rockchip,pins = 1054 <0 6 RK_FUNC_1 &pcfg_pull_none>; 1055 }; 1056 }; 1057 1058 pwm3b { 1059 pwm3b_pin: pwm3b-pin { 1060 rockchip,pins = 1061 <1 14 RK_FUNC_1 &pcfg_pull_none>; 1062 }; 1063 }; 1064 }; 1065}; 1066