1/* 2 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3399-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/rk3399-power.h> 13#include <dt-bindings/thermal/thermal.h> 14#define USB_CLASS_HUB 9 15 16/ { 17 compatible = "rockchip,rk3399"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 i2c8 = &i2c8; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 cpu-map { 45 cluster0 { 46 core0 { 47 cpu = <&cpu_l0>; 48 }; 49 core1 { 50 cpu = <&cpu_l1>; 51 }; 52 core2 { 53 cpu = <&cpu_l2>; 54 }; 55 core3 { 56 cpu = <&cpu_l3>; 57 }; 58 }; 59 60 cluster1 { 61 core0 { 62 cpu = <&cpu_b0>; 63 }; 64 core1 { 65 cpu = <&cpu_b1>; 66 }; 67 }; 68 }; 69 70 cpu_l0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53", "arm,armv8"; 73 reg = <0x0 0x0>; 74 enable-method = "psci"; 75 #cooling-cells = <2>; /* min followed by max */ 76 clocks = <&cru ARMCLKL>; 77 }; 78 79 cpu_l1: cpu@1 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 reg = <0x0 0x1>; 83 enable-method = "psci"; 84 clocks = <&cru ARMCLKL>; 85 }; 86 87 cpu_l2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53", "arm,armv8"; 90 reg = <0x0 0x2>; 91 enable-method = "psci"; 92 clocks = <&cru ARMCLKL>; 93 }; 94 95 cpu_l3: cpu@3 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a53", "arm,armv8"; 98 reg = <0x0 0x3>; 99 enable-method = "psci"; 100 clocks = <&cru ARMCLKL>; 101 }; 102 103 cpu_b0: cpu@100 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a72", "arm,armv8"; 106 reg = <0x0 0x100>; 107 enable-method = "psci"; 108 #cooling-cells = <2>; /* min followed by max */ 109 clocks = <&cru ARMCLKB>; 110 }; 111 112 cpu_b1: cpu@101 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a72", "arm,armv8"; 115 reg = <0x0 0x101>; 116 enable-method = "psci"; 117 clocks = <&cru ARMCLKB>; 118 }; 119 }; 120 121 display_subsystem: display-subsystem { 122 compatible = "rockchip,display-subsystem"; 123 ports = <&vopb_out>, <&vopl_out>; 124 status = "okay"; 125 126 route { 127 route_hdmi: route-hdmi { 128 status = "disabled"; 129 logo,uboot = "logo.bmp"; 130 logo,kernel = "logo_kernel.bmp"; 131 logo,mode = "center"; 132 charge_logo,mode = "center"; 133 connect = <&vopb_out_hdmi>; 134 }; 135 136 route_edp: route-edp { 137 status = "disabled"; 138 logo,uboot = "logo.bmp"; 139 logo,kernel = "logo_kernel.bmp"; 140 logo,mode = "center"; 141 charge_logo,mode = "center"; 142 connect = <&vopb_out_edp>; 143 }; 144 }; 145 }; 146 147 pmu_a53 { 148 compatible = "arm,cortex-a53-pmu"; 149 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 150 }; 151 152 pmu_a72 { 153 compatible = "arm,cortex-a72-pmu"; 154 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 155 }; 156 157 psci { 158 compatible = "arm,psci-1.0"; 159 method = "smc"; 160 }; 161 162 timer { 163 compatible = "arm,armv8-timer"; 164 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 165 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 166 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 167 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 168 arm,no-tick-in-suspend; 169 }; 170 171 xin24m: xin24m { 172 compatible = "fixed-clock"; 173 clock-frequency = <24000000>; 174 clock-output-names = "xin24m"; 175 #clock-cells = <0>; 176 }; 177 178 amba { 179 compatible = "simple-bus"; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 ranges; 183 184 dmac_bus: dma-controller@ff6d0000 { 185 compatible = "arm,pl330", "arm,primecell"; 186 reg = <0x0 0xff6d0000 0x0 0x4000>; 187 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 188 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 189 #dma-cells = <1>; 190 clocks = <&cru ACLK_DMAC0_PERILP>; 191 clock-names = "apb_pclk"; 192 }; 193 194 dmac_peri: dma-controller@ff6e0000 { 195 compatible = "arm,pl330", "arm,primecell"; 196 reg = <0x0 0xff6e0000 0x0 0x4000>; 197 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 198 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 199 #dma-cells = <1>; 200 clocks = <&cru ACLK_DMAC1_PERILP>; 201 clock-names = "apb_pclk"; 202 }; 203 }; 204 205 pcie0: pcie@f8000000 { 206 compatible = "rockchip,rk3399-pcie"; 207 reg = <0x0 0xf8000000 0x0 0x2000000>, 208 <0x0 0xfd000000 0x0 0x1000000>; 209 reg-names = "axi-base", "apb-base"; 210 #address-cells = <3>; 211 #size-cells = <2>; 212 #interrupt-cells = <1>; 213 aspm-no-l0s; 214 bus-range = <0x0 0x1>; 215 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 216 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 217 clock-names = "aclk", "aclk-perf", 218 "hclk", "pm"; 219 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 220 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 221 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 222 interrupt-names = "sys", "legacy", "client"; 223 interrupt-map-mask = <0 0 0 7>; 224 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 225 <0 0 0 2 &pcie0_intc 1>, 226 <0 0 0 3 &pcie0_intc 2>, 227 <0 0 0 4 &pcie0_intc 3>; 228 linux,pci-domain = <0>; 229 max-link-speed = <1>; 230 msi-map = <0x0 &its 0x0 0x1000>; 231 phys = <&pcie_phy>; 232 phy-names = "pcie-phy"; 233 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 234 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; 235 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 236 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 237 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 238 <&cru SRST_A_PCIE>; 239 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 240 "pm", "pclk", "aclk"; 241 status = "disabled"; 242 243 pcie0_intc: interrupt-controller { 244 interrupt-controller; 245 #address-cells = <0>; 246 #interrupt-cells = <1>; 247 }; 248 }; 249 250 gmac: ethernet@fe300000 { 251 compatible = "rockchip,rk3399-gmac"; 252 reg = <0x0 0xfe300000 0x0 0x10000>; 253 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 254 interrupt-names = "macirq"; 255 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 256 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 257 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 258 <&cru PCLK_GMAC>; 259 clock-names = "stmmaceth", "mac_clk_rx", 260 "mac_clk_tx", "clk_mac_ref", 261 "clk_mac_refout", "aclk_mac", 262 "pclk_mac"; 263 power-domains = <&power RK3399_PD_GMAC>; 264 resets = <&cru SRST_A_GMAC>; 265 reset-names = "stmmaceth"; 266 rockchip,grf = <&grf>; 267 status = "disabled"; 268 }; 269 270 sdio0: dwmmc@fe310000 { 271 compatible = "rockchip,rk3399-dw-mshc", 272 "rockchip,rk3288-dw-mshc"; 273 reg = <0x0 0xfe310000 0x0 0x4000>; 274 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 275 max-frequency = <150000000>; 276 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 277 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 278 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 279 fifo-depth = <0x100>; 280 power-domains = <&power RK3399_PD_SDIOAUDIO>; 281 resets = <&cru SRST_SDIO0>; 282 reset-names = "reset"; 283 status = "disabled"; 284 }; 285 286 sdmmc: dwmmc@fe320000 { 287 compatible = "rockchip,rk3399-dw-mshc", 288 "rockchip,rk3288-dw-mshc"; 289 reg = <0x0 0xfe320000 0x0 0x4000>; 290 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 291 max-frequency = <150000000>; 292 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 293 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 295 fifo-depth = <0x100>; 296 power-domains = <&power RK3399_PD_SD>; 297 resets = <&cru SRST_SDMMC>; 298 reset-names = "reset"; 299 status = "disabled"; 300 }; 301 302 sdhci: sdhci@fe330000 { 303 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 304 reg = <0x0 0xfe330000 0x0 0x10000>; 305 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 306 arasan,soc-ctl-syscon = <&grf>; 307 assigned-clocks = <&cru SCLK_EMMC>; 308 assigned-clock-rates = <200000000>; 309 max-frequency = <150000000>; 310 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 311 clock-names = "clk_xin", "clk_ahb"; 312 clock-output-names = "emmc_cardclock"; 313 #clock-cells = <0>; 314 phys = <&emmc_phy>; 315 phy-names = "phy_arasan"; 316 power-domains = <&power RK3399_PD_EMMC>; 317 status = "disabled"; 318 }; 319 320 usb_host0_ehci: usb@fe380000 { 321 compatible = "generic-ehci"; 322 reg = <0x0 0xfe380000 0x0 0x20000>; 323 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 324 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 325 <&u2phy0>; 326 clock-names = "usbhost", "arbiter", 327 "utmi"; 328 phys = <&u2phy0_host>; 329 phy-names = "usb"; 330 power-domains = <&power RK3399_PD_PERIHP>; 331 status = "disabled"; 332 }; 333 334 usb_host0_ohci: usb@fe3a0000 { 335 compatible = "generic-ohci"; 336 reg = <0x0 0xfe3a0000 0x0 0x20000>; 337 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 338 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 339 <&u2phy0>; 340 clock-names = "usbhost", "arbiter", 341 "utmi"; 342 phys = <&u2phy0_host>; 343 phy-names = "usb"; 344 power-domains = <&power RK3399_PD_PERIHP>; 345 status = "disabled"; 346 }; 347 348 usb_host1_ehci: usb@fe3c0000 { 349 compatible = "generic-ehci"; 350 reg = <0x0 0xfe3c0000 0x0 0x20000>; 351 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 352 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 353 <&u2phy1>; 354 clock-names = "usbhost", "arbiter", 355 "utmi"; 356 phys = <&u2phy1_host>; 357 phy-names = "usb"; 358 power-domains = <&power RK3399_PD_PERIHP>; 359 status = "disabled"; 360 }; 361 362 usb_host1_ohci: usb@fe3e0000 { 363 compatible = "generic-ohci"; 364 reg = <0x0 0xfe3e0000 0x0 0x20000>; 365 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 366 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 367 <&u2phy1>; 368 clock-names = "usbhost", "arbiter", 369 "utmi"; 370 phys = <&u2phy1_host>; 371 phy-names = "usb"; 372 power-domains = <&power RK3399_PD_PERIHP>; 373 status = "disabled"; 374 }; 375 376 dwc3_typec0: usb@fe800000 { 377 compatible = "rockchip,rk3399-xhci"; 378 reg = <0x0 0xfe800000 0x0 0x100000>; 379 status = "disabled"; 380 snps,dis-enblslpm-quirk; 381 snps,phyif-utmi-bits = <16>; 382 snps,dis-u2-freeclk-exists-quirk; 383 snps,dis-u2-susphy-quirk; 384 385 #address-cells = <2>; 386 #size-cells = <2>; 387 hub { 388 compatible = "usb-hub"; 389 usb,device-class = <USB_CLASS_HUB>; 390 }; 391 typec_phy0 { 392 compatible = "rockchip,rk3399-usb3-phy"; 393 reg = <0x0 0xff7c0000 0x0 0x40000>; 394 }; 395 }; 396 397 dwc3_typec1: usb@fe900000 { 398 compatible = "rockchip,rk3399-xhci"; 399 reg = <0x0 0xfe900000 0x0 0x100000>; 400 status = "disabled"; 401 snps,dis-enblslpm-quirk; 402 snps,phyif-utmi-bits = <16>; 403 snps,dis-u2-freeclk-exists-quirk; 404 snps,dis-u2-susphy-quirk; 405 406 #address-cells = <2>; 407 #size-cells = <2>; 408 hub { 409 compatible = "usb-hub"; 410 usb,device-class = <USB_CLASS_HUB>; 411 }; 412 typec_phy1 { 413 compatible = "rockchip,rk3399-usb3-phy"; 414 reg = <0x0 0xff800000 0x0 0x40000>; 415 }; 416 }; 417 418 gic: interrupt-controller@fee00000 { 419 compatible = "arm,gic-v3"; 420 #interrupt-cells = <4>; 421 #address-cells = <2>; 422 #size-cells = <2>; 423 ranges; 424 interrupt-controller; 425 426 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 427 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 428 <0x0 0xfff00000 0 0x10000>, /* GICC */ 429 <0x0 0xfff10000 0 0x10000>, /* GICH */ 430 <0x0 0xfff20000 0 0x10000>; /* GICV */ 431 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 432 its: interrupt-controller@fee20000 { 433 compatible = "arm,gic-v3-its"; 434 msi-controller; 435 reg = <0x0 0xfee20000 0x0 0x20000>; 436 }; 437 438 ppi-partitions { 439 ppi_cluster0: interrupt-partition-0 { 440 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 441 }; 442 443 ppi_cluster1: interrupt-partition-1 { 444 affinity = <&cpu_b0 &cpu_b1>; 445 }; 446 }; 447 }; 448 449 saradc: saradc@ff100000 { 450 compatible = "rockchip,rk3399-saradc"; 451 reg = <0x0 0xff100000 0x0 0x100>; 452 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 453 #io-channel-cells = <1>; 454 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 455 clock-names = "saradc", "apb_pclk"; 456 resets = <&cru SRST_P_SARADC>; 457 reset-names = "saradc-apb"; 458 status = "disabled"; 459 }; 460 461 i2c1: i2c@ff110000 { 462 compatible = "rockchip,rk3399-i2c"; 463 reg = <0x0 0xff110000 0x0 0x1000>; 464 assigned-clocks = <&cru SCLK_I2C1>; 465 assigned-clock-rates = <200000000>; 466 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 467 clock-names = "i2c", "pclk"; 468 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&i2c1_xfer>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 status = "disabled"; 474 }; 475 476 i2c2: i2c@ff120000 { 477 compatible = "rockchip,rk3399-i2c"; 478 reg = <0x0 0xff120000 0x0 0x1000>; 479 assigned-clocks = <&cru SCLK_I2C2>; 480 assigned-clock-rates = <200000000>; 481 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 482 clock-names = "i2c", "pclk"; 483 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&i2c2_xfer>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 status = "disabled"; 489 }; 490 491 i2c3: i2c@ff130000 { 492 compatible = "rockchip,rk3399-i2c"; 493 reg = <0x0 0xff130000 0x0 0x1000>; 494 assigned-clocks = <&cru SCLK_I2C3>; 495 assigned-clock-rates = <200000000>; 496 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 497 clock-names = "i2c", "pclk"; 498 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&i2c3_xfer>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 status = "disabled"; 504 }; 505 506 i2c5: i2c@ff140000 { 507 compatible = "rockchip,rk3399-i2c"; 508 reg = <0x0 0xff140000 0x0 0x1000>; 509 assigned-clocks = <&cru SCLK_I2C5>; 510 assigned-clock-rates = <200000000>; 511 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 512 clock-names = "i2c", "pclk"; 513 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&i2c5_xfer>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 status = "disabled"; 519 }; 520 521 i2c6: i2c@ff150000 { 522 compatible = "rockchip,rk3399-i2c"; 523 reg = <0x0 0xff150000 0x0 0x1000>; 524 assigned-clocks = <&cru SCLK_I2C6>; 525 assigned-clock-rates = <200000000>; 526 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 527 clock-names = "i2c", "pclk"; 528 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 529 pinctrl-names = "default"; 530 pinctrl-0 = <&i2c6_xfer>; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 status = "disabled"; 534 }; 535 536 i2c7: i2c@ff160000 { 537 compatible = "rockchip,rk3399-i2c"; 538 reg = <0x0 0xff160000 0x0 0x1000>; 539 assigned-clocks = <&cru SCLK_I2C7>; 540 assigned-clock-rates = <200000000>; 541 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 542 clock-names = "i2c", "pclk"; 543 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&i2c7_xfer>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 status = "disabled"; 549 }; 550 551 uart0: serial@ff180000 { 552 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 553 reg = <0x0 0xff180000 0x0 0x100>; 554 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 555 clock-names = "baudclk", "apb_pclk"; 556 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 557 reg-shift = <2>; 558 reg-io-width = <4>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&uart0_xfer>; 561 status = "disabled"; 562 }; 563 564 uart1: serial@ff190000 { 565 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 566 reg = <0x0 0xff190000 0x0 0x100>; 567 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 568 clock-names = "baudclk", "apb_pclk"; 569 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 570 reg-shift = <2>; 571 reg-io-width = <4>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&uart1_xfer>; 574 status = "disabled"; 575 }; 576 577 uart2: serial@ff1a0000 { 578 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 579 reg = <0x0 0xff1a0000 0x0 0x100>; 580 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 581 clock-names = "baudclk", "apb_pclk"; 582 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 583 clock-frequency = <24000000>; 584 reg-shift = <2>; 585 reg-io-width = <4>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&uart2c_xfer>; 588 status = "disabled"; 589 }; 590 591 uart3: serial@ff1b0000 { 592 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 593 reg = <0x0 0xff1b0000 0x0 0x100>; 594 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 595 clock-names = "baudclk", "apb_pclk"; 596 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 597 reg-shift = <2>; 598 reg-io-width = <4>; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&uart3_xfer>; 601 status = "disabled"; 602 }; 603 604 spi0: spi@ff1c0000 { 605 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 606 reg = <0x0 0xff1c0000 0x0 0x1000>; 607 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 608 clock-names = "spiclk", "apb_pclk"; 609 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 status = "disabled"; 615 }; 616 617 spi1: spi@ff1d0000 { 618 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 619 reg = <0x0 0xff1d0000 0x0 0x1000>; 620 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 621 clock-names = "spiclk", "apb_pclk"; 622 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 status = "disabled"; 628 }; 629 630 spi2: spi@ff1e0000 { 631 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 632 reg = <0x0 0xff1e0000 0x0 0x1000>; 633 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 634 clock-names = "spiclk", "apb_pclk"; 635 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 636 pinctrl-names = "default"; 637 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 status = "disabled"; 641 }; 642 643 spi4: spi@ff1f0000 { 644 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 645 reg = <0x0 0xff1f0000 0x0 0x1000>; 646 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 647 clock-names = "spiclk", "apb_pclk"; 648 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 649 pinctrl-names = "default"; 650 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 status = "disabled"; 654 }; 655 656 spi5: spi@ff200000 { 657 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 658 reg = <0x0 0xff200000 0x0 0x1000>; 659 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 660 clock-names = "spiclk", "apb_pclk"; 661 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 662 pinctrl-names = "default"; 663 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 status = "disabled"; 667 }; 668 669 thermal_zones: thermal-zones { 670 cpu_thermal: cpu { 671 polling-delay-passive = <100>; 672 polling-delay = <1000>; 673 674 thermal-sensors = <&tsadc 0>; 675 676 trips { 677 cpu_alert0: cpu_alert0 { 678 temperature = <70000>; 679 hysteresis = <2000>; 680 type = "passive"; 681 }; 682 cpu_alert1: cpu_alert1 { 683 temperature = <75000>; 684 hysteresis = <2000>; 685 type = "passive"; 686 }; 687 cpu_crit: cpu_crit { 688 temperature = <95000>; 689 hysteresis = <2000>; 690 type = "critical"; 691 }; 692 }; 693 694 cooling-maps { 695 map0 { 696 trip = <&cpu_alert0>; 697 cooling-device = 698 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 699 }; 700 map1 { 701 trip = <&cpu_alert1>; 702 cooling-device = 703 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 704 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 705 }; 706 }; 707 }; 708 709 gpu_thermal: gpu { 710 polling-delay-passive = <100>; 711 polling-delay = <1000>; 712 713 thermal-sensors = <&tsadc 1>; 714 715 trips { 716 gpu_alert0: gpu_alert0 { 717 temperature = <75000>; 718 hysteresis = <2000>; 719 type = "passive"; 720 }; 721 gpu_crit: gpu_crit { 722 temperature = <95000>; 723 hysteresis = <2000>; 724 type = "critical"; 725 }; 726 }; 727 728 cooling-maps { 729 map0 { 730 trip = <&gpu_alert0>; 731 cooling-device = 732 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 733 }; 734 }; 735 }; 736 }; 737 738 tsadc: tsadc@ff260000 { 739 compatible = "rockchip,rk3399-tsadc"; 740 reg = <0x0 0xff260000 0x0 0x100>; 741 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 742 assigned-clocks = <&cru SCLK_TSADC>; 743 assigned-clock-rates = <750000>; 744 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 745 clock-names = "tsadc", "apb_pclk"; 746 resets = <&cru SRST_TSADC>; 747 reset-names = "tsadc-apb"; 748 rockchip,grf = <&grf>; 749 rockchip,hw-tshut-temp = <95000>; 750 pinctrl-names = "init", "default", "sleep"; 751 pinctrl-0 = <&otp_gpio>; 752 pinctrl-1 = <&otp_out>; 753 pinctrl-2 = <&otp_gpio>; 754 #thermal-sensor-cells = <1>; 755 status = "disabled"; 756 }; 757 758 qos_emmc: qos@ffa58000 { 759 compatible = "syscon"; 760 reg = <0x0 0xffa58000 0x0 0x20>; 761 }; 762 763 qos_gmac: qos@ffa5c000 { 764 compatible = "syscon"; 765 reg = <0x0 0xffa5c000 0x0 0x20>; 766 }; 767 768 qos_pcie: qos@ffa60080 { 769 compatible = "syscon"; 770 reg = <0x0 0xffa60080 0x0 0x20>; 771 }; 772 773 qos_usb_host0: qos@ffa60100 { 774 compatible = "syscon"; 775 reg = <0x0 0xffa60100 0x0 0x20>; 776 }; 777 778 qos_usb_host1: qos@ffa60180 { 779 compatible = "syscon"; 780 reg = <0x0 0xffa60180 0x0 0x20>; 781 }; 782 783 qos_usb_otg0: qos@ffa70000 { 784 compatible = "syscon"; 785 reg = <0x0 0xffa70000 0x0 0x20>; 786 }; 787 788 qos_usb_otg1: qos@ffa70080 { 789 compatible = "syscon"; 790 reg = <0x0 0xffa70080 0x0 0x20>; 791 }; 792 793 qos_sd: qos@ffa74000 { 794 compatible = "syscon"; 795 reg = <0x0 0xffa74000 0x0 0x20>; 796 }; 797 798 qos_sdioaudio: qos@ffa76000 { 799 compatible = "syscon"; 800 reg = <0x0 0xffa76000 0x0 0x20>; 801 }; 802 803 qos_hdcp: qos@ffa90000 { 804 compatible = "syscon"; 805 reg = <0x0 0xffa90000 0x0 0x20>; 806 }; 807 808 qos_iep: qos@ffa98000 { 809 compatible = "syscon"; 810 reg = <0x0 0xffa98000 0x0 0x20>; 811 }; 812 813 qos_isp0_m0: qos@ffaa0000 { 814 compatible = "syscon"; 815 reg = <0x0 0xffaa0000 0x0 0x20>; 816 }; 817 818 qos_isp0_m1: qos@ffaa0080 { 819 compatible = "syscon"; 820 reg = <0x0 0xffaa0080 0x0 0x20>; 821 }; 822 823 qos_isp1_m0: qos@ffaa8000 { 824 compatible = "syscon"; 825 reg = <0x0 0xffaa8000 0x0 0x20>; 826 }; 827 828 qos_isp1_m1: qos@ffaa8080 { 829 compatible = "syscon"; 830 reg = <0x0 0xffaa8080 0x0 0x20>; 831 }; 832 833 qos_rga_r: qos@ffab0000 { 834 compatible = "syscon"; 835 reg = <0x0 0xffab0000 0x0 0x20>; 836 }; 837 838 qos_rga_w: qos@ffab0080 { 839 compatible = "syscon"; 840 reg = <0x0 0xffab0080 0x0 0x20>; 841 }; 842 843 qos_video_m0: qos@ffab8000 { 844 compatible = "syscon"; 845 reg = <0x0 0xffab8000 0x0 0x20>; 846 }; 847 848 qos_video_m1_r: qos@ffac0000 { 849 compatible = "syscon"; 850 reg = <0x0 0xffac0000 0x0 0x20>; 851 }; 852 853 qos_video_m1_w: qos@ffac0080 { 854 compatible = "syscon"; 855 reg = <0x0 0xffac0080 0x0 0x20>; 856 }; 857 858 qos_vop_big_r: qos@ffac8000 { 859 compatible = "syscon"; 860 reg = <0x0 0xffac8000 0x0 0x20>; 861 }; 862 863 qos_vop_big_w: qos@ffac8080 { 864 compatible = "syscon"; 865 reg = <0x0 0xffac8080 0x0 0x20>; 866 }; 867 868 qos_vop_little: qos@ffad0000 { 869 compatible = "syscon"; 870 reg = <0x0 0xffad0000 0x0 0x20>; 871 }; 872 873 qos_perihp: qos@ffad8080 { 874 compatible = "syscon"; 875 reg = <0x0 0xffad8080 0x0 0x20>; 876 }; 877 878 qos_gpu: qos@ffae0000 { 879 compatible = "syscon"; 880 reg = <0x0 0xffae0000 0x0 0x20>; 881 }; 882 883 pmu: power-management@ff310000 { 884 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 885 reg = <0x0 0xff310000 0x0 0x1000>; 886 887 /* 888 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 889 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 890 * Some of the power domains are grouped together for every 891 * voltage domain. 892 * The detail contents as below. 893 */ 894 power: power-controller { 895 compatible = "rockchip,rk3399-power-controller"; 896 #power-domain-cells = <1>; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 900 /* These power domains are grouped by VD_CENTER */ 901 pd_iep@RK3399_PD_IEP { 902 reg = <RK3399_PD_IEP>; 903 clocks = <&cru ACLK_IEP>, 904 <&cru HCLK_IEP>; 905 pm_qos = <&qos_iep>; 906 }; 907 pd_rga@RK3399_PD_RGA { 908 reg = <RK3399_PD_RGA>; 909 clocks = <&cru ACLK_RGA>, 910 <&cru HCLK_RGA>; 911 pm_qos = <&qos_rga_r>, 912 <&qos_rga_w>; 913 }; 914 pd_vcodec@RK3399_PD_VCODEC { 915 reg = <RK3399_PD_VCODEC>; 916 clocks = <&cru ACLK_VCODEC>, 917 <&cru HCLK_VCODEC>; 918 pm_qos = <&qos_video_m0>; 919 }; 920 pd_vdu@RK3399_PD_VDU { 921 reg = <RK3399_PD_VDU>; 922 clocks = <&cru ACLK_VDU>, 923 <&cru HCLK_VDU>; 924 pm_qos = <&qos_video_m1_r>, 925 <&qos_video_m1_w>; 926 }; 927 928 /* These power domains are grouped by VD_GPU */ 929 pd_gpu@RK3399_PD_GPU { 930 reg = <RK3399_PD_GPU>; 931 clocks = <&cru ACLK_GPU>; 932 pm_qos = <&qos_gpu>; 933 }; 934 935 /* These power domains are grouped by VD_LOGIC */ 936 pd_edp@RK3399_PD_EDP { 937 reg = <RK3399_PD_EDP>; 938 clocks = <&cru PCLK_EDP_CTRL>; 939 }; 940 pd_emmc@RK3399_PD_EMMC { 941 reg = <RK3399_PD_EMMC>; 942 clocks = <&cru ACLK_EMMC>; 943 pm_qos = <&qos_emmc>; 944 }; 945 pd_gmac@RK3399_PD_GMAC { 946 reg = <RK3399_PD_GMAC>; 947 clocks = <&cru ACLK_GMAC>, 948 <&cru PCLK_GMAC>; 949 pm_qos = <&qos_gmac>; 950 }; 951 pd_perihp@RK3399_PD_PERIHP { 952 reg = <RK3399_PD_PERIHP>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 clocks = <&cru ACLK_PERIHP>; 956 pm_qos = <&qos_perihp>, 957 <&qos_pcie>, 958 <&qos_usb_host0>, 959 <&qos_usb_host1>; 960 961 pd_sd@RK3399_PD_SD { 962 reg = <RK3399_PD_SD>; 963 clocks = <&cru HCLK_SDMMC>, 964 <&cru SCLK_SDMMC>; 965 pm_qos = <&qos_sd>; 966 }; 967 }; 968 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 969 reg = <RK3399_PD_SDIOAUDIO>; 970 clocks = <&cru HCLK_SDIO>; 971 pm_qos = <&qos_sdioaudio>; 972 }; 973 pd_usb3@RK3399_PD_USB3 { 974 reg = <RK3399_PD_USB3>; 975 clocks = <&cru ACLK_USB3>; 976 pm_qos = <&qos_usb_otg0>, 977 <&qos_usb_otg1>; 978 }; 979 pd_vio@RK3399_PD_VIO { 980 reg = <RK3399_PD_VIO>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 984 pd_hdcp@RK3399_PD_HDCP { 985 reg = <RK3399_PD_HDCP>; 986 clocks = <&cru ACLK_HDCP>, 987 <&cru HCLK_HDCP>, 988 <&cru PCLK_HDCP>; 989 pm_qos = <&qos_hdcp>; 990 }; 991 pd_isp0@RK3399_PD_ISP0 { 992 reg = <RK3399_PD_ISP0>; 993 clocks = <&cru ACLK_ISP0>, 994 <&cru HCLK_ISP0>; 995 pm_qos = <&qos_isp0_m0>, 996 <&qos_isp0_m1>; 997 }; 998 pd_isp1@RK3399_PD_ISP1 { 999 reg = <RK3399_PD_ISP1>; 1000 clocks = <&cru ACLK_ISP1>, 1001 <&cru HCLK_ISP1>; 1002 pm_qos = <&qos_isp1_m0>, 1003 <&qos_isp1_m1>; 1004 }; 1005 pd_tcpc0@RK3399_PD_TCPC0 { 1006 reg = <RK3399_PD_TCPD0>; 1007 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1008 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1009 }; 1010 pd_tcpc1@RK3399_PD_TCPC1 { 1011 reg = <RK3399_PD_TCPD1>; 1012 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1013 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1014 }; 1015 pd_vo@RK3399_PD_VO { 1016 reg = <RK3399_PD_VO>; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 1020 pd_vopb@RK3399_PD_VOPB { 1021 reg = <RK3399_PD_VOPB>; 1022 clocks = <&cru ACLK_VOP0>, 1023 <&cru HCLK_VOP0>; 1024 pm_qos = <&qos_vop_big_r>, 1025 <&qos_vop_big_w>; 1026 }; 1027 pd_vopl@RK3399_PD_VOPL { 1028 reg = <RK3399_PD_VOPL>; 1029 clocks = <&cru ACLK_VOP1>, 1030 <&cru HCLK_VOP1>; 1031 pm_qos = <&qos_vop_little>; 1032 }; 1033 }; 1034 }; 1035 }; 1036 }; 1037 1038 pmugrf: syscon@ff320000 { 1039 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1040 reg = <0x0 0xff320000 0x0 0x1000>; 1041 #address-cells = <1>; 1042 #size-cells = <1>; 1043 1044 pmu_io_domains: io-domains { 1045 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1046 status = "disabled"; 1047 }; 1048 }; 1049 1050 pmusgrf: syscon@ff330000 { 1051 compatible = "rockchip,rk3399-pmusgrf", "syscon"; 1052 reg = <0x0 0xff330000 0x0 0xe3d4>; 1053 }; 1054 1055 spi3: spi@ff350000 { 1056 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1057 reg = <0x0 0xff350000 0x0 0x1000>; 1058 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1059 clock-names = "spiclk", "apb_pclk"; 1060 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 status = "disabled"; 1066 }; 1067 1068 uart4: serial@ff370000 { 1069 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1070 reg = <0x0 0xff370000 0x0 0x100>; 1071 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1072 clock-names = "baudclk", "apb_pclk"; 1073 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1074 reg-shift = <2>; 1075 reg-io-width = <4>; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&uart4_xfer>; 1078 status = "disabled"; 1079 }; 1080 1081 i2c4: i2c@ff3d0000 { 1082 compatible = "rockchip,rk3399-i2c"; 1083 reg = <0x0 0xff3d0000 0x0 0x1000>; 1084 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1085 assigned-clock-rates = <200000000>; 1086 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1087 clock-names = "i2c", "pclk"; 1088 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&i2c4_xfer>; 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 status = "disabled"; 1094 }; 1095 1096 i2c8: i2c@ff3e0000 { 1097 compatible = "rockchip,rk3399-i2c"; 1098 reg = <0x0 0xff3e0000 0x0 0x1000>; 1099 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1100 assigned-clock-rates = <200000000>; 1101 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1102 clock-names = "i2c", "pclk"; 1103 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&i2c8_xfer>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 pwm0: pwm@ff420000 { 1112 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1113 reg = <0x0 0xff420000 0x0 0x10>; 1114 #pwm-cells = <3>; 1115 pinctrl-names = "active"; 1116 pinctrl-0 = <&pwm0_pin>; 1117 clocks = <&pmucru PCLK_RKPWM_PMU>; 1118 clock-names = "pwm"; 1119 status = "disabled"; 1120 }; 1121 1122 pwm1: pwm@ff420010 { 1123 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1124 reg = <0x0 0xff420010 0x0 0x10>; 1125 #pwm-cells = <3>; 1126 pinctrl-names = "active"; 1127 pinctrl-0 = <&pwm1_pin>; 1128 clocks = <&pmucru PCLK_RKPWM_PMU>; 1129 clock-names = "pwm"; 1130 status = "disabled"; 1131 }; 1132 1133 pwm2: pwm@ff420020 { 1134 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1135 reg = <0x0 0xff420020 0x0 0x10>; 1136 #pwm-cells = <3>; 1137 pinctrl-names = "active"; 1138 pinctrl-0 = <&pwm2_pin>; 1139 clocks = <&pmucru PCLK_RKPWM_PMU>; 1140 clock-names = "pwm"; 1141 status = "disabled"; 1142 }; 1143 1144 pwm3: pwm@ff420030 { 1145 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1146 reg = <0x0 0xff420030 0x0 0x10>; 1147 #pwm-cells = <3>; 1148 pinctrl-names = "active"; 1149 pinctrl-0 = <&pwm3a_pin>; 1150 clocks = <&pmucru PCLK_RKPWM_PMU>; 1151 clock-names = "pwm"; 1152 status = "disabled"; 1153 }; 1154 1155 cic: syscon@ff620000 { 1156 compatible = "rockchip,rk3399-cic", "syscon"; 1157 reg = <0x0 0xff620000 0x0 0x100>; 1158 }; 1159 1160 dfi: dfi@ff630000 { 1161 reg = <0x00 0xff630000 0x00 0x4000>; 1162 compatible = "rockchip,rk3399-dfi"; 1163 rockchip,pmu = <&pmugrf>; 1164 clocks = <&cru PCLK_DDR_MON>; 1165 clock-names = "pclk_ddr_mon"; 1166 status = "disabled"; 1167 }; 1168 1169 dmc: dmc { 1170 compatible = "rockchip,rk3399-dmc"; 1171 devfreq-events = <&dfi>; 1172 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; 1173 clocks = <&cru SCLK_DDRCLK>; 1174 clock-names = "dmc_clk"; 1175 reg = <0x0 0xffa80000 0x0 0x0800 1176 0x0 0xffa80800 0x0 0x1800 1177 0x0 0xffa82000 0x0 0x2000 1178 0x0 0xffa84000 0x0 0x1000 1179 0x0 0xffa88000 0x0 0x0800 1180 0x0 0xffa88800 0x0 0x1800 1181 0x0 0xffa8a000 0x0 0x2000 1182 0x0 0xffa8c000 0x0 0x1000>; 1183 }; 1184 1185 efuse0: efuse@ff690000 { 1186 compatible = "rockchip,rk3399-efuse"; 1187 reg = <0x0 0xff690000 0x0 0x80>; 1188 #address-cells = <1>; 1189 #size-cells = <1>; 1190 clocks = <&cru PCLK_EFUSE1024NS>; 1191 clock-names = "pclk_efuse"; 1192 1193 /* Data cells */ 1194 cpu_id: cpu-id@7 { 1195 reg = <0x07 0x10>; 1196 }; 1197 cpub_leakage: cpu-leakage@17 { 1198 reg = <0x17 0x1>; 1199 }; 1200 gpu_leakage: gpu-leakage@18 { 1201 reg = <0x18 0x1>; 1202 }; 1203 center_leakage: center-leakage@19 { 1204 reg = <0x19 0x1>; 1205 }; 1206 cpul_leakage: cpu-leakage@1a { 1207 reg = <0x1a 0x1>; 1208 }; 1209 logic_leakage: logic-leakage@1b { 1210 reg = <0x1b 0x1>; 1211 }; 1212 wafer_info: wafer-info@1c { 1213 reg = <0x1c 0x1>; 1214 }; 1215 }; 1216 1217 pmucru: pmu-clock-controller@ff750000 { 1218 compatible = "rockchip,rk3399-pmucru"; 1219 reg = <0x0 0xff750000 0x0 0x1000>; 1220 rockchip,grf = <&pmugrf>; 1221 #clock-cells = <1>; 1222 #reset-cells = <1>; 1223 assigned-clocks = <&pmucru PLL_PPLL>; 1224 assigned-clock-rates = <676000000>; 1225 }; 1226 1227 cru: clock-controller@ff760000 { 1228 compatible = "rockchip,rk3399-cru"; 1229 reg = <0x0 0xff760000 0x0 0x1000>; 1230 rockchip,grf = <&grf>; 1231 #clock-cells = <1>; 1232 #reset-cells = <1>; 1233 assigned-clocks = 1234 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1235 <&cru PLL_NPLL>, 1236 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1237 <&cru PCLK_PERIHP>, 1238 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1239 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1240 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1241 assigned-clock-rates = 1242 <594000000>, <800000000>, 1243 <1000000000>, 1244 <150000000>, <75000000>, 1245 <37500000>, 1246 <100000000>, <100000000>, 1247 <50000000>, <600000000>, 1248 <100000000>, <50000000>; 1249 }; 1250 1251 grf: syscon@ff770000 { 1252 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1253 reg = <0x0 0xff770000 0x0 0x10000>; 1254 #address-cells = <1>; 1255 #size-cells = <1>; 1256 1257 io_domains: io-domains { 1258 compatible = "rockchip,rk3399-io-voltage-domain"; 1259 status = "disabled"; 1260 }; 1261 1262 u2phy0: usb2-phy@e450 { 1263 compatible = "rockchip,rk3399-usb2phy"; 1264 reg = <0xe450 0x10>; 1265 clocks = <&cru SCLK_USB2PHY0_REF>; 1266 clock-names = "phyclk"; 1267 #clock-cells = <0>; 1268 clock-output-names = "clk_usbphy0_480m"; 1269 status = "disabled"; 1270 1271 u2phy0_host: host-port { 1272 #phy-cells = <0>; 1273 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1274 interrupt-names = "linestate"; 1275 status = "disabled"; 1276 }; 1277 1278 u2phy0_otg: otg-port { 1279 #phy-cells = <0>; 1280 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1281 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1282 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1283 interrupt-names = "otg-bvalid", "otg-id", 1284 "linestate"; 1285 status = "disabled"; 1286 }; 1287 }; 1288 1289 u2phy1: usb2-phy@e460 { 1290 compatible = "rockchip,rk3399-usb2phy"; 1291 reg = <0xe460 0x10>; 1292 clocks = <&cru SCLK_USB2PHY1_REF>; 1293 clock-names = "phyclk"; 1294 #clock-cells = <0>; 1295 clock-output-names = "clk_usbphy1_480m"; 1296 status = "disabled"; 1297 1298 u2phy1_host: host-port { 1299 #phy-cells = <0>; 1300 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1301 interrupt-names = "linestate"; 1302 status = "disabled"; 1303 }; 1304 1305 u2phy1_otg: otg-port { 1306 #phy-cells = <0>; 1307 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1308 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1309 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1310 interrupt-names = "otg-bvalid", "otg-id", 1311 "linestate"; 1312 status = "disabled"; 1313 }; 1314 }; 1315 1316 emmc_phy: phy@f780 { 1317 compatible = "rockchip,rk3399-emmc-phy"; 1318 reg = <0xf780 0x24>; 1319 clocks = <&sdhci>; 1320 clock-names = "emmcclk"; 1321 #phy-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 pcie_phy: pcie-phy { 1326 compatible = "rockchip,rk3399-pcie-phy"; 1327 clocks = <&cru SCLK_PCIEPHY_REF>; 1328 clock-names = "refclk"; 1329 #phy-cells = <0>; 1330 resets = <&cru SRST_PCIEPHY>; 1331 reset-names = "phy"; 1332 status = "disabled"; 1333 }; 1334 }; 1335 1336 watchdog@ff848000 { 1337 compatible = "snps,dw-wdt"; 1338 reg = <0x0 0xff848000 0x0 0x100>; 1339 clocks = <&cru PCLK_WDT>; 1340 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1341 }; 1342 1343 rktimer: rktimer@ff850000 { 1344 compatible = "rockchip,rk3399-timer"; 1345 reg = <0x0 0xff850000 0x0 0x1000>; 1346 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1347 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1348 clock-names = "pclk", "timer"; 1349 }; 1350 1351 spdif: spdif@ff870000 { 1352 compatible = "rockchip,rk3399-spdif"; 1353 reg = <0x0 0xff870000 0x0 0x1000>; 1354 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1355 dmas = <&dmac_bus 7>; 1356 dma-names = "tx"; 1357 clock-names = "mclk", "hclk"; 1358 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&spdif_bus>; 1361 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1362 status = "disabled"; 1363 }; 1364 1365 i2s0: i2s@ff880000 { 1366 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1367 reg = <0x0 0xff880000 0x0 0x1000>; 1368 rockchip,grf = <&grf>; 1369 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1370 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1371 dma-names = "tx", "rx"; 1372 clock-names = "i2s_clk", "i2s_hclk"; 1373 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1374 pinctrl-names = "default"; 1375 pinctrl-0 = <&i2s0_8ch_bus>; 1376 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1377 status = "disabled"; 1378 }; 1379 1380 i2s1: i2s@ff890000 { 1381 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1382 reg = <0x0 0xff890000 0x0 0x1000>; 1383 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1384 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1385 dma-names = "tx", "rx"; 1386 clock-names = "i2s_clk", "i2s_hclk"; 1387 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1388 pinctrl-names = "default"; 1389 pinctrl-0 = <&i2s1_2ch_bus>; 1390 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1391 status = "disabled"; 1392 }; 1393 1394 i2s2: i2s@ff8a0000 { 1395 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1396 reg = <0x0 0xff8a0000 0x0 0x1000>; 1397 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1398 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1399 dma-names = "tx", "rx"; 1400 clock-names = "i2s_clk", "i2s_hclk"; 1401 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1402 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1403 status = "disabled"; 1404 }; 1405 1406 i2c0: i2c@ff3c0000 { 1407 compatible = "rockchip,rk3399-i2c"; 1408 reg = <0x0 0xff3c0000 0x0 0x1000>; 1409 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1410 assigned-clock-rates = <200000000>; 1411 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1412 clock-names = "i2c", "pclk"; 1413 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1414 pinctrl-names = "default"; 1415 pinctrl-0 = <&i2c0_xfer>; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 vopl: vop@ff8f0000 { 1422 compatible = "rockchip,rk3399-vop-lit"; 1423 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1424 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1425 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1426 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1427 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1428 reset-names = "axi", "ahb", "dclk"; 1429 status = "disabled"; 1430 vopl_out: port { 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 vopl_out_mipi: endpoint@0 { 1434 reg = <0>; 1435 remote-endpoint = <&mipi_in_vopl>; 1436 }; 1437 1438 vopl_out_hdmi: endpoint@1 { 1439 reg = <1>; 1440 remote-endpoint = <&hdmi_in_vopl>; 1441 }; 1442 1443 vopl_out_edp: endpoint@2 { 1444 reg = <2>; 1445 remote-endpoint = <&edp_in_vopl>; 1446 }; 1447 }; 1448 }; 1449 1450 vopb: vop@ff900000 { 1451 compatible = "rockchip,rk3399-vop-big"; 1452 reg = <0x0 0xff900000 0x0 0x3efc>; 1453 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1454 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1455 #clock-cells = <0>; 1456 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1457 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1458 reset-names = "axi", "ahb", "dclk"; 1459 status = "disabled"; 1460 vopb_out: port { 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 vopb_out_mipi: endpoint@0 { 1464 reg = <0>; 1465 remote-endpoint = <&mipi_in_vopb>; 1466 }; 1467 1468 vopb_out_hdmi: endpoint@1 { 1469 reg = <1>; 1470 remote-endpoint = <&hdmi_in_vopb>; 1471 }; 1472 1473 vopb_out_edp: endpoint@2 { 1474 reg = <2>; 1475 remote-endpoint = <&edp_in_vopb>; 1476 }; 1477 }; 1478 }; 1479 1480 hdmi: hdmi@ff940000 { 1481 compatible = "rockchip,rk3399-dw-hdmi"; 1482 reg = <0x0 0xff940000 0x0 0x20000>; 1483 reg-io-width = <4>; 1484 rockchip,grf = <&grf>; 1485 pinctrl-names = "default"; 1486 pinctrl-0 = <&hdmi_i2c_xfer>; 1487 power-domains = <&power RK3399_PD_HDCP>; 1488 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1489 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; 1490 clock-names = "iahb", "isfr", "vpll", "grf"; 1491 status = "okay"; 1492 1493 ports { 1494 hdmi_in: port { 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 hdmi_in_vopb: endpoint@0 { 1498 reg = <0>; 1499 remote-endpoint = <&vopb_out_hdmi>; 1500 }; 1501 hdmi_in_vopl: endpoint@1 { 1502 reg = <1>; 1503 remote-endpoint = <&vopl_out_hdmi>; 1504 }; 1505 }; 1506 }; 1507 }; 1508 1509 mipi_dsi: mipi@ff960000 { 1510 compatible = "rockchip,rk3399_mipi_dsi"; 1511 reg = <0x0 0xff960000 0x0 0x8000>; 1512 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1513 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, 1514 <&cru SCLK_DPHY_TX0_CFG>; 1515 clock-names = "ref", "pclk", "phy_cfg"; 1516 rockchip,grf = <&grf>; 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 status = "disabled"; 1520 ports { 1521 #address-cells = <1>; 1522 #size-cells = <0>; 1523 reg = <1>; 1524 mipi_in: port { 1525 #address-cells = <1>; 1526 #size-cells = <0>; 1527 mipi_in_vopb: endpoint@0 { 1528 reg = <0>; 1529 remote-endpoint = <&vopb_out_mipi>; 1530 }; 1531 mipi_in_vopl: endpoint@1 { 1532 reg = <1>; 1533 remote-endpoint = <&vopl_out_mipi>; 1534 }; 1535 }; 1536 }; 1537 }; 1538 1539 edp: edp@ff970000 { 1540 compatible = "rockchip,rk3399-edp"; 1541 reg = <0x0 0xff970000 0x0 0x8000>; 1542 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1543 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>; 1544 clock-names = "dp", "pclk"; 1545 power-domains = <&power RK3399_PD_EDP>; 1546 resets = <&cru SRST_P_EDP_CTRL>; 1547 reset-names = "dp"; 1548 rockchip,grf = <&grf>; 1549 status = "disabled"; 1550 pinctrl-names = "default"; 1551 pinctrl-0 = <&edp_hpd>; 1552 1553 ports { 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 1557 edp_in: port@0 { 1558 reg = <0>; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 1562 edp_in_vopb: endpoint@0 { 1563 reg = <0>; 1564 remote-endpoint = <&vopb_out_edp>; 1565 }; 1566 1567 edp_in_vopl: endpoint@1 { 1568 reg = <1>; 1569 remote-endpoint = <&vopl_out_edp>; 1570 }; 1571 }; 1572 }; 1573 }; 1574 1575 pinctrl: pinctrl { 1576 compatible = "rockchip,rk3399-pinctrl"; 1577 rockchip,grf = <&grf>; 1578 rockchip,pmu = <&pmugrf>; 1579 #address-cells = <2>; 1580 #size-cells = <2>; 1581 ranges; 1582 1583 gpio0: gpio0@ff720000 { 1584 compatible = "rockchip,gpio-bank"; 1585 reg = <0x0 0xff720000 0x0 0x100>; 1586 clocks = <&pmucru PCLK_GPIO0_PMU>; 1587 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1588 1589 gpio-controller; 1590 #gpio-cells = <0x2>; 1591 1592 interrupt-controller; 1593 #interrupt-cells = <0x2>; 1594 }; 1595 1596 gpio1: gpio1@ff730000 { 1597 compatible = "rockchip,gpio-bank"; 1598 reg = <0x0 0xff730000 0x0 0x100>; 1599 clocks = <&pmucru PCLK_GPIO1_PMU>; 1600 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1601 1602 gpio-controller; 1603 #gpio-cells = <0x2>; 1604 1605 interrupt-controller; 1606 #interrupt-cells = <0x2>; 1607 }; 1608 1609 gpio2: gpio2@ff780000 { 1610 compatible = "rockchip,gpio-bank"; 1611 reg = <0x0 0xff780000 0x0 0x100>; 1612 clocks = <&cru PCLK_GPIO2>; 1613 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1614 1615 gpio-controller; 1616 #gpio-cells = <0x2>; 1617 1618 interrupt-controller; 1619 #interrupt-cells = <0x2>; 1620 }; 1621 1622 gpio3: gpio3@ff788000 { 1623 compatible = "rockchip,gpio-bank"; 1624 reg = <0x0 0xff788000 0x0 0x100>; 1625 clocks = <&cru PCLK_GPIO3>; 1626 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1627 1628 gpio-controller; 1629 #gpio-cells = <0x2>; 1630 1631 interrupt-controller; 1632 #interrupt-cells = <0x2>; 1633 }; 1634 1635 gpio4: gpio4@ff790000 { 1636 compatible = "rockchip,gpio-bank"; 1637 reg = <0x0 0xff790000 0x0 0x100>; 1638 clocks = <&cru PCLK_GPIO4>; 1639 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1640 1641 gpio-controller; 1642 #gpio-cells = <0x2>; 1643 1644 interrupt-controller; 1645 #interrupt-cells = <0x2>; 1646 }; 1647 1648 pcfg_pull_up: pcfg-pull-up { 1649 bias-pull-up; 1650 }; 1651 1652 pcfg_pull_down: pcfg-pull-down { 1653 bias-pull-down; 1654 }; 1655 1656 pcfg_pull_none: pcfg-pull-none { 1657 bias-disable; 1658 }; 1659 1660 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1661 bias-disable; 1662 drive-strength = <12>; 1663 }; 1664 1665 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1666 bias-pull-up; 1667 drive-strength = <8>; 1668 }; 1669 1670 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1671 bias-pull-down; 1672 drive-strength = <4>; 1673 }; 1674 1675 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1676 bias-pull-up; 1677 drive-strength = <2>; 1678 }; 1679 1680 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1681 bias-pull-down; 1682 drive-strength = <12>; 1683 }; 1684 1685 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1686 bias-disable; 1687 drive-strength = <13>; 1688 }; 1689 1690 clock { 1691 clk_32k: clk-32k { 1692 rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>; 1693 }; 1694 }; 1695 1696 edp { 1697 edp_hpd: edp-hpd { 1698 rockchip,pins = 1699 <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1700 }; 1701 }; 1702 1703 gmac { 1704 rgmii_pins: rgmii-pins { 1705 rockchip,pins = 1706 /* mac_txclk */ 1707 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1708 /* mac_rxclk */ 1709 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1710 /* mac_mdio */ 1711 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1712 /* mac_txen */ 1713 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1714 /* mac_clk */ 1715 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1716 /* mac_rxdv */ 1717 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1718 /* mac_mdc */ 1719 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1720 /* mac_rxd1 */ 1721 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1722 /* mac_rxd0 */ 1723 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1724 /* mac_txd1 */ 1725 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1726 /* mac_txd0 */ 1727 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1728 /* mac_rxd3 */ 1729 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1730 /* mac_rxd2 */ 1731 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1732 /* mac_txd3 */ 1733 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1734 /* mac_txd2 */ 1735 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>; 1736 }; 1737 1738 rmii_pins: rmii-pins { 1739 rockchip,pins = 1740 /* mac_mdio */ 1741 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1742 /* mac_txen */ 1743 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1744 /* mac_clk */ 1745 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1746 /* mac_rxer */ 1747 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1748 /* mac_rxdv */ 1749 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1750 /* mac_mdc */ 1751 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1752 /* mac_rxd1 */ 1753 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1754 /* mac_rxd0 */ 1755 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1756 /* mac_txd1 */ 1757 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1758 /* mac_txd0 */ 1759 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>; 1760 }; 1761 }; 1762 1763 i2c0 { 1764 i2c0_xfer: i2c0-xfer { 1765 rockchip,pins = 1766 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, 1767 <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1768 }; 1769 }; 1770 1771 i2c1 { 1772 i2c1_xfer: i2c1-xfer { 1773 rockchip,pins = 1774 <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1775 <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1776 }; 1777 }; 1778 1779 i2c2 { 1780 i2c2_xfer: i2c2-xfer { 1781 rockchip,pins = 1782 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 1783 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>; 1784 }; 1785 }; 1786 1787 i2c3 { 1788 i2c3_xfer: i2c3-xfer { 1789 rockchip,pins = 1790 <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1791 <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1792 }; 1793 }; 1794 1795 i2c4 { 1796 i2c4_xfer: i2c4-xfer { 1797 rockchip,pins = 1798 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1799 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1800 }; 1801 }; 1802 1803 i2c5 { 1804 i2c5_xfer: i2c5-xfer { 1805 rockchip,pins = 1806 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>, 1807 <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 1808 }; 1809 }; 1810 1811 i2c6 { 1812 i2c6_xfer: i2c6-xfer { 1813 rockchip,pins = 1814 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>, 1815 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1816 }; 1817 }; 1818 1819 i2c7 { 1820 i2c7_xfer: i2c7-xfer { 1821 rockchip,pins = 1822 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>, 1823 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1824 }; 1825 }; 1826 1827 i2c8 { 1828 i2c8_xfer: i2c8-xfer { 1829 rockchip,pins = 1830 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, 1831 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1832 }; 1833 }; 1834 1835 i2s0 { 1836 i2s0_8ch_bus: i2s0-8ch-bus { 1837 rockchip,pins = 1838 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>, 1839 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 1840 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 1841 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, 1842 <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>, 1843 <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>, 1844 <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>, 1845 <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>, 1846 <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; 1847 }; 1848 }; 1849 1850 i2s1 { 1851 i2s1_2ch_bus: i2s1-2ch-bus { 1852 rockchip,pins = 1853 <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1854 <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1855 <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1856 <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1857 <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 1858 }; 1859 }; 1860 1861 sdio0 { 1862 sdio0_bus1: sdio0-bus1 { 1863 rockchip,pins = 1864 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1865 }; 1866 1867 sdio0_bus4: sdio0-bus4 { 1868 rockchip,pins = 1869 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 1870 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 1871 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1872 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 1873 }; 1874 1875 sdio0_cmd: sdio0-cmd { 1876 rockchip,pins = 1877 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 1878 }; 1879 1880 sdio0_clk: sdio0-clk { 1881 rockchip,pins = 1882 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 1883 }; 1884 1885 sdio0_cd: sdio0-cd { 1886 rockchip,pins = 1887 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 1888 }; 1889 1890 sdio0_pwr: sdio0-pwr { 1891 rockchip,pins = 1892 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 1893 }; 1894 1895 sdio0_bkpwr: sdio0-bkpwr { 1896 rockchip,pins = 1897 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 1898 }; 1899 1900 sdio0_wp: sdio0-wp { 1901 rockchip,pins = 1902 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 1903 }; 1904 1905 sdio0_int: sdio0-int { 1906 rockchip,pins = 1907 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 1908 }; 1909 }; 1910 1911 sdmmc { 1912 sdmmc_bus1: sdmmc-bus1 { 1913 rockchip,pins = 1914 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 1915 }; 1916 1917 sdmmc_bus4: sdmmc-bus4 { 1918 rockchip,pins = 1919 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 1920 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 1921 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1922 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 1923 }; 1924 1925 sdmmc_clk: sdmmc-clk { 1926 rockchip,pins = 1927 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1928 }; 1929 1930 sdmmc_cmd: sdmmc-cmd { 1931 rockchip,pins = 1932 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 1933 }; 1934 1935 sdmmc_cd: sdmcc-cd { 1936 rockchip,pins = 1937 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 1938 }; 1939 1940 sdmmc_wp: sdmmc-wp { 1941 rockchip,pins = 1942 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 1943 }; 1944 }; 1945 1946 sleep { 1947 ap_pwroff: ap-pwroff { 1948 rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 1949 }; 1950 1951 ddrio_pwroff: ddrio-pwroff { 1952 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1953 }; 1954 }; 1955 1956 spdif { 1957 spdif_bus: spdif-bus { 1958 rockchip,pins = 1959 <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1960 }; 1961 1962 spdif_bus_1: spdif-bus-1 { 1963 rockchip,pins = 1964 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 1965 }; 1966 }; 1967 1968 spi0 { 1969 spi0_clk: spi0-clk { 1970 rockchip,pins = 1971 <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>; 1972 }; 1973 spi0_cs0: spi0-cs0 { 1974 rockchip,pins = 1975 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 1976 }; 1977 spi0_cs1: spi0-cs1 { 1978 rockchip,pins = 1979 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 1980 }; 1981 spi0_tx: spi0-tx { 1982 rockchip,pins = 1983 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>; 1984 }; 1985 spi0_rx: spi0-rx { 1986 rockchip,pins = 1987 <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>; 1988 }; 1989 }; 1990 1991 spi1 { 1992 spi1_clk: spi1-clk { 1993 rockchip,pins = 1994 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>; 1995 }; 1996 spi1_cs0: spi1-cs0 { 1997 rockchip,pins = 1998 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>; 1999 }; 2000 spi1_rx: spi1-rx { 2001 rockchip,pins = 2002 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 2003 }; 2004 spi1_tx: spi1-tx { 2005 rockchip,pins = 2006 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 2007 }; 2008 }; 2009 2010 spi2 { 2011 spi2_clk: spi2-clk { 2012 rockchip,pins = 2013 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 2014 }; 2015 spi2_cs0: spi2-cs0 { 2016 rockchip,pins = 2017 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>; 2018 }; 2019 spi2_rx: spi2-rx { 2020 rockchip,pins = 2021 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>; 2022 }; 2023 spi2_tx: spi2-tx { 2024 rockchip,pins = 2025 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>; 2026 }; 2027 }; 2028 2029 spi3 { 2030 spi3_clk: spi3-clk { 2031 rockchip,pins = 2032 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>; 2033 }; 2034 spi3_cs0: spi3-cs0 { 2035 rockchip,pins = 2036 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>; 2037 }; 2038 spi3_rx: spi3-rx { 2039 rockchip,pins = 2040 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>; 2041 }; 2042 spi3_tx: spi3-tx { 2043 rockchip,pins = 2044 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>; 2045 }; 2046 }; 2047 2048 spi4 { 2049 spi4_clk: spi4-clk { 2050 rockchip,pins = 2051 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>; 2052 }; 2053 spi4_cs0: spi4-cs0 { 2054 rockchip,pins = 2055 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>; 2056 }; 2057 spi4_rx: spi4-rx { 2058 rockchip,pins = 2059 <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>; 2060 }; 2061 spi4_tx: spi4-tx { 2062 rockchip,pins = 2063 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>; 2064 }; 2065 }; 2066 2067 spi5 { 2068 spi5_clk: spi5-clk { 2069 rockchip,pins = 2070 <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>; 2071 }; 2072 spi5_cs0: spi5-cs0 { 2073 rockchip,pins = 2074 <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>; 2075 }; 2076 spi5_rx: spi5-rx { 2077 rockchip,pins = 2078 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>; 2079 }; 2080 spi5_tx: spi5-tx { 2081 rockchip,pins = 2082 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>; 2083 }; 2084 }; 2085 2086 tsadc { 2087 otp_gpio: otp-gpio { 2088 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2089 }; 2090 2091 otp_out: otp-out { 2092 rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2093 }; 2094 }; 2095 2096 uart0 { 2097 uart0_xfer: uart0-xfer { 2098 rockchip,pins = 2099 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>, 2100 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2101 }; 2102 2103 uart0_cts: uart0-cts { 2104 rockchip,pins = 2105 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2106 }; 2107 2108 uart0_rts: uart0-rts { 2109 rockchip,pins = 2110 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2111 }; 2112 }; 2113 2114 uart1 { 2115 uart1_xfer: uart1-xfer { 2116 rockchip,pins = 2117 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 2118 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 2119 }; 2120 }; 2121 2122 uart2a { 2123 uart2a_xfer: uart2a-xfer { 2124 rockchip,pins = 2125 <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>, 2126 <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2127 }; 2128 }; 2129 2130 uart2b { 2131 uart2b_xfer: uart2b-xfer { 2132 rockchip,pins = 2133 <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 2134 <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 2135 }; 2136 }; 2137 2138 uart2c { 2139 uart2c_xfer: uart2c-xfer { 2140 rockchip,pins = 2141 <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>, 2142 <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 2143 }; 2144 }; 2145 2146 uart3 { 2147 uart3_xfer: uart3-xfer { 2148 rockchip,pins = 2149 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 2150 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 2151 }; 2152 2153 uart3_cts: uart3-cts { 2154 rockchip,pins = 2155 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2156 }; 2157 2158 uart3_rts: uart3-rts { 2159 rockchip,pins = 2160 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 2161 }; 2162 }; 2163 2164 uart4 { 2165 uart4_xfer: uart4-xfer { 2166 rockchip,pins = 2167 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>, 2168 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 2169 }; 2170 }; 2171 2172 uarthdcp { 2173 uarthdcp_xfer: uarthdcp-xfer { 2174 rockchip,pins = 2175 <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>, 2176 <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 2177 }; 2178 }; 2179 2180 pwm0 { 2181 pwm0_pin: pwm0-pin { 2182 rockchip,pins = 2183 <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2184 }; 2185 2186 vop0_pwm_pin: vop0-pwm-pin { 2187 rockchip,pins = 2188 <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2189 }; 2190 }; 2191 2192 pwm1 { 2193 pwm1_pin: pwm1-pin { 2194 rockchip,pins = 2195 <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 2196 }; 2197 2198 vop1_pwm_pin: vop1-pwm-pin { 2199 rockchip,pins = 2200 <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2201 }; 2202 }; 2203 2204 pwm2 { 2205 pwm2_pin: pwm2-pin { 2206 rockchip,pins = 2207 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2208 }; 2209 }; 2210 2211 pwm3a { 2212 pwm3a_pin: pwm3a-pin { 2213 rockchip,pins = 2214 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2215 }; 2216 }; 2217 2218 pwm3b { 2219 pwm3b_pin: pwm3b-pin { 2220 rockchip,pins = 2221 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 2222 }; 2223 }; 2224 2225 hdmi { 2226 hdmi_i2c_xfer: hdmi-i2c-xfer { 2227 rockchip,pins = 2228 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2229 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2230 }; 2231 2232 hdmi_cec: hdmi-cec { 2233 rockchip,pins = 2234 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2235 }; 2236 }; 2237 2238 pcie { 2239 pcie_clkreqn: pci-clkreqn { 2240 rockchip,pins = 2241 <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>; 2242 }; 2243 2244 pcie_clkreqnb: pci-clkreqnb { 2245 rockchip,pins = 2246 <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 2247 }; 2248 2249 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2250 rockchip,pins = 2251 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2252 }; 2253 2254 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2255 rockchip,pins = 2256 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2257 }; 2258 }; 2259 2260 }; 2261}; 2262
