1/* 2 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3399-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/rk3399-power.h> 13#include <dt-bindings/thermal/thermal.h> 14#define USB_CLASS_HUB 9 15 16/ { 17 compatible = "rockchip,rk3399"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 i2c8 = &i2c8; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 cpu-map { 45 cluster0 { 46 core0 { 47 cpu = <&cpu_l0>; 48 }; 49 core1 { 50 cpu = <&cpu_l1>; 51 }; 52 core2 { 53 cpu = <&cpu_l2>; 54 }; 55 core3 { 56 cpu = <&cpu_l3>; 57 }; 58 }; 59 60 cluster1 { 61 core0 { 62 cpu = <&cpu_b0>; 63 }; 64 core1 { 65 cpu = <&cpu_b1>; 66 }; 67 }; 68 }; 69 70 cpu_l0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53", "arm,armv8"; 73 reg = <0x0 0x0>; 74 enable-method = "psci"; 75 #cooling-cells = <2>; /* min followed by max */ 76 clocks = <&cru ARMCLKL>; 77 }; 78 79 cpu_l1: cpu@1 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 reg = <0x0 0x1>; 83 enable-method = "psci"; 84 clocks = <&cru ARMCLKL>; 85 }; 86 87 cpu_l2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53", "arm,armv8"; 90 reg = <0x0 0x2>; 91 enable-method = "psci"; 92 clocks = <&cru ARMCLKL>; 93 }; 94 95 cpu_l3: cpu@3 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a53", "arm,armv8"; 98 reg = <0x0 0x3>; 99 enable-method = "psci"; 100 clocks = <&cru ARMCLKL>; 101 }; 102 103 cpu_b0: cpu@100 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a72", "arm,armv8"; 106 reg = <0x0 0x100>; 107 enable-method = "psci"; 108 #cooling-cells = <2>; /* min followed by max */ 109 clocks = <&cru ARMCLKB>; 110 }; 111 112 cpu_b1: cpu@101 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a72", "arm,armv8"; 115 reg = <0x0 0x101>; 116 enable-method = "psci"; 117 clocks = <&cru ARMCLKB>; 118 }; 119 }; 120 121 display_subsystem: display-subsystem { 122 compatible = "rockchip,display-subsystem"; 123 ports = <&vopb_out>, <&vopl_out>; 124 status = "okay"; 125 126 route { 127 route_hdmi: route-hdmi { 128 status = "disabled"; 129 logo,uboot = "logo.bmp"; 130 logo,kernel = "logo_kernel.bmp"; 131 logo,mode = "center"; 132 charge_logo,mode = "center"; 133 connect = <&vopb_out_hdmi>; 134 }; 135 136 route_edp: route-edp { 137 status = "disabled"; 138 logo,uboot = "logo.bmp"; 139 logo,kernel = "logo_kernel.bmp"; 140 logo,mode = "center"; 141 charge_logo,mode = "center"; 142 connect = <&vopb_out_edp>; 143 }; 144 }; 145 }; 146 147 pmu_a53 { 148 compatible = "arm,cortex-a53-pmu"; 149 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 150 }; 151 152 pmu_a72 { 153 compatible = "arm,cortex-a72-pmu"; 154 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 155 }; 156 157 psci { 158 compatible = "arm,psci-1.0"; 159 method = "smc"; 160 }; 161 162 timer { 163 compatible = "arm,armv8-timer"; 164 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 165 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 166 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 167 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 168 arm,no-tick-in-suspend; 169 }; 170 171 xin24m: xin24m { 172 compatible = "fixed-clock"; 173 clock-frequency = <24000000>; 174 clock-output-names = "xin24m"; 175 #clock-cells = <0>; 176 }; 177 178 amba { 179 compatible = "simple-bus"; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 ranges; 183 184 dmac_bus: dma-controller@ff6d0000 { 185 compatible = "arm,pl330", "arm,primecell"; 186 reg = <0x0 0xff6d0000 0x0 0x4000>; 187 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 188 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 189 #dma-cells = <1>; 190 clocks = <&cru ACLK_DMAC0_PERILP>; 191 clock-names = "apb_pclk"; 192 }; 193 194 dmac_peri: dma-controller@ff6e0000 { 195 compatible = "arm,pl330", "arm,primecell"; 196 reg = <0x0 0xff6e0000 0x0 0x4000>; 197 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 198 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 199 #dma-cells = <1>; 200 clocks = <&cru ACLK_DMAC1_PERILP>; 201 clock-names = "apb_pclk"; 202 }; 203 }; 204 205 crypto: crypto@ff8b0000 { 206 compatible = "rockchip,rk3399-crypto"; 207 reg = <0x0 0xff8b0000 0x0 0x10000>; 208 clock-names = "sclk_crypto0", "sclk_crypto1"; 209 clocks = <&cru SCLK_CRYPTO0>, <&cru SCLK_CRYPTO1>; 210 status = "disabled"; 211 }; 212 213 pcie0: pcie@f8000000 { 214 compatible = "rockchip,rk3399-pcie"; 215 reg = <0x0 0xf8000000 0x0 0x2000000>, 216 <0x0 0xfd000000 0x0 0x1000000>; 217 reg-names = "axi-base", "apb-base"; 218 #address-cells = <3>; 219 #size-cells = <2>; 220 #interrupt-cells = <1>; 221 aspm-no-l0s; 222 bus-range = <0x0 0x1>; 223 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 224 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 225 clock-names = "aclk", "aclk-perf", 226 "hclk", "pm"; 227 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 228 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 229 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 230 interrupt-names = "sys", "legacy", "client"; 231 interrupt-map-mask = <0 0 0 7>; 232 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 233 <0 0 0 2 &pcie0_intc 1>, 234 <0 0 0 3 &pcie0_intc 2>, 235 <0 0 0 4 &pcie0_intc 3>; 236 linux,pci-domain = <0>; 237 max-link-speed = <1>; 238 msi-map = <0x0 &its 0x0 0x1000>; 239 phys = <&pcie_phy>; 240 phy-names = "pcie-phy"; 241 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 242 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; 243 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 244 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 245 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 246 <&cru SRST_A_PCIE>; 247 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 248 "pm", "pclk", "aclk"; 249 status = "disabled"; 250 251 pcie0_intc: interrupt-controller { 252 interrupt-controller; 253 #address-cells = <0>; 254 #interrupt-cells = <1>; 255 }; 256 }; 257 258 gmac: ethernet@fe300000 { 259 compatible = "rockchip,rk3399-gmac"; 260 reg = <0x0 0xfe300000 0x0 0x10000>; 261 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 262 interrupt-names = "macirq"; 263 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 264 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 265 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 266 <&cru PCLK_GMAC>; 267 clock-names = "stmmaceth", "mac_clk_rx", 268 "mac_clk_tx", "clk_mac_ref", 269 "clk_mac_refout", "aclk_mac", 270 "pclk_mac"; 271 power-domains = <&power RK3399_PD_GMAC>; 272 resets = <&cru SRST_A_GMAC>; 273 reset-names = "stmmaceth"; 274 rockchip,grf = <&grf>; 275 status = "disabled"; 276 }; 277 278 sdio0: dwmmc@fe310000 { 279 compatible = "rockchip,rk3399-dw-mshc", 280 "rockchip,rk3288-dw-mshc"; 281 reg = <0x0 0xfe310000 0x0 0x4000>; 282 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 283 max-frequency = <150000000>; 284 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 285 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 286 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 287 fifo-depth = <0x100>; 288 power-domains = <&power RK3399_PD_SDIOAUDIO>; 289 resets = <&cru SRST_SDIO0>; 290 reset-names = "reset"; 291 status = "disabled"; 292 }; 293 294 sdmmc: dwmmc@fe320000 { 295 compatible = "rockchip,rk3399-dw-mshc", 296 "rockchip,rk3288-dw-mshc"; 297 reg = <0x0 0xfe320000 0x0 0x4000>; 298 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 299 max-frequency = <150000000>; 300 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 301 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 302 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 303 fifo-depth = <0x100>; 304 power-domains = <&power RK3399_PD_SD>; 305 resets = <&cru SRST_SDMMC>; 306 reset-names = "reset"; 307 status = "disabled"; 308 }; 309 310 sdhci: sdhci@fe330000 { 311 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 312 reg = <0x0 0xfe330000 0x0 0x10000>; 313 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 314 arasan,soc-ctl-syscon = <&grf>; 315 assigned-clocks = <&cru SCLK_EMMC>; 316 assigned-clock-rates = <200000000>; 317 max-frequency = <150000000>; 318 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 319 clock-names = "clk_xin", "clk_ahb"; 320 clock-output-names = "emmc_cardclock"; 321 #clock-cells = <0>; 322 phys = <&emmc_phy>; 323 phy-names = "phy_arasan"; 324 power-domains = <&power RK3399_PD_EMMC>; 325 status = "disabled"; 326 }; 327 328 usb_host0_ehci: usb@fe380000 { 329 compatible = "generic-ehci"; 330 reg = <0x0 0xfe380000 0x0 0x20000>; 331 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 332 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 333 <&u2phy0>; 334 clock-names = "usbhost", "arbiter", 335 "utmi"; 336 phys = <&u2phy0_host>; 337 phy-names = "usb"; 338 power-domains = <&power RK3399_PD_PERIHP>; 339 status = "disabled"; 340 }; 341 342 usb_host0_ohci: usb@fe3a0000 { 343 compatible = "generic-ohci"; 344 reg = <0x0 0xfe3a0000 0x0 0x20000>; 345 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 346 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 347 <&u2phy0>; 348 clock-names = "usbhost", "arbiter", 349 "utmi"; 350 phys = <&u2phy0_host>; 351 phy-names = "usb"; 352 power-domains = <&power RK3399_PD_PERIHP>; 353 status = "disabled"; 354 }; 355 356 usb_host1_ehci: usb@fe3c0000 { 357 compatible = "generic-ehci"; 358 reg = <0x0 0xfe3c0000 0x0 0x20000>; 359 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 360 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 361 <&u2phy1>; 362 clock-names = "usbhost", "arbiter", 363 "utmi"; 364 phys = <&u2phy1_host>; 365 phy-names = "usb"; 366 power-domains = <&power RK3399_PD_PERIHP>; 367 status = "disabled"; 368 }; 369 370 usb_host1_ohci: usb@fe3e0000 { 371 compatible = "generic-ohci"; 372 reg = <0x0 0xfe3e0000 0x0 0x20000>; 373 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 374 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 375 <&u2phy1>; 376 clock-names = "usbhost", "arbiter", 377 "utmi"; 378 phys = <&u2phy1_host>; 379 phy-names = "usb"; 380 power-domains = <&power RK3399_PD_PERIHP>; 381 status = "disabled"; 382 }; 383 384 dwc3_typec0: usb@fe800000 { 385 compatible = "rockchip,rk3399-xhci"; 386 reg = <0x0 0xfe800000 0x0 0x100000>; 387 status = "disabled"; 388 snps,dis-enblslpm-quirk; 389 snps,phyif-utmi-bits = <16>; 390 snps,dis-u2-freeclk-exists-quirk; 391 snps,dis-u2-susphy-quirk; 392 393 #address-cells = <2>; 394 #size-cells = <2>; 395 hub { 396 compatible = "usb-hub"; 397 usb,device-class = <USB_CLASS_HUB>; 398 }; 399 typec_phy0 { 400 compatible = "rockchip,rk3399-usb3-phy"; 401 reg = <0x0 0xff7c0000 0x0 0x40000>; 402 }; 403 }; 404 405 dwc3_typec1: usb@fe900000 { 406 compatible = "rockchip,rk3399-xhci"; 407 reg = <0x0 0xfe900000 0x0 0x100000>; 408 status = "disabled"; 409 snps,dis-enblslpm-quirk; 410 snps,phyif-utmi-bits = <16>; 411 snps,dis-u2-freeclk-exists-quirk; 412 snps,dis-u2-susphy-quirk; 413 414 #address-cells = <2>; 415 #size-cells = <2>; 416 hub { 417 compatible = "usb-hub"; 418 usb,device-class = <USB_CLASS_HUB>; 419 }; 420 typec_phy1 { 421 compatible = "rockchip,rk3399-usb3-phy"; 422 reg = <0x0 0xff800000 0x0 0x40000>; 423 }; 424 }; 425 426 gic: interrupt-controller@fee00000 { 427 compatible = "arm,gic-v3"; 428 #interrupt-cells = <4>; 429 #address-cells = <2>; 430 #size-cells = <2>; 431 ranges; 432 interrupt-controller; 433 434 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 435 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 436 <0x0 0xfff00000 0 0x10000>, /* GICC */ 437 <0x0 0xfff10000 0 0x10000>, /* GICH */ 438 <0x0 0xfff20000 0 0x10000>; /* GICV */ 439 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 440 its: interrupt-controller@fee20000 { 441 compatible = "arm,gic-v3-its"; 442 msi-controller; 443 reg = <0x0 0xfee20000 0x0 0x20000>; 444 }; 445 446 ppi-partitions { 447 ppi_cluster0: interrupt-partition-0 { 448 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 449 }; 450 451 ppi_cluster1: interrupt-partition-1 { 452 affinity = <&cpu_b0 &cpu_b1>; 453 }; 454 }; 455 }; 456 457 saradc: saradc@ff100000 { 458 compatible = "rockchip,rk3399-saradc"; 459 reg = <0x0 0xff100000 0x0 0x100>; 460 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 461 #io-channel-cells = <1>; 462 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 463 clock-names = "saradc", "apb_pclk"; 464 resets = <&cru SRST_P_SARADC>; 465 reset-names = "saradc-apb"; 466 status = "disabled"; 467 }; 468 469 i2c1: i2c@ff110000 { 470 compatible = "rockchip,rk3399-i2c"; 471 reg = <0x0 0xff110000 0x0 0x1000>; 472 assigned-clocks = <&cru SCLK_I2C1>; 473 assigned-clock-rates = <200000000>; 474 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 475 clock-names = "i2c", "pclk"; 476 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 477 pinctrl-names = "default"; 478 pinctrl-0 = <&i2c1_xfer>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 status = "disabled"; 482 }; 483 484 i2c2: i2c@ff120000 { 485 compatible = "rockchip,rk3399-i2c"; 486 reg = <0x0 0xff120000 0x0 0x1000>; 487 assigned-clocks = <&cru SCLK_I2C2>; 488 assigned-clock-rates = <200000000>; 489 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 490 clock-names = "i2c", "pclk"; 491 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&i2c2_xfer>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 status = "disabled"; 497 }; 498 499 i2c3: i2c@ff130000 { 500 compatible = "rockchip,rk3399-i2c"; 501 reg = <0x0 0xff130000 0x0 0x1000>; 502 assigned-clocks = <&cru SCLK_I2C3>; 503 assigned-clock-rates = <200000000>; 504 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 505 clock-names = "i2c", "pclk"; 506 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&i2c3_xfer>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 status = "disabled"; 512 }; 513 514 i2c5: i2c@ff140000 { 515 compatible = "rockchip,rk3399-i2c"; 516 reg = <0x0 0xff140000 0x0 0x1000>; 517 assigned-clocks = <&cru SCLK_I2C5>; 518 assigned-clock-rates = <200000000>; 519 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 520 clock-names = "i2c", "pclk"; 521 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&i2c5_xfer>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 status = "disabled"; 527 }; 528 529 i2c6: i2c@ff150000 { 530 compatible = "rockchip,rk3399-i2c"; 531 reg = <0x0 0xff150000 0x0 0x1000>; 532 assigned-clocks = <&cru SCLK_I2C6>; 533 assigned-clock-rates = <200000000>; 534 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 535 clock-names = "i2c", "pclk"; 536 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 537 pinctrl-names = "default"; 538 pinctrl-0 = <&i2c6_xfer>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 status = "disabled"; 542 }; 543 544 i2c7: i2c@ff160000 { 545 compatible = "rockchip,rk3399-i2c"; 546 reg = <0x0 0xff160000 0x0 0x1000>; 547 assigned-clocks = <&cru SCLK_I2C7>; 548 assigned-clock-rates = <200000000>; 549 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 550 clock-names = "i2c", "pclk"; 551 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&i2c7_xfer>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "disabled"; 557 }; 558 559 uart0: serial@ff180000 { 560 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 561 reg = <0x0 0xff180000 0x0 0x100>; 562 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 563 clock-names = "baudclk", "apb_pclk"; 564 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 565 reg-shift = <2>; 566 reg-io-width = <4>; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&uart0_xfer>; 569 status = "disabled"; 570 }; 571 572 uart1: serial@ff190000 { 573 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 574 reg = <0x0 0xff190000 0x0 0x100>; 575 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 576 clock-names = "baudclk", "apb_pclk"; 577 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 578 reg-shift = <2>; 579 reg-io-width = <4>; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&uart1_xfer>; 582 status = "disabled"; 583 }; 584 585 uart2: serial@ff1a0000 { 586 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 587 reg = <0x0 0xff1a0000 0x0 0x100>; 588 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 589 clock-names = "baudclk", "apb_pclk"; 590 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 591 clock-frequency = <24000000>; 592 reg-shift = <2>; 593 reg-io-width = <4>; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&uart2c_xfer>; 596 status = "disabled"; 597 }; 598 599 uart3: serial@ff1b0000 { 600 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 601 reg = <0x0 0xff1b0000 0x0 0x100>; 602 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 603 clock-names = "baudclk", "apb_pclk"; 604 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 605 reg-shift = <2>; 606 reg-io-width = <4>; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&uart3_xfer>; 609 status = "disabled"; 610 }; 611 612 spi0: spi@ff1c0000 { 613 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 614 reg = <0x0 0xff1c0000 0x0 0x1000>; 615 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 616 clock-names = "spiclk", "apb_pclk"; 617 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 618 pinctrl-names = "default"; 619 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 status = "disabled"; 623 }; 624 625 spi1: spi@ff1d0000 { 626 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 627 reg = <0x0 0xff1d0000 0x0 0x1000>; 628 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 629 clock-names = "spiclk", "apb_pclk"; 630 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 631 pinctrl-names = "default"; 632 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 status = "disabled"; 636 }; 637 638 spi2: spi@ff1e0000 { 639 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 640 reg = <0x0 0xff1e0000 0x0 0x1000>; 641 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 642 clock-names = "spiclk", "apb_pclk"; 643 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 spi4: spi@ff1f0000 { 652 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 653 reg = <0x0 0xff1f0000 0x0 0x1000>; 654 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 655 clock-names = "spiclk", "apb_pclk"; 656 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 status = "disabled"; 662 }; 663 664 spi5: spi@ff200000 { 665 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 666 reg = <0x0 0xff200000 0x0 0x1000>; 667 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 668 clock-names = "spiclk", "apb_pclk"; 669 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 status = "disabled"; 675 }; 676 677 thermal_zones: thermal-zones { 678 cpu_thermal: cpu { 679 polling-delay-passive = <100>; 680 polling-delay = <1000>; 681 682 thermal-sensors = <&tsadc 0>; 683 684 trips { 685 cpu_alert0: cpu_alert0 { 686 temperature = <70000>; 687 hysteresis = <2000>; 688 type = "passive"; 689 }; 690 cpu_alert1: cpu_alert1 { 691 temperature = <75000>; 692 hysteresis = <2000>; 693 type = "passive"; 694 }; 695 cpu_crit: cpu_crit { 696 temperature = <95000>; 697 hysteresis = <2000>; 698 type = "critical"; 699 }; 700 }; 701 702 cooling-maps { 703 map0 { 704 trip = <&cpu_alert0>; 705 cooling-device = 706 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 707 }; 708 map1 { 709 trip = <&cpu_alert1>; 710 cooling-device = 711 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 712 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 713 }; 714 }; 715 }; 716 717 gpu_thermal: gpu { 718 polling-delay-passive = <100>; 719 polling-delay = <1000>; 720 721 thermal-sensors = <&tsadc 1>; 722 723 trips { 724 gpu_alert0: gpu_alert0 { 725 temperature = <75000>; 726 hysteresis = <2000>; 727 type = "passive"; 728 }; 729 gpu_crit: gpu_crit { 730 temperature = <95000>; 731 hysteresis = <2000>; 732 type = "critical"; 733 }; 734 }; 735 736 cooling-maps { 737 map0 { 738 trip = <&gpu_alert0>; 739 cooling-device = 740 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 741 }; 742 }; 743 }; 744 }; 745 746 tsadc: tsadc@ff260000 { 747 compatible = "rockchip,rk3399-tsadc"; 748 reg = <0x0 0xff260000 0x0 0x100>; 749 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 750 assigned-clocks = <&cru SCLK_TSADC>; 751 assigned-clock-rates = <750000>; 752 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 753 clock-names = "tsadc", "apb_pclk"; 754 resets = <&cru SRST_TSADC>; 755 reset-names = "tsadc-apb"; 756 rockchip,grf = <&grf>; 757 rockchip,hw-tshut-temp = <95000>; 758 pinctrl-names = "init", "default", "sleep"; 759 pinctrl-0 = <&otp_gpio>; 760 pinctrl-1 = <&otp_out>; 761 pinctrl-2 = <&otp_gpio>; 762 #thermal-sensor-cells = <1>; 763 status = "disabled"; 764 }; 765 766 qos_emmc: qos@ffa58000 { 767 compatible = "syscon"; 768 reg = <0x0 0xffa58000 0x0 0x20>; 769 }; 770 771 qos_gmac: qos@ffa5c000 { 772 compatible = "syscon"; 773 reg = <0x0 0xffa5c000 0x0 0x20>; 774 }; 775 776 qos_pcie: qos@ffa60080 { 777 compatible = "syscon"; 778 reg = <0x0 0xffa60080 0x0 0x20>; 779 }; 780 781 qos_usb_host0: qos@ffa60100 { 782 compatible = "syscon"; 783 reg = <0x0 0xffa60100 0x0 0x20>; 784 }; 785 786 qos_usb_host1: qos@ffa60180 { 787 compatible = "syscon"; 788 reg = <0x0 0xffa60180 0x0 0x20>; 789 }; 790 791 qos_usb_otg0: qos@ffa70000 { 792 compatible = "syscon"; 793 reg = <0x0 0xffa70000 0x0 0x20>; 794 }; 795 796 qos_usb_otg1: qos@ffa70080 { 797 compatible = "syscon"; 798 reg = <0x0 0xffa70080 0x0 0x20>; 799 }; 800 801 qos_sd: qos@ffa74000 { 802 compatible = "syscon"; 803 reg = <0x0 0xffa74000 0x0 0x20>; 804 }; 805 806 qos_sdioaudio: qos@ffa76000 { 807 compatible = "syscon"; 808 reg = <0x0 0xffa76000 0x0 0x20>; 809 }; 810 811 qos_hdcp: qos@ffa90000 { 812 compatible = "syscon"; 813 reg = <0x0 0xffa90000 0x0 0x20>; 814 }; 815 816 qos_iep: qos@ffa98000 { 817 compatible = "syscon"; 818 reg = <0x0 0xffa98000 0x0 0x20>; 819 }; 820 821 qos_isp0_m0: qos@ffaa0000 { 822 compatible = "syscon"; 823 reg = <0x0 0xffaa0000 0x0 0x20>; 824 }; 825 826 qos_isp0_m1: qos@ffaa0080 { 827 compatible = "syscon"; 828 reg = <0x0 0xffaa0080 0x0 0x20>; 829 }; 830 831 qos_isp1_m0: qos@ffaa8000 { 832 compatible = "syscon"; 833 reg = <0x0 0xffaa8000 0x0 0x20>; 834 }; 835 836 qos_isp1_m1: qos@ffaa8080 { 837 compatible = "syscon"; 838 reg = <0x0 0xffaa8080 0x0 0x20>; 839 }; 840 841 qos_rga_r: qos@ffab0000 { 842 compatible = "syscon"; 843 reg = <0x0 0xffab0000 0x0 0x20>; 844 }; 845 846 qos_rga_w: qos@ffab0080 { 847 compatible = "syscon"; 848 reg = <0x0 0xffab0080 0x0 0x20>; 849 }; 850 851 qos_video_m0: qos@ffab8000 { 852 compatible = "syscon"; 853 reg = <0x0 0xffab8000 0x0 0x20>; 854 }; 855 856 qos_video_m1_r: qos@ffac0000 { 857 compatible = "syscon"; 858 reg = <0x0 0xffac0000 0x0 0x20>; 859 }; 860 861 qos_video_m1_w: qos@ffac0080 { 862 compatible = "syscon"; 863 reg = <0x0 0xffac0080 0x0 0x20>; 864 }; 865 866 qos_vop_big_r: qos@ffac8000 { 867 compatible = "syscon"; 868 reg = <0x0 0xffac8000 0x0 0x20>; 869 }; 870 871 qos_vop_big_w: qos@ffac8080 { 872 compatible = "syscon"; 873 reg = <0x0 0xffac8080 0x0 0x20>; 874 }; 875 876 qos_vop_little: qos@ffad0000 { 877 compatible = "syscon"; 878 reg = <0x0 0xffad0000 0x0 0x20>; 879 }; 880 881 qos_perihp: qos@ffad8080 { 882 compatible = "syscon"; 883 reg = <0x0 0xffad8080 0x0 0x20>; 884 }; 885 886 qos_gpu: qos@ffae0000 { 887 compatible = "syscon"; 888 reg = <0x0 0xffae0000 0x0 0x20>; 889 }; 890 891 pmu: power-management@ff310000 { 892 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 893 reg = <0x0 0xff310000 0x0 0x1000>; 894 895 /* 896 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 897 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 898 * Some of the power domains are grouped together for every 899 * voltage domain. 900 * The detail contents as below. 901 */ 902 power: power-controller { 903 compatible = "rockchip,rk3399-power-controller"; 904 #power-domain-cells = <1>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 908 /* These power domains are grouped by VD_CENTER */ 909 pd_iep@RK3399_PD_IEP { 910 reg = <RK3399_PD_IEP>; 911 clocks = <&cru ACLK_IEP>, 912 <&cru HCLK_IEP>; 913 pm_qos = <&qos_iep>; 914 }; 915 pd_rga@RK3399_PD_RGA { 916 reg = <RK3399_PD_RGA>; 917 clocks = <&cru ACLK_RGA>, 918 <&cru HCLK_RGA>; 919 pm_qos = <&qos_rga_r>, 920 <&qos_rga_w>; 921 }; 922 pd_vcodec@RK3399_PD_VCODEC { 923 reg = <RK3399_PD_VCODEC>; 924 clocks = <&cru ACLK_VCODEC>, 925 <&cru HCLK_VCODEC>; 926 pm_qos = <&qos_video_m0>; 927 }; 928 pd_vdu@RK3399_PD_VDU { 929 reg = <RK3399_PD_VDU>; 930 clocks = <&cru ACLK_VDU>, 931 <&cru HCLK_VDU>; 932 pm_qos = <&qos_video_m1_r>, 933 <&qos_video_m1_w>; 934 }; 935 936 /* These power domains are grouped by VD_GPU */ 937 pd_gpu@RK3399_PD_GPU { 938 reg = <RK3399_PD_GPU>; 939 clocks = <&cru ACLK_GPU>; 940 pm_qos = <&qos_gpu>; 941 }; 942 943 /* These power domains are grouped by VD_LOGIC */ 944 pd_edp@RK3399_PD_EDP { 945 reg = <RK3399_PD_EDP>; 946 clocks = <&cru PCLK_EDP_CTRL>; 947 }; 948 pd_emmc@RK3399_PD_EMMC { 949 reg = <RK3399_PD_EMMC>; 950 clocks = <&cru ACLK_EMMC>; 951 pm_qos = <&qos_emmc>; 952 }; 953 pd_gmac@RK3399_PD_GMAC { 954 reg = <RK3399_PD_GMAC>; 955 clocks = <&cru ACLK_GMAC>, 956 <&cru PCLK_GMAC>; 957 pm_qos = <&qos_gmac>; 958 }; 959 pd_perihp@RK3399_PD_PERIHP { 960 reg = <RK3399_PD_PERIHP>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 clocks = <&cru ACLK_PERIHP>; 964 pm_qos = <&qos_perihp>, 965 <&qos_pcie>, 966 <&qos_usb_host0>, 967 <&qos_usb_host1>; 968 969 pd_sd@RK3399_PD_SD { 970 reg = <RK3399_PD_SD>; 971 clocks = <&cru HCLK_SDMMC>, 972 <&cru SCLK_SDMMC>; 973 pm_qos = <&qos_sd>; 974 }; 975 }; 976 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 977 reg = <RK3399_PD_SDIOAUDIO>; 978 clocks = <&cru HCLK_SDIO>; 979 pm_qos = <&qos_sdioaudio>; 980 }; 981 pd_usb3@RK3399_PD_USB3 { 982 reg = <RK3399_PD_USB3>; 983 clocks = <&cru ACLK_USB3>; 984 pm_qos = <&qos_usb_otg0>, 985 <&qos_usb_otg1>; 986 }; 987 pd_vio@RK3399_PD_VIO { 988 reg = <RK3399_PD_VIO>; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 992 pd_hdcp@RK3399_PD_HDCP { 993 reg = <RK3399_PD_HDCP>; 994 clocks = <&cru ACLK_HDCP>, 995 <&cru HCLK_HDCP>, 996 <&cru PCLK_HDCP>; 997 pm_qos = <&qos_hdcp>; 998 }; 999 pd_isp0@RK3399_PD_ISP0 { 1000 reg = <RK3399_PD_ISP0>; 1001 clocks = <&cru ACLK_ISP0>, 1002 <&cru HCLK_ISP0>; 1003 pm_qos = <&qos_isp0_m0>, 1004 <&qos_isp0_m1>; 1005 }; 1006 pd_isp1@RK3399_PD_ISP1 { 1007 reg = <RK3399_PD_ISP1>; 1008 clocks = <&cru ACLK_ISP1>, 1009 <&cru HCLK_ISP1>; 1010 pm_qos = <&qos_isp1_m0>, 1011 <&qos_isp1_m1>; 1012 }; 1013 pd_tcpc0@RK3399_PD_TCPC0 { 1014 reg = <RK3399_PD_TCPD0>; 1015 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1016 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1017 }; 1018 pd_tcpc1@RK3399_PD_TCPC1 { 1019 reg = <RK3399_PD_TCPD1>; 1020 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1021 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1022 }; 1023 pd_vo@RK3399_PD_VO { 1024 reg = <RK3399_PD_VO>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 1028 pd_vopb@RK3399_PD_VOPB { 1029 reg = <RK3399_PD_VOPB>; 1030 clocks = <&cru ACLK_VOP0>, 1031 <&cru HCLK_VOP0>; 1032 pm_qos = <&qos_vop_big_r>, 1033 <&qos_vop_big_w>; 1034 }; 1035 pd_vopl@RK3399_PD_VOPL { 1036 reg = <RK3399_PD_VOPL>; 1037 clocks = <&cru ACLK_VOP1>, 1038 <&cru HCLK_VOP1>; 1039 pm_qos = <&qos_vop_little>; 1040 }; 1041 }; 1042 }; 1043 }; 1044 }; 1045 1046 pmugrf: syscon@ff320000 { 1047 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1048 reg = <0x0 0xff320000 0x0 0x1000>; 1049 #address-cells = <1>; 1050 #size-cells = <1>; 1051 1052 pmu_io_domains: io-domains { 1053 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1054 status = "disabled"; 1055 }; 1056 }; 1057 1058 pmusgrf: syscon@ff330000 { 1059 compatible = "rockchip,rk3399-pmusgrf", "syscon"; 1060 reg = <0x0 0xff330000 0x0 0xe3d4>; 1061 }; 1062 1063 spi3: spi@ff350000 { 1064 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1065 reg = <0x0 0xff350000 0x0 0x1000>; 1066 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1067 clock-names = "spiclk", "apb_pclk"; 1068 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 status = "disabled"; 1074 }; 1075 1076 uart4: serial@ff370000 { 1077 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1078 reg = <0x0 0xff370000 0x0 0x100>; 1079 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1080 clock-names = "baudclk", "apb_pclk"; 1081 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1082 reg-shift = <2>; 1083 reg-io-width = <4>; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&uart4_xfer>; 1086 status = "disabled"; 1087 }; 1088 1089 i2c4: i2c@ff3d0000 { 1090 compatible = "rockchip,rk3399-i2c"; 1091 reg = <0x0 0xff3d0000 0x0 0x1000>; 1092 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1093 assigned-clock-rates = <200000000>; 1094 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1095 clock-names = "i2c", "pclk"; 1096 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1097 pinctrl-names = "default"; 1098 pinctrl-0 = <&i2c4_xfer>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 status = "disabled"; 1102 }; 1103 1104 i2c8: i2c@ff3e0000 { 1105 compatible = "rockchip,rk3399-i2c"; 1106 reg = <0x0 0xff3e0000 0x0 0x1000>; 1107 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1108 assigned-clock-rates = <200000000>; 1109 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1110 clock-names = "i2c", "pclk"; 1111 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&i2c8_xfer>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 status = "disabled"; 1117 }; 1118 1119 pwm0: pwm@ff420000 { 1120 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1121 reg = <0x0 0xff420000 0x0 0x10>; 1122 #pwm-cells = <3>; 1123 pinctrl-names = "active"; 1124 pinctrl-0 = <&pwm0_pin>; 1125 clocks = <&pmucru PCLK_RKPWM_PMU>; 1126 clock-names = "pwm"; 1127 status = "disabled"; 1128 }; 1129 1130 pwm1: pwm@ff420010 { 1131 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1132 reg = <0x0 0xff420010 0x0 0x10>; 1133 #pwm-cells = <3>; 1134 pinctrl-names = "active"; 1135 pinctrl-0 = <&pwm1_pin>; 1136 clocks = <&pmucru PCLK_RKPWM_PMU>; 1137 clock-names = "pwm"; 1138 status = "disabled"; 1139 }; 1140 1141 pwm2: pwm@ff420020 { 1142 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1143 reg = <0x0 0xff420020 0x0 0x10>; 1144 #pwm-cells = <3>; 1145 pinctrl-names = "active"; 1146 pinctrl-0 = <&pwm2_pin>; 1147 clocks = <&pmucru PCLK_RKPWM_PMU>; 1148 clock-names = "pwm"; 1149 status = "disabled"; 1150 }; 1151 1152 pwm3: pwm@ff420030 { 1153 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1154 reg = <0x0 0xff420030 0x0 0x10>; 1155 #pwm-cells = <3>; 1156 pinctrl-names = "active"; 1157 pinctrl-0 = <&pwm3a_pin>; 1158 clocks = <&pmucru PCLK_RKPWM_PMU>; 1159 clock-names = "pwm"; 1160 status = "disabled"; 1161 }; 1162 1163 cic: syscon@ff620000 { 1164 compatible = "rockchip,rk3399-cic", "syscon"; 1165 reg = <0x0 0xff620000 0x0 0x100>; 1166 }; 1167 1168 dfi: dfi@ff630000 { 1169 reg = <0x00 0xff630000 0x00 0x4000>; 1170 compatible = "rockchip,rk3399-dfi"; 1171 rockchip,pmu = <&pmugrf>; 1172 clocks = <&cru PCLK_DDR_MON>; 1173 clock-names = "pclk_ddr_mon"; 1174 status = "disabled"; 1175 }; 1176 1177 dmc: dmc { 1178 compatible = "rockchip,rk3399-dmc"; 1179 devfreq-events = <&dfi>; 1180 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; 1181 clocks = <&cru SCLK_DDRCLK>; 1182 clock-names = "dmc_clk"; 1183 reg = <0x0 0xffa80000 0x0 0x0800 1184 0x0 0xffa80800 0x0 0x1800 1185 0x0 0xffa82000 0x0 0x2000 1186 0x0 0xffa84000 0x0 0x1000 1187 0x0 0xffa88000 0x0 0x0800 1188 0x0 0xffa88800 0x0 0x1800 1189 0x0 0xffa8a000 0x0 0x2000 1190 0x0 0xffa8c000 0x0 0x1000>; 1191 }; 1192 1193 efuse0: efuse@ff690000 { 1194 compatible = "rockchip,rk3399-efuse"; 1195 reg = <0x0 0xff690000 0x0 0x80>; 1196 #address-cells = <1>; 1197 #size-cells = <1>; 1198 clocks = <&cru PCLK_EFUSE1024NS>; 1199 clock-names = "pclk_efuse"; 1200 1201 /* Data cells */ 1202 cpu_id: cpu-id@7 { 1203 reg = <0x07 0x10>; 1204 }; 1205 cpub_leakage: cpu-leakage@17 { 1206 reg = <0x17 0x1>; 1207 }; 1208 gpu_leakage: gpu-leakage@18 { 1209 reg = <0x18 0x1>; 1210 }; 1211 center_leakage: center-leakage@19 { 1212 reg = <0x19 0x1>; 1213 }; 1214 cpul_leakage: cpu-leakage@1a { 1215 reg = <0x1a 0x1>; 1216 }; 1217 logic_leakage: logic-leakage@1b { 1218 reg = <0x1b 0x1>; 1219 }; 1220 wafer_info: wafer-info@1c { 1221 reg = <0x1c 0x1>; 1222 }; 1223 }; 1224 1225 pmucru: pmu-clock-controller@ff750000 { 1226 compatible = "rockchip,rk3399-pmucru"; 1227 reg = <0x0 0xff750000 0x0 0x1000>; 1228 rockchip,grf = <&pmugrf>; 1229 #clock-cells = <1>; 1230 #reset-cells = <1>; 1231 assigned-clocks = <&pmucru PLL_PPLL>; 1232 assigned-clock-rates = <676000000>; 1233 }; 1234 1235 cru: clock-controller@ff760000 { 1236 compatible = "rockchip,rk3399-cru"; 1237 reg = <0x0 0xff760000 0x0 0x1000>; 1238 rockchip,grf = <&grf>; 1239 #clock-cells = <1>; 1240 #reset-cells = <1>; 1241 assigned-clocks = 1242 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1243 <&cru PLL_NPLL>, 1244 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1245 <&cru PCLK_PERIHP>, 1246 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1247 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1248 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1249 assigned-clock-rates = 1250 <594000000>, <800000000>, 1251 <1000000000>, 1252 <150000000>, <75000000>, 1253 <37500000>, 1254 <100000000>, <100000000>, 1255 <50000000>, <600000000>, 1256 <100000000>, <50000000>; 1257 }; 1258 1259 grf: syscon@ff770000 { 1260 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1261 reg = <0x0 0xff770000 0x0 0x10000>; 1262 #address-cells = <1>; 1263 #size-cells = <1>; 1264 1265 io_domains: io-domains { 1266 compatible = "rockchip,rk3399-io-voltage-domain"; 1267 status = "disabled"; 1268 }; 1269 1270 u2phy0: usb2-phy@e450 { 1271 compatible = "rockchip,rk3399-usb2phy"; 1272 reg = <0xe450 0x10>; 1273 clocks = <&cru SCLK_USB2PHY0_REF>; 1274 clock-names = "phyclk"; 1275 #clock-cells = <0>; 1276 clock-output-names = "clk_usbphy0_480m"; 1277 status = "disabled"; 1278 1279 u2phy0_host: host-port { 1280 #phy-cells = <0>; 1281 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1282 interrupt-names = "linestate"; 1283 status = "disabled"; 1284 }; 1285 1286 u2phy0_otg: otg-port { 1287 #phy-cells = <0>; 1288 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1289 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1290 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1291 interrupt-names = "otg-bvalid", "otg-id", 1292 "linestate"; 1293 status = "disabled"; 1294 }; 1295 }; 1296 1297 u2phy1: usb2-phy@e460 { 1298 compatible = "rockchip,rk3399-usb2phy"; 1299 reg = <0xe460 0x10>; 1300 clocks = <&cru SCLK_USB2PHY1_REF>; 1301 clock-names = "phyclk"; 1302 #clock-cells = <0>; 1303 clock-output-names = "clk_usbphy1_480m"; 1304 status = "disabled"; 1305 1306 u2phy1_host: host-port { 1307 #phy-cells = <0>; 1308 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1309 interrupt-names = "linestate"; 1310 status = "disabled"; 1311 }; 1312 1313 u2phy1_otg: otg-port { 1314 #phy-cells = <0>; 1315 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1316 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1317 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1318 interrupt-names = "otg-bvalid", "otg-id", 1319 "linestate"; 1320 status = "disabled"; 1321 }; 1322 }; 1323 1324 emmc_phy: phy@f780 { 1325 compatible = "rockchip,rk3399-emmc-phy"; 1326 reg = <0xf780 0x24>; 1327 clocks = <&sdhci>; 1328 clock-names = "emmcclk"; 1329 #phy-cells = <0>; 1330 status = "disabled"; 1331 }; 1332 1333 pcie_phy: pcie-phy { 1334 compatible = "rockchip,rk3399-pcie-phy"; 1335 clocks = <&cru SCLK_PCIEPHY_REF>; 1336 clock-names = "refclk"; 1337 #phy-cells = <0>; 1338 resets = <&cru SRST_PCIEPHY>; 1339 reset-names = "phy"; 1340 status = "disabled"; 1341 }; 1342 }; 1343 1344 watchdog@ff848000 { 1345 compatible = "snps,dw-wdt"; 1346 reg = <0x0 0xff848000 0x0 0x100>; 1347 clocks = <&cru PCLK_WDT>; 1348 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1349 }; 1350 1351 rktimer: rktimer@ff850000 { 1352 compatible = "rockchip,rk3399-timer"; 1353 reg = <0x0 0xff850000 0x0 0x1000>; 1354 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1355 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1356 clock-names = "pclk", "timer"; 1357 }; 1358 1359 spdif: spdif@ff870000 { 1360 compatible = "rockchip,rk3399-spdif"; 1361 reg = <0x0 0xff870000 0x0 0x1000>; 1362 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1363 dmas = <&dmac_bus 7>; 1364 dma-names = "tx"; 1365 clock-names = "mclk", "hclk"; 1366 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1367 pinctrl-names = "default"; 1368 pinctrl-0 = <&spdif_bus>; 1369 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1370 status = "disabled"; 1371 }; 1372 1373 i2s0: i2s@ff880000 { 1374 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1375 reg = <0x0 0xff880000 0x0 0x1000>; 1376 rockchip,grf = <&grf>; 1377 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1378 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1379 dma-names = "tx", "rx"; 1380 clock-names = "i2s_clk", "i2s_hclk"; 1381 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&i2s0_8ch_bus>; 1384 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1385 status = "disabled"; 1386 }; 1387 1388 i2s1: i2s@ff890000 { 1389 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1390 reg = <0x0 0xff890000 0x0 0x1000>; 1391 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1392 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1393 dma-names = "tx", "rx"; 1394 clock-names = "i2s_clk", "i2s_hclk"; 1395 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1396 pinctrl-names = "default"; 1397 pinctrl-0 = <&i2s1_2ch_bus>; 1398 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1399 status = "disabled"; 1400 }; 1401 1402 i2s2: i2s@ff8a0000 { 1403 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1404 reg = <0x0 0xff8a0000 0x0 0x1000>; 1405 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1406 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1407 dma-names = "tx", "rx"; 1408 clock-names = "i2s_clk", "i2s_hclk"; 1409 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1410 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1411 status = "disabled"; 1412 }; 1413 1414 i2c0: i2c@ff3c0000 { 1415 compatible = "rockchip,rk3399-i2c"; 1416 reg = <0x0 0xff3c0000 0x0 0x1000>; 1417 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1418 assigned-clock-rates = <200000000>; 1419 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1420 clock-names = "i2c", "pclk"; 1421 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1422 pinctrl-names = "default"; 1423 pinctrl-0 = <&i2c0_xfer>; 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 status = "disabled"; 1427 }; 1428 1429 vopl: vop@ff8f0000 { 1430 compatible = "rockchip,rk3399-vop-lit"; 1431 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1432 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1433 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1434 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1435 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1436 reset-names = "axi", "ahb", "dclk"; 1437 status = "disabled"; 1438 vopl_out: port { 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 vopl_out_mipi: endpoint@0 { 1442 reg = <0>; 1443 remote-endpoint = <&mipi_in_vopl>; 1444 }; 1445 1446 vopl_out_hdmi: endpoint@1 { 1447 reg = <1>; 1448 remote-endpoint = <&hdmi_in_vopl>; 1449 }; 1450 1451 vopl_out_edp: endpoint@2 { 1452 reg = <2>; 1453 remote-endpoint = <&edp_in_vopl>; 1454 }; 1455 }; 1456 }; 1457 1458 vopb: vop@ff900000 { 1459 compatible = "rockchip,rk3399-vop-big"; 1460 reg = <0x0 0xff900000 0x0 0x3efc>; 1461 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1462 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1463 #clock-cells = <0>; 1464 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1465 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1466 reset-names = "axi", "ahb", "dclk"; 1467 status = "disabled"; 1468 vopb_out: port { 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 vopb_out_mipi: endpoint@0 { 1472 reg = <0>; 1473 remote-endpoint = <&mipi_in_vopb>; 1474 }; 1475 1476 vopb_out_hdmi: endpoint@1 { 1477 reg = <1>; 1478 remote-endpoint = <&hdmi_in_vopb>; 1479 }; 1480 1481 vopb_out_edp: endpoint@2 { 1482 reg = <2>; 1483 remote-endpoint = <&edp_in_vopb>; 1484 }; 1485 }; 1486 }; 1487 1488 hdmi: hdmi@ff940000 { 1489 compatible = "rockchip,rk3399-dw-hdmi"; 1490 reg = <0x0 0xff940000 0x0 0x20000>; 1491 reg-io-width = <4>; 1492 rockchip,grf = <&grf>; 1493 pinctrl-names = "default"; 1494 pinctrl-0 = <&hdmi_i2c_xfer>; 1495 power-domains = <&power RK3399_PD_HDCP>; 1496 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1497 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; 1498 clock-names = "iahb", "isfr", "vpll", "grf"; 1499 status = "okay"; 1500 1501 ports { 1502 hdmi_in: port { 1503 #address-cells = <1>; 1504 #size-cells = <0>; 1505 hdmi_in_vopb: endpoint@0 { 1506 reg = <0>; 1507 remote-endpoint = <&vopb_out_hdmi>; 1508 }; 1509 hdmi_in_vopl: endpoint@1 { 1510 reg = <1>; 1511 remote-endpoint = <&vopl_out_hdmi>; 1512 }; 1513 }; 1514 }; 1515 }; 1516 1517 mipi_dsi: mipi@ff960000 { 1518 compatible = "rockchip,rk3399_mipi_dsi"; 1519 reg = <0x0 0xff960000 0x0 0x8000>; 1520 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1521 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, 1522 <&cru SCLK_DPHY_TX0_CFG>; 1523 clock-names = "ref", "pclk", "phy_cfg"; 1524 rockchip,grf = <&grf>; 1525 #address-cells = <1>; 1526 #size-cells = <0>; 1527 status = "disabled"; 1528 ports { 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 reg = <1>; 1532 mipi_in: port { 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 mipi_in_vopb: endpoint@0 { 1536 reg = <0>; 1537 remote-endpoint = <&vopb_out_mipi>; 1538 }; 1539 mipi_in_vopl: endpoint@1 { 1540 reg = <1>; 1541 remote-endpoint = <&vopl_out_mipi>; 1542 }; 1543 }; 1544 }; 1545 }; 1546 1547 edp: edp@ff970000 { 1548 compatible = "rockchip,rk3399-edp"; 1549 reg = <0x0 0xff970000 0x0 0x8000>; 1550 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1551 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>; 1552 clock-names = "dp", "pclk"; 1553 power-domains = <&power RK3399_PD_EDP>; 1554 resets = <&cru SRST_P_EDP_CTRL>; 1555 reset-names = "dp"; 1556 rockchip,grf = <&grf>; 1557 status = "disabled"; 1558 pinctrl-names = "default"; 1559 pinctrl-0 = <&edp_hpd>; 1560 1561 ports { 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 1565 edp_in: port@0 { 1566 reg = <0>; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 1570 edp_in_vopb: endpoint@0 { 1571 reg = <0>; 1572 remote-endpoint = <&vopb_out_edp>; 1573 }; 1574 1575 edp_in_vopl: endpoint@1 { 1576 reg = <1>; 1577 remote-endpoint = <&vopl_out_edp>; 1578 }; 1579 }; 1580 }; 1581 }; 1582 1583 pinctrl: pinctrl { 1584 compatible = "rockchip,rk3399-pinctrl"; 1585 rockchip,grf = <&grf>; 1586 rockchip,pmu = <&pmugrf>; 1587 #address-cells = <2>; 1588 #size-cells = <2>; 1589 ranges; 1590 1591 gpio0: gpio0@ff720000 { 1592 compatible = "rockchip,gpio-bank"; 1593 reg = <0x0 0xff720000 0x0 0x100>; 1594 clocks = <&pmucru PCLK_GPIO0_PMU>; 1595 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1596 1597 gpio-controller; 1598 #gpio-cells = <0x2>; 1599 1600 interrupt-controller; 1601 #interrupt-cells = <0x2>; 1602 }; 1603 1604 gpio1: gpio1@ff730000 { 1605 compatible = "rockchip,gpio-bank"; 1606 reg = <0x0 0xff730000 0x0 0x100>; 1607 clocks = <&pmucru PCLK_GPIO1_PMU>; 1608 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1609 1610 gpio-controller; 1611 #gpio-cells = <0x2>; 1612 1613 interrupt-controller; 1614 #interrupt-cells = <0x2>; 1615 }; 1616 1617 gpio2: gpio2@ff780000 { 1618 compatible = "rockchip,gpio-bank"; 1619 reg = <0x0 0xff780000 0x0 0x100>; 1620 clocks = <&cru PCLK_GPIO2>; 1621 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1622 1623 gpio-controller; 1624 #gpio-cells = <0x2>; 1625 1626 interrupt-controller; 1627 #interrupt-cells = <0x2>; 1628 }; 1629 1630 gpio3: gpio3@ff788000 { 1631 compatible = "rockchip,gpio-bank"; 1632 reg = <0x0 0xff788000 0x0 0x100>; 1633 clocks = <&cru PCLK_GPIO3>; 1634 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1635 1636 gpio-controller; 1637 #gpio-cells = <0x2>; 1638 1639 interrupt-controller; 1640 #interrupt-cells = <0x2>; 1641 }; 1642 1643 gpio4: gpio4@ff790000 { 1644 compatible = "rockchip,gpio-bank"; 1645 reg = <0x0 0xff790000 0x0 0x100>; 1646 clocks = <&cru PCLK_GPIO4>; 1647 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1648 1649 gpio-controller; 1650 #gpio-cells = <0x2>; 1651 1652 interrupt-controller; 1653 #interrupt-cells = <0x2>; 1654 }; 1655 1656 pcfg_pull_up: pcfg-pull-up { 1657 bias-pull-up; 1658 }; 1659 1660 pcfg_pull_down: pcfg-pull-down { 1661 bias-pull-down; 1662 }; 1663 1664 pcfg_pull_none: pcfg-pull-none { 1665 bias-disable; 1666 }; 1667 1668 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1669 bias-disable; 1670 drive-strength = <12>; 1671 }; 1672 1673 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1674 bias-pull-up; 1675 drive-strength = <8>; 1676 }; 1677 1678 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1679 bias-pull-down; 1680 drive-strength = <4>; 1681 }; 1682 1683 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1684 bias-pull-up; 1685 drive-strength = <2>; 1686 }; 1687 1688 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1689 bias-pull-down; 1690 drive-strength = <12>; 1691 }; 1692 1693 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1694 bias-disable; 1695 drive-strength = <13>; 1696 }; 1697 1698 clock { 1699 clk_32k: clk-32k { 1700 rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>; 1701 }; 1702 }; 1703 1704 edp { 1705 edp_hpd: edp-hpd { 1706 rockchip,pins = 1707 <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1708 }; 1709 }; 1710 1711 gmac { 1712 rgmii_pins: rgmii-pins { 1713 rockchip,pins = 1714 /* mac_txclk */ 1715 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1716 /* mac_rxclk */ 1717 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1718 /* mac_mdio */ 1719 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1720 /* mac_txen */ 1721 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1722 /* mac_clk */ 1723 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1724 /* mac_rxdv */ 1725 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1726 /* mac_mdc */ 1727 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1728 /* mac_rxd1 */ 1729 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1730 /* mac_rxd0 */ 1731 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1732 /* mac_txd1 */ 1733 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1734 /* mac_txd0 */ 1735 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1736 /* mac_rxd3 */ 1737 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1738 /* mac_rxd2 */ 1739 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1740 /* mac_txd3 */ 1741 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1742 /* mac_txd2 */ 1743 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>; 1744 }; 1745 1746 rmii_pins: rmii-pins { 1747 rockchip,pins = 1748 /* mac_mdio */ 1749 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1750 /* mac_txen */ 1751 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1752 /* mac_clk */ 1753 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1754 /* mac_rxer */ 1755 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1756 /* mac_rxdv */ 1757 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1758 /* mac_mdc */ 1759 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1760 /* mac_rxd1 */ 1761 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1762 /* mac_rxd0 */ 1763 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1764 /* mac_txd1 */ 1765 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1766 /* mac_txd0 */ 1767 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>; 1768 }; 1769 }; 1770 1771 i2c0 { 1772 i2c0_xfer: i2c0-xfer { 1773 rockchip,pins = 1774 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, 1775 <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1776 }; 1777 }; 1778 1779 i2c1 { 1780 i2c1_xfer: i2c1-xfer { 1781 rockchip,pins = 1782 <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1783 <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1784 }; 1785 }; 1786 1787 i2c2 { 1788 i2c2_xfer: i2c2-xfer { 1789 rockchip,pins = 1790 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 1791 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>; 1792 }; 1793 }; 1794 1795 i2c3 { 1796 i2c3_xfer: i2c3-xfer { 1797 rockchip,pins = 1798 <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1799 <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1800 }; 1801 }; 1802 1803 i2c4 { 1804 i2c4_xfer: i2c4-xfer { 1805 rockchip,pins = 1806 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1807 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1808 }; 1809 }; 1810 1811 i2c5 { 1812 i2c5_xfer: i2c5-xfer { 1813 rockchip,pins = 1814 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>, 1815 <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 1816 }; 1817 }; 1818 1819 i2c6 { 1820 i2c6_xfer: i2c6-xfer { 1821 rockchip,pins = 1822 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>, 1823 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1824 }; 1825 }; 1826 1827 i2c7 { 1828 i2c7_xfer: i2c7-xfer { 1829 rockchip,pins = 1830 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>, 1831 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1832 }; 1833 }; 1834 1835 i2c8 { 1836 i2c8_xfer: i2c8-xfer { 1837 rockchip,pins = 1838 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, 1839 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1840 }; 1841 }; 1842 1843 i2s0 { 1844 i2s0_8ch_bus: i2s0-8ch-bus { 1845 rockchip,pins = 1846 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>, 1847 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 1848 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 1849 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, 1850 <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>, 1851 <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>, 1852 <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>, 1853 <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>, 1854 <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; 1855 }; 1856 }; 1857 1858 i2s1 { 1859 i2s1_2ch_bus: i2s1-2ch-bus { 1860 rockchip,pins = 1861 <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1862 <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1863 <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1864 <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1865 <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 1866 }; 1867 }; 1868 1869 sdio0 { 1870 sdio0_bus1: sdio0-bus1 { 1871 rockchip,pins = 1872 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1873 }; 1874 1875 sdio0_bus4: sdio0-bus4 { 1876 rockchip,pins = 1877 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 1878 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 1879 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1880 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 1881 }; 1882 1883 sdio0_cmd: sdio0-cmd { 1884 rockchip,pins = 1885 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 1886 }; 1887 1888 sdio0_clk: sdio0-clk { 1889 rockchip,pins = 1890 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 1891 }; 1892 1893 sdio0_cd: sdio0-cd { 1894 rockchip,pins = 1895 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 1896 }; 1897 1898 sdio0_pwr: sdio0-pwr { 1899 rockchip,pins = 1900 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 1901 }; 1902 1903 sdio0_bkpwr: sdio0-bkpwr { 1904 rockchip,pins = 1905 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 1906 }; 1907 1908 sdio0_wp: sdio0-wp { 1909 rockchip,pins = 1910 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 1911 }; 1912 1913 sdio0_int: sdio0-int { 1914 rockchip,pins = 1915 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 1916 }; 1917 }; 1918 1919 sdmmc { 1920 sdmmc_bus1: sdmmc-bus1 { 1921 rockchip,pins = 1922 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 1923 }; 1924 1925 sdmmc_bus4: sdmmc-bus4 { 1926 rockchip,pins = 1927 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 1928 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 1929 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1930 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 1931 }; 1932 1933 sdmmc_clk: sdmmc-clk { 1934 rockchip,pins = 1935 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1936 }; 1937 1938 sdmmc_cmd: sdmmc-cmd { 1939 rockchip,pins = 1940 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 1941 }; 1942 1943 sdmmc_cd: sdmcc-cd { 1944 rockchip,pins = 1945 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 1946 }; 1947 1948 sdmmc_wp: sdmmc-wp { 1949 rockchip,pins = 1950 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 1951 }; 1952 }; 1953 1954 sleep { 1955 ap_pwroff: ap-pwroff { 1956 rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 1957 }; 1958 1959 ddrio_pwroff: ddrio-pwroff { 1960 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1961 }; 1962 }; 1963 1964 spdif { 1965 spdif_bus: spdif-bus { 1966 rockchip,pins = 1967 <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1968 }; 1969 1970 spdif_bus_1: spdif-bus-1 { 1971 rockchip,pins = 1972 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 1973 }; 1974 }; 1975 1976 spi0 { 1977 spi0_clk: spi0-clk { 1978 rockchip,pins = 1979 <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>; 1980 }; 1981 spi0_cs0: spi0-cs0 { 1982 rockchip,pins = 1983 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 1984 }; 1985 spi0_cs1: spi0-cs1 { 1986 rockchip,pins = 1987 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 1988 }; 1989 spi0_tx: spi0-tx { 1990 rockchip,pins = 1991 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>; 1992 }; 1993 spi0_rx: spi0-rx { 1994 rockchip,pins = 1995 <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>; 1996 }; 1997 }; 1998 1999 spi1 { 2000 spi1_clk: spi1-clk { 2001 rockchip,pins = 2002 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>; 2003 }; 2004 spi1_cs0: spi1-cs0 { 2005 rockchip,pins = 2006 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>; 2007 }; 2008 spi1_rx: spi1-rx { 2009 rockchip,pins = 2010 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 2011 }; 2012 spi1_tx: spi1-tx { 2013 rockchip,pins = 2014 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 2015 }; 2016 }; 2017 2018 spi2 { 2019 spi2_clk: spi2-clk { 2020 rockchip,pins = 2021 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 2022 }; 2023 spi2_cs0: spi2-cs0 { 2024 rockchip,pins = 2025 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>; 2026 }; 2027 spi2_rx: spi2-rx { 2028 rockchip,pins = 2029 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>; 2030 }; 2031 spi2_tx: spi2-tx { 2032 rockchip,pins = 2033 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>; 2034 }; 2035 }; 2036 2037 spi3 { 2038 spi3_clk: spi3-clk { 2039 rockchip,pins = 2040 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>; 2041 }; 2042 spi3_cs0: spi3-cs0 { 2043 rockchip,pins = 2044 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>; 2045 }; 2046 spi3_rx: spi3-rx { 2047 rockchip,pins = 2048 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>; 2049 }; 2050 spi3_tx: spi3-tx { 2051 rockchip,pins = 2052 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>; 2053 }; 2054 }; 2055 2056 spi4 { 2057 spi4_clk: spi4-clk { 2058 rockchip,pins = 2059 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>; 2060 }; 2061 spi4_cs0: spi4-cs0 { 2062 rockchip,pins = 2063 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>; 2064 }; 2065 spi4_rx: spi4-rx { 2066 rockchip,pins = 2067 <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>; 2068 }; 2069 spi4_tx: spi4-tx { 2070 rockchip,pins = 2071 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>; 2072 }; 2073 }; 2074 2075 spi5 { 2076 spi5_clk: spi5-clk { 2077 rockchip,pins = 2078 <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>; 2079 }; 2080 spi5_cs0: spi5-cs0 { 2081 rockchip,pins = 2082 <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>; 2083 }; 2084 spi5_rx: spi5-rx { 2085 rockchip,pins = 2086 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>; 2087 }; 2088 spi5_tx: spi5-tx { 2089 rockchip,pins = 2090 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>; 2091 }; 2092 }; 2093 2094 tsadc { 2095 otp_gpio: otp-gpio { 2096 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2097 }; 2098 2099 otp_out: otp-out { 2100 rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2101 }; 2102 }; 2103 2104 uart0 { 2105 uart0_xfer: uart0-xfer { 2106 rockchip,pins = 2107 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>, 2108 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2109 }; 2110 2111 uart0_cts: uart0-cts { 2112 rockchip,pins = 2113 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2114 }; 2115 2116 uart0_rts: uart0-rts { 2117 rockchip,pins = 2118 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2119 }; 2120 }; 2121 2122 uart1 { 2123 uart1_xfer: uart1-xfer { 2124 rockchip,pins = 2125 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 2126 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 2127 }; 2128 }; 2129 2130 uart2a { 2131 uart2a_xfer: uart2a-xfer { 2132 rockchip,pins = 2133 <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>, 2134 <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2135 }; 2136 }; 2137 2138 uart2b { 2139 uart2b_xfer: uart2b-xfer { 2140 rockchip,pins = 2141 <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 2142 <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 2143 }; 2144 }; 2145 2146 uart2c { 2147 uart2c_xfer: uart2c-xfer { 2148 rockchip,pins = 2149 <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>, 2150 <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 2151 }; 2152 }; 2153 2154 uart3 { 2155 uart3_xfer: uart3-xfer { 2156 rockchip,pins = 2157 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 2158 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 2159 }; 2160 2161 uart3_cts: uart3-cts { 2162 rockchip,pins = 2163 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2164 }; 2165 2166 uart3_rts: uart3-rts { 2167 rockchip,pins = 2168 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 2169 }; 2170 }; 2171 2172 uart4 { 2173 uart4_xfer: uart4-xfer { 2174 rockchip,pins = 2175 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>, 2176 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 2177 }; 2178 }; 2179 2180 uarthdcp { 2181 uarthdcp_xfer: uarthdcp-xfer { 2182 rockchip,pins = 2183 <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>, 2184 <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 2185 }; 2186 }; 2187 2188 pwm0 { 2189 pwm0_pin: pwm0-pin { 2190 rockchip,pins = 2191 <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2192 }; 2193 2194 vop0_pwm_pin: vop0-pwm-pin { 2195 rockchip,pins = 2196 <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2197 }; 2198 }; 2199 2200 pwm1 { 2201 pwm1_pin: pwm1-pin { 2202 rockchip,pins = 2203 <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 2204 }; 2205 2206 vop1_pwm_pin: vop1-pwm-pin { 2207 rockchip,pins = 2208 <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2209 }; 2210 }; 2211 2212 pwm2 { 2213 pwm2_pin: pwm2-pin { 2214 rockchip,pins = 2215 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2216 }; 2217 }; 2218 2219 pwm3a { 2220 pwm3a_pin: pwm3a-pin { 2221 rockchip,pins = 2222 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2223 }; 2224 }; 2225 2226 pwm3b { 2227 pwm3b_pin: pwm3b-pin { 2228 rockchip,pins = 2229 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 2230 }; 2231 }; 2232 2233 hdmi { 2234 hdmi_i2c_xfer: hdmi-i2c-xfer { 2235 rockchip,pins = 2236 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2237 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2238 }; 2239 2240 hdmi_cec: hdmi-cec { 2241 rockchip,pins = 2242 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2243 }; 2244 }; 2245 2246 pcie { 2247 pcie_clkreqn: pci-clkreqn { 2248 rockchip,pins = 2249 <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>; 2250 }; 2251 2252 pcie_clkreqnb: pci-clkreqnb { 2253 rockchip,pins = 2254 <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 2255 }; 2256 2257 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2258 rockchip,pins = 2259 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2260 }; 2261 2262 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2263 rockchip,pins = 2264 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2265 }; 2266 }; 2267 2268 }; 2269}; 2270
