1/* 2 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3399-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/rk3399-power.h> 13#include <dt-bindings/thermal/thermal.h> 14#define USB_CLASS_HUB 9 15 16/ { 17 compatible = "rockchip,rk3399"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 i2c8 = &i2c8; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 cpu-map { 45 cluster0 { 46 core0 { 47 cpu = <&cpu_l0>; 48 }; 49 core1 { 50 cpu = <&cpu_l1>; 51 }; 52 core2 { 53 cpu = <&cpu_l2>; 54 }; 55 core3 { 56 cpu = <&cpu_l3>; 57 }; 58 }; 59 60 cluster1 { 61 core0 { 62 cpu = <&cpu_b0>; 63 }; 64 core1 { 65 cpu = <&cpu_b1>; 66 }; 67 }; 68 }; 69 70 cpu_l0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53", "arm,armv8"; 73 reg = <0x0 0x0>; 74 enable-method = "psci"; 75 #cooling-cells = <2>; /* min followed by max */ 76 clocks = <&cru ARMCLKL>; 77 }; 78 79 cpu_l1: cpu@1 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 reg = <0x0 0x1>; 83 enable-method = "psci"; 84 clocks = <&cru ARMCLKL>; 85 }; 86 87 cpu_l2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53", "arm,armv8"; 90 reg = <0x0 0x2>; 91 enable-method = "psci"; 92 clocks = <&cru ARMCLKL>; 93 }; 94 95 cpu_l3: cpu@3 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a53", "arm,armv8"; 98 reg = <0x0 0x3>; 99 enable-method = "psci"; 100 clocks = <&cru ARMCLKL>; 101 }; 102 103 cpu_b0: cpu@100 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a72", "arm,armv8"; 106 reg = <0x0 0x100>; 107 enable-method = "psci"; 108 #cooling-cells = <2>; /* min followed by max */ 109 clocks = <&cru ARMCLKB>; 110 }; 111 112 cpu_b1: cpu@101 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a72", "arm,armv8"; 115 reg = <0x0 0x101>; 116 enable-method = "psci"; 117 clocks = <&cru ARMCLKB>; 118 }; 119 }; 120 121 pmu_a53 { 122 compatible = "arm,cortex-a53-pmu"; 123 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 124 }; 125 126 pmu_a72 { 127 compatible = "arm,cortex-a72-pmu"; 128 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 129 }; 130 131 psci { 132 compatible = "arm,psci-1.0"; 133 method = "smc"; 134 }; 135 136 timer { 137 compatible = "arm,armv8-timer"; 138 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 139 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 140 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 141 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 142 arm,no-tick-in-suspend; 143 }; 144 145 xin24m: xin24m { 146 compatible = "fixed-clock"; 147 clock-frequency = <24000000>; 148 clock-output-names = "xin24m"; 149 #clock-cells = <0>; 150 }; 151 152 amba { 153 compatible = "simple-bus"; 154 #address-cells = <2>; 155 #size-cells = <2>; 156 ranges; 157 158 dmac_bus: dma-controller@ff6d0000 { 159 compatible = "arm,pl330", "arm,primecell"; 160 reg = <0x0 0xff6d0000 0x0 0x4000>; 161 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 162 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 163 #dma-cells = <1>; 164 clocks = <&cru ACLK_DMAC0_PERILP>; 165 clock-names = "apb_pclk"; 166 }; 167 168 dmac_peri: dma-controller@ff6e0000 { 169 compatible = "arm,pl330", "arm,primecell"; 170 reg = <0x0 0xff6e0000 0x0 0x4000>; 171 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 172 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 173 #dma-cells = <1>; 174 clocks = <&cru ACLK_DMAC1_PERILP>; 175 clock-names = "apb_pclk"; 176 }; 177 }; 178 179 pcie0: pcie@f8000000 { 180 compatible = "rockchip,rk3399-pcie"; 181 reg = <0x0 0xf8000000 0x0 0x2000000>, 182 <0x0 0xfd000000 0x0 0x1000000>; 183 reg-names = "axi-base", "apb-base"; 184 #address-cells = <3>; 185 #size-cells = <2>; 186 #interrupt-cells = <1>; 187 aspm-no-l0s; 188 bus-range = <0x0 0x1>; 189 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 190 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 191 clock-names = "aclk", "aclk-perf", 192 "hclk", "pm"; 193 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 194 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 195 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 196 interrupt-names = "sys", "legacy", "client"; 197 interrupt-map-mask = <0 0 0 7>; 198 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 199 <0 0 0 2 &pcie0_intc 1>, 200 <0 0 0 3 &pcie0_intc 2>, 201 <0 0 0 4 &pcie0_intc 3>; 202 linux,pci-domain = <0>; 203 max-link-speed = <1>; 204 msi-map = <0x0 &its 0x0 0x1000>; 205 phys = <&pcie_phy>; 206 phy-names = "pcie-phy"; 207 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 208 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; 209 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 210 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 211 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 212 <&cru SRST_A_PCIE>; 213 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 214 "pm", "pclk", "aclk"; 215 status = "disabled"; 216 217 pcie0_intc: interrupt-controller { 218 interrupt-controller; 219 #address-cells = <0>; 220 #interrupt-cells = <1>; 221 }; 222 }; 223 224 gmac: ethernet@fe300000 { 225 compatible = "rockchip,rk3399-gmac"; 226 reg = <0x0 0xfe300000 0x0 0x10000>; 227 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 228 interrupt-names = "macirq"; 229 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 230 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 231 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 232 <&cru PCLK_GMAC>; 233 clock-names = "stmmaceth", "mac_clk_rx", 234 "mac_clk_tx", "clk_mac_ref", 235 "clk_mac_refout", "aclk_mac", 236 "pclk_mac"; 237 power-domains = <&power RK3399_PD_GMAC>; 238 resets = <&cru SRST_A_GMAC>; 239 reset-names = "stmmaceth"; 240 rockchip,grf = <&grf>; 241 status = "disabled"; 242 }; 243 244 sdio0: dwmmc@fe310000 { 245 compatible = "rockchip,rk3399-dw-mshc", 246 "rockchip,rk3288-dw-mshc"; 247 reg = <0x0 0xfe310000 0x0 0x4000>; 248 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 249 max-frequency = <150000000>; 250 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 251 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 252 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 253 fifo-depth = <0x100>; 254 power-domains = <&power RK3399_PD_SDIOAUDIO>; 255 resets = <&cru SRST_SDIO0>; 256 reset-names = "reset"; 257 status = "disabled"; 258 }; 259 260 sdmmc: dwmmc@fe320000 { 261 compatible = "rockchip,rk3399-dw-mshc", 262 "rockchip,rk3288-dw-mshc"; 263 reg = <0x0 0xfe320000 0x0 0x4000>; 264 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 265 max-frequency = <150000000>; 266 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 267 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 268 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 269 fifo-depth = <0x100>; 270 power-domains = <&power RK3399_PD_SD>; 271 resets = <&cru SRST_SDMMC>; 272 reset-names = "reset"; 273 status = "disabled"; 274 }; 275 276 sdhci: sdhci@fe330000 { 277 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 278 reg = <0x0 0xfe330000 0x0 0x10000>; 279 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 280 arasan,soc-ctl-syscon = <&grf>; 281 assigned-clocks = <&cru SCLK_EMMC>; 282 assigned-clock-rates = <200000000>; 283 max-frequency = <150000000>; 284 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 285 clock-names = "clk_xin", "clk_ahb"; 286 clock-output-names = "emmc_cardclock"; 287 #clock-cells = <0>; 288 phys = <&emmc_phy>; 289 phy-names = "phy_arasan"; 290 power-domains = <&power RK3399_PD_EMMC>; 291 status = "disabled"; 292 }; 293 294 usb_host0_ehci: usb@fe380000 { 295 compatible = "generic-ehci"; 296 reg = <0x0 0xfe380000 0x0 0x20000>; 297 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 298 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 299 <&u2phy0>; 300 clock-names = "usbhost", "arbiter", 301 "utmi"; 302 phys = <&u2phy0_host>; 303 phy-names = "usb"; 304 power-domains = <&power RK3399_PD_PERIHP>; 305 status = "disabled"; 306 }; 307 308 usb_host0_ohci: usb@fe3a0000 { 309 compatible = "generic-ohci"; 310 reg = <0x0 0xfe3a0000 0x0 0x20000>; 311 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 312 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 313 <&u2phy0>; 314 clock-names = "usbhost", "arbiter", 315 "utmi"; 316 phys = <&u2phy0_host>; 317 phy-names = "usb"; 318 power-domains = <&power RK3399_PD_PERIHP>; 319 status = "disabled"; 320 }; 321 322 usb_host1_ehci: usb@fe3c0000 { 323 compatible = "generic-ehci"; 324 reg = <0x0 0xfe3c0000 0x0 0x20000>; 325 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 326 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 327 <&u2phy1>; 328 clock-names = "usbhost", "arbiter", 329 "utmi"; 330 phys = <&u2phy1_host>; 331 phy-names = "usb"; 332 power-domains = <&power RK3399_PD_PERIHP>; 333 status = "disabled"; 334 }; 335 336 usb_host1_ohci: usb@fe3e0000 { 337 compatible = "generic-ohci"; 338 reg = <0x0 0xfe3e0000 0x0 0x20000>; 339 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 340 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 341 <&u2phy1>; 342 clock-names = "usbhost", "arbiter", 343 "utmi"; 344 phys = <&u2phy1_host>; 345 phy-names = "usb"; 346 power-domains = <&power RK3399_PD_PERIHP>; 347 status = "disabled"; 348 }; 349 350 dwc3_typec0: usb@fe800000 { 351 compatible = "rockchip,rk3399-xhci"; 352 reg = <0x0 0xfe800000 0x0 0x100000>; 353 status = "disabled"; 354 snps,dis-enblslpm-quirk; 355 snps,phyif-utmi-bits = <16>; 356 snps,dis-u2-freeclk-exists-quirk; 357 snps,dis-u2-susphy-quirk; 358 359 #address-cells = <2>; 360 #size-cells = <2>; 361 hub { 362 compatible = "usb-hub"; 363 usb,device-class = <USB_CLASS_HUB>; 364 }; 365 typec_phy0 { 366 compatible = "rockchip,rk3399-usb3-phy"; 367 reg = <0x0 0xff7c0000 0x0 0x40000>; 368 }; 369 }; 370 371 dwc3_typec1: usb@fe900000 { 372 compatible = "rockchip,rk3399-xhci"; 373 reg = <0x0 0xfe900000 0x0 0x100000>; 374 status = "disabled"; 375 snps,dis-enblslpm-quirk; 376 snps,phyif-utmi-bits = <16>; 377 snps,dis-u2-freeclk-exists-quirk; 378 snps,dis-u2-susphy-quirk; 379 380 #address-cells = <2>; 381 #size-cells = <2>; 382 hub { 383 compatible = "usb-hub"; 384 usb,device-class = <USB_CLASS_HUB>; 385 }; 386 typec_phy1 { 387 compatible = "rockchip,rk3399-usb3-phy"; 388 reg = <0x0 0xff800000 0x0 0x40000>; 389 }; 390 }; 391 392 gic: interrupt-controller@fee00000 { 393 compatible = "arm,gic-v3"; 394 #interrupt-cells = <4>; 395 #address-cells = <2>; 396 #size-cells = <2>; 397 ranges; 398 interrupt-controller; 399 400 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 401 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 402 <0x0 0xfff00000 0 0x10000>, /* GICC */ 403 <0x0 0xfff10000 0 0x10000>, /* GICH */ 404 <0x0 0xfff20000 0 0x10000>; /* GICV */ 405 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 406 its: interrupt-controller@fee20000 { 407 compatible = "arm,gic-v3-its"; 408 msi-controller; 409 reg = <0x0 0xfee20000 0x0 0x20000>; 410 }; 411 412 ppi-partitions { 413 ppi_cluster0: interrupt-partition-0 { 414 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 415 }; 416 417 ppi_cluster1: interrupt-partition-1 { 418 affinity = <&cpu_b0 &cpu_b1>; 419 }; 420 }; 421 }; 422 423 saradc: saradc@ff100000 { 424 compatible = "rockchip,rk3399-saradc"; 425 reg = <0x0 0xff100000 0x0 0x100>; 426 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 427 #io-channel-cells = <1>; 428 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 429 clock-names = "saradc", "apb_pclk"; 430 resets = <&cru SRST_P_SARADC>; 431 reset-names = "saradc-apb"; 432 status = "disabled"; 433 }; 434 435 i2c1: i2c@ff110000 { 436 compatible = "rockchip,rk3399-i2c"; 437 reg = <0x0 0xff110000 0x0 0x1000>; 438 assigned-clocks = <&cru SCLK_I2C1>; 439 assigned-clock-rates = <200000000>; 440 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 441 clock-names = "i2c", "pclk"; 442 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&i2c1_xfer>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 status = "disabled"; 448 }; 449 450 i2c2: i2c@ff120000 { 451 compatible = "rockchip,rk3399-i2c"; 452 reg = <0x0 0xff120000 0x0 0x1000>; 453 assigned-clocks = <&cru SCLK_I2C2>; 454 assigned-clock-rates = <200000000>; 455 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 456 clock-names = "i2c", "pclk"; 457 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&i2c2_xfer>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 status = "disabled"; 463 }; 464 465 i2c3: i2c@ff130000 { 466 compatible = "rockchip,rk3399-i2c"; 467 reg = <0x0 0xff130000 0x0 0x1000>; 468 assigned-clocks = <&cru SCLK_I2C3>; 469 assigned-clock-rates = <200000000>; 470 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 471 clock-names = "i2c", "pclk"; 472 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&i2c3_xfer>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 status = "disabled"; 478 }; 479 480 i2c5: i2c@ff140000 { 481 compatible = "rockchip,rk3399-i2c"; 482 reg = <0x0 0xff140000 0x0 0x1000>; 483 assigned-clocks = <&cru SCLK_I2C5>; 484 assigned-clock-rates = <200000000>; 485 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 486 clock-names = "i2c", "pclk"; 487 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&i2c5_xfer>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 status = "disabled"; 493 }; 494 495 i2c6: i2c@ff150000 { 496 compatible = "rockchip,rk3399-i2c"; 497 reg = <0x0 0xff150000 0x0 0x1000>; 498 assigned-clocks = <&cru SCLK_I2C6>; 499 assigned-clock-rates = <200000000>; 500 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 501 clock-names = "i2c", "pclk"; 502 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 503 pinctrl-names = "default"; 504 pinctrl-0 = <&i2c6_xfer>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 status = "disabled"; 508 }; 509 510 i2c7: i2c@ff160000 { 511 compatible = "rockchip,rk3399-i2c"; 512 reg = <0x0 0xff160000 0x0 0x1000>; 513 assigned-clocks = <&cru SCLK_I2C7>; 514 assigned-clock-rates = <200000000>; 515 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 516 clock-names = "i2c", "pclk"; 517 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&i2c7_xfer>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 status = "disabled"; 523 }; 524 525 uart0: serial@ff180000 { 526 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 527 reg = <0x0 0xff180000 0x0 0x100>; 528 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 529 clock-names = "baudclk", "apb_pclk"; 530 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 531 reg-shift = <2>; 532 reg-io-width = <4>; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&uart0_xfer>; 535 status = "disabled"; 536 }; 537 538 uart1: serial@ff190000 { 539 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 540 reg = <0x0 0xff190000 0x0 0x100>; 541 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 542 clock-names = "baudclk", "apb_pclk"; 543 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 544 reg-shift = <2>; 545 reg-io-width = <4>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&uart1_xfer>; 548 status = "disabled"; 549 }; 550 551 uart2: serial@ff1a0000 { 552 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 553 reg = <0x0 0xff1a0000 0x0 0x100>; 554 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 555 clock-names = "baudclk", "apb_pclk"; 556 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 557 clock-frequency = <24000000>; 558 reg-shift = <2>; 559 reg-io-width = <4>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&uart2c_xfer>; 562 status = "disabled"; 563 }; 564 565 uart3: serial@ff1b0000 { 566 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 567 reg = <0x0 0xff1b0000 0x0 0x100>; 568 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 569 clock-names = "baudclk", "apb_pclk"; 570 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 571 reg-shift = <2>; 572 reg-io-width = <4>; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&uart3_xfer>; 575 status = "disabled"; 576 }; 577 578 spi0: spi@ff1c0000 { 579 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 580 reg = <0x0 0xff1c0000 0x0 0x1000>; 581 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 582 clock-names = "spiclk", "apb_pclk"; 583 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 spi1: spi@ff1d0000 { 592 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 593 reg = <0x0 0xff1d0000 0x0 0x1000>; 594 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 595 clock-names = "spiclk", "apb_pclk"; 596 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 spi2: spi@ff1e0000 { 605 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 606 reg = <0x0 0xff1e0000 0x0 0x1000>; 607 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 608 clock-names = "spiclk", "apb_pclk"; 609 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 status = "disabled"; 615 }; 616 617 spi4: spi@ff1f0000 { 618 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 619 reg = <0x0 0xff1f0000 0x0 0x1000>; 620 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 621 clock-names = "spiclk", "apb_pclk"; 622 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 status = "disabled"; 628 }; 629 630 spi5: spi@ff200000 { 631 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 632 reg = <0x0 0xff200000 0x0 0x1000>; 633 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 634 clock-names = "spiclk", "apb_pclk"; 635 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 636 pinctrl-names = "default"; 637 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 status = "disabled"; 641 }; 642 643 thermal_zones: thermal-zones { 644 cpu_thermal: cpu { 645 polling-delay-passive = <100>; 646 polling-delay = <1000>; 647 648 thermal-sensors = <&tsadc 0>; 649 650 trips { 651 cpu_alert0: cpu_alert0 { 652 temperature = <70000>; 653 hysteresis = <2000>; 654 type = "passive"; 655 }; 656 cpu_alert1: cpu_alert1 { 657 temperature = <75000>; 658 hysteresis = <2000>; 659 type = "passive"; 660 }; 661 cpu_crit: cpu_crit { 662 temperature = <95000>; 663 hysteresis = <2000>; 664 type = "critical"; 665 }; 666 }; 667 668 cooling-maps { 669 map0 { 670 trip = <&cpu_alert0>; 671 cooling-device = 672 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 673 }; 674 map1 { 675 trip = <&cpu_alert1>; 676 cooling-device = 677 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 678 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 679 }; 680 }; 681 }; 682 683 gpu_thermal: gpu { 684 polling-delay-passive = <100>; 685 polling-delay = <1000>; 686 687 thermal-sensors = <&tsadc 1>; 688 689 trips { 690 gpu_alert0: gpu_alert0 { 691 temperature = <75000>; 692 hysteresis = <2000>; 693 type = "passive"; 694 }; 695 gpu_crit: gpu_crit { 696 temperature = <95000>; 697 hysteresis = <2000>; 698 type = "critical"; 699 }; 700 }; 701 702 cooling-maps { 703 map0 { 704 trip = <&gpu_alert0>; 705 cooling-device = 706 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 707 }; 708 }; 709 }; 710 }; 711 712 tsadc: tsadc@ff260000 { 713 compatible = "rockchip,rk3399-tsadc"; 714 reg = <0x0 0xff260000 0x0 0x100>; 715 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 716 assigned-clocks = <&cru SCLK_TSADC>; 717 assigned-clock-rates = <750000>; 718 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 719 clock-names = "tsadc", "apb_pclk"; 720 resets = <&cru SRST_TSADC>; 721 reset-names = "tsadc-apb"; 722 rockchip,grf = <&grf>; 723 rockchip,hw-tshut-temp = <95000>; 724 pinctrl-names = "init", "default", "sleep"; 725 pinctrl-0 = <&otp_gpio>; 726 pinctrl-1 = <&otp_out>; 727 pinctrl-2 = <&otp_gpio>; 728 #thermal-sensor-cells = <1>; 729 status = "disabled"; 730 }; 731 732 qos_emmc: qos@ffa58000 { 733 compatible = "syscon"; 734 reg = <0x0 0xffa58000 0x0 0x20>; 735 }; 736 737 qos_gmac: qos@ffa5c000 { 738 compatible = "syscon"; 739 reg = <0x0 0xffa5c000 0x0 0x20>; 740 }; 741 742 qos_pcie: qos@ffa60080 { 743 compatible = "syscon"; 744 reg = <0x0 0xffa60080 0x0 0x20>; 745 }; 746 747 qos_usb_host0: qos@ffa60100 { 748 compatible = "syscon"; 749 reg = <0x0 0xffa60100 0x0 0x20>; 750 }; 751 752 qos_usb_host1: qos@ffa60180 { 753 compatible = "syscon"; 754 reg = <0x0 0xffa60180 0x0 0x20>; 755 }; 756 757 qos_usb_otg0: qos@ffa70000 { 758 compatible = "syscon"; 759 reg = <0x0 0xffa70000 0x0 0x20>; 760 }; 761 762 qos_usb_otg1: qos@ffa70080 { 763 compatible = "syscon"; 764 reg = <0x0 0xffa70080 0x0 0x20>; 765 }; 766 767 qos_sd: qos@ffa74000 { 768 compatible = "syscon"; 769 reg = <0x0 0xffa74000 0x0 0x20>; 770 }; 771 772 qos_sdioaudio: qos@ffa76000 { 773 compatible = "syscon"; 774 reg = <0x0 0xffa76000 0x0 0x20>; 775 }; 776 777 qos_hdcp: qos@ffa90000 { 778 compatible = "syscon"; 779 reg = <0x0 0xffa90000 0x0 0x20>; 780 }; 781 782 qos_iep: qos@ffa98000 { 783 compatible = "syscon"; 784 reg = <0x0 0xffa98000 0x0 0x20>; 785 }; 786 787 qos_isp0_m0: qos@ffaa0000 { 788 compatible = "syscon"; 789 reg = <0x0 0xffaa0000 0x0 0x20>; 790 }; 791 792 qos_isp0_m1: qos@ffaa0080 { 793 compatible = "syscon"; 794 reg = <0x0 0xffaa0080 0x0 0x20>; 795 }; 796 797 qos_isp1_m0: qos@ffaa8000 { 798 compatible = "syscon"; 799 reg = <0x0 0xffaa8000 0x0 0x20>; 800 }; 801 802 qos_isp1_m1: qos@ffaa8080 { 803 compatible = "syscon"; 804 reg = <0x0 0xffaa8080 0x0 0x20>; 805 }; 806 807 qos_rga_r: qos@ffab0000 { 808 compatible = "syscon"; 809 reg = <0x0 0xffab0000 0x0 0x20>; 810 }; 811 812 qos_rga_w: qos@ffab0080 { 813 compatible = "syscon"; 814 reg = <0x0 0xffab0080 0x0 0x20>; 815 }; 816 817 qos_video_m0: qos@ffab8000 { 818 compatible = "syscon"; 819 reg = <0x0 0xffab8000 0x0 0x20>; 820 }; 821 822 qos_video_m1_r: qos@ffac0000 { 823 compatible = "syscon"; 824 reg = <0x0 0xffac0000 0x0 0x20>; 825 }; 826 827 qos_video_m1_w: qos@ffac0080 { 828 compatible = "syscon"; 829 reg = <0x0 0xffac0080 0x0 0x20>; 830 }; 831 832 qos_vop_big_r: qos@ffac8000 { 833 compatible = "syscon"; 834 reg = <0x0 0xffac8000 0x0 0x20>; 835 }; 836 837 qos_vop_big_w: qos@ffac8080 { 838 compatible = "syscon"; 839 reg = <0x0 0xffac8080 0x0 0x20>; 840 }; 841 842 qos_vop_little: qos@ffad0000 { 843 compatible = "syscon"; 844 reg = <0x0 0xffad0000 0x0 0x20>; 845 }; 846 847 qos_perihp: qos@ffad8080 { 848 compatible = "syscon"; 849 reg = <0x0 0xffad8080 0x0 0x20>; 850 }; 851 852 qos_gpu: qos@ffae0000 { 853 compatible = "syscon"; 854 reg = <0x0 0xffae0000 0x0 0x20>; 855 }; 856 857 pmu: power-management@ff310000 { 858 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 859 reg = <0x0 0xff310000 0x0 0x1000>; 860 861 /* 862 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 863 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 864 * Some of the power domains are grouped together for every 865 * voltage domain. 866 * The detail contents as below. 867 */ 868 power: power-controller { 869 compatible = "rockchip,rk3399-power-controller"; 870 #power-domain-cells = <1>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 874 /* These power domains are grouped by VD_CENTER */ 875 pd_iep@RK3399_PD_IEP { 876 reg = <RK3399_PD_IEP>; 877 clocks = <&cru ACLK_IEP>, 878 <&cru HCLK_IEP>; 879 pm_qos = <&qos_iep>; 880 }; 881 pd_rga@RK3399_PD_RGA { 882 reg = <RK3399_PD_RGA>; 883 clocks = <&cru ACLK_RGA>, 884 <&cru HCLK_RGA>; 885 pm_qos = <&qos_rga_r>, 886 <&qos_rga_w>; 887 }; 888 pd_vcodec@RK3399_PD_VCODEC { 889 reg = <RK3399_PD_VCODEC>; 890 clocks = <&cru ACLK_VCODEC>, 891 <&cru HCLK_VCODEC>; 892 pm_qos = <&qos_video_m0>; 893 }; 894 pd_vdu@RK3399_PD_VDU { 895 reg = <RK3399_PD_VDU>; 896 clocks = <&cru ACLK_VDU>, 897 <&cru HCLK_VDU>; 898 pm_qos = <&qos_video_m1_r>, 899 <&qos_video_m1_w>; 900 }; 901 902 /* These power domains are grouped by VD_GPU */ 903 pd_gpu@RK3399_PD_GPU { 904 reg = <RK3399_PD_GPU>; 905 clocks = <&cru ACLK_GPU>; 906 pm_qos = <&qos_gpu>; 907 }; 908 909 /* These power domains are grouped by VD_LOGIC */ 910 pd_edp@RK3399_PD_EDP { 911 reg = <RK3399_PD_EDP>; 912 clocks = <&cru PCLK_EDP_CTRL>; 913 }; 914 pd_emmc@RK3399_PD_EMMC { 915 reg = <RK3399_PD_EMMC>; 916 clocks = <&cru ACLK_EMMC>; 917 pm_qos = <&qos_emmc>; 918 }; 919 pd_gmac@RK3399_PD_GMAC { 920 reg = <RK3399_PD_GMAC>; 921 clocks = <&cru ACLK_GMAC>, 922 <&cru PCLK_GMAC>; 923 pm_qos = <&qos_gmac>; 924 }; 925 pd_perihp@RK3399_PD_PERIHP { 926 reg = <RK3399_PD_PERIHP>; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 clocks = <&cru ACLK_PERIHP>; 930 pm_qos = <&qos_perihp>, 931 <&qos_pcie>, 932 <&qos_usb_host0>, 933 <&qos_usb_host1>; 934 935 pd_sd@RK3399_PD_SD { 936 reg = <RK3399_PD_SD>; 937 clocks = <&cru HCLK_SDMMC>, 938 <&cru SCLK_SDMMC>; 939 pm_qos = <&qos_sd>; 940 }; 941 }; 942 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 943 reg = <RK3399_PD_SDIOAUDIO>; 944 clocks = <&cru HCLK_SDIO>; 945 pm_qos = <&qos_sdioaudio>; 946 }; 947 pd_usb3@RK3399_PD_USB3 { 948 reg = <RK3399_PD_USB3>; 949 clocks = <&cru ACLK_USB3>; 950 pm_qos = <&qos_usb_otg0>, 951 <&qos_usb_otg1>; 952 }; 953 pd_vio@RK3399_PD_VIO { 954 reg = <RK3399_PD_VIO>; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 958 pd_hdcp@RK3399_PD_HDCP { 959 reg = <RK3399_PD_HDCP>; 960 clocks = <&cru ACLK_HDCP>, 961 <&cru HCLK_HDCP>, 962 <&cru PCLK_HDCP>; 963 pm_qos = <&qos_hdcp>; 964 }; 965 pd_isp0@RK3399_PD_ISP0 { 966 reg = <RK3399_PD_ISP0>; 967 clocks = <&cru ACLK_ISP0>, 968 <&cru HCLK_ISP0>; 969 pm_qos = <&qos_isp0_m0>, 970 <&qos_isp0_m1>; 971 }; 972 pd_isp1@RK3399_PD_ISP1 { 973 reg = <RK3399_PD_ISP1>; 974 clocks = <&cru ACLK_ISP1>, 975 <&cru HCLK_ISP1>; 976 pm_qos = <&qos_isp1_m0>, 977 <&qos_isp1_m1>; 978 }; 979 pd_tcpc0@RK3399_PD_TCPC0 { 980 reg = <RK3399_PD_TCPD0>; 981 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 982 <&cru SCLK_UPHY0_TCPDPHY_REF>; 983 }; 984 pd_tcpc1@RK3399_PD_TCPC1 { 985 reg = <RK3399_PD_TCPD1>; 986 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 987 <&cru SCLK_UPHY1_TCPDPHY_REF>; 988 }; 989 pd_vo@RK3399_PD_VO { 990 reg = <RK3399_PD_VO>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 994 pd_vopb@RK3399_PD_VOPB { 995 reg = <RK3399_PD_VOPB>; 996 clocks = <&cru ACLK_VOP0>, 997 <&cru HCLK_VOP0>; 998 pm_qos = <&qos_vop_big_r>, 999 <&qos_vop_big_w>; 1000 }; 1001 pd_vopl@RK3399_PD_VOPL { 1002 reg = <RK3399_PD_VOPL>; 1003 clocks = <&cru ACLK_VOP1>, 1004 <&cru HCLK_VOP1>; 1005 pm_qos = <&qos_vop_little>; 1006 }; 1007 }; 1008 }; 1009 }; 1010 }; 1011 1012 pmugrf: syscon@ff320000 { 1013 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1014 reg = <0x0 0xff320000 0x0 0x1000>; 1015 #address-cells = <1>; 1016 #size-cells = <1>; 1017 1018 pmu_io_domains: io-domains { 1019 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1020 status = "disabled"; 1021 }; 1022 }; 1023 1024 pmusgrf: syscon@ff330000 { 1025 compatible = "rockchip,rk3399-pmusgrf", "syscon"; 1026 reg = <0x0 0xff330000 0x0 0xe3d4>; 1027 }; 1028 1029 spi3: spi@ff350000 { 1030 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1031 reg = <0x0 0xff350000 0x0 0x1000>; 1032 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1033 clock-names = "spiclk", "apb_pclk"; 1034 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1035 pinctrl-names = "default"; 1036 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 status = "disabled"; 1040 }; 1041 1042 uart4: serial@ff370000 { 1043 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1044 reg = <0x0 0xff370000 0x0 0x100>; 1045 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1046 clock-names = "baudclk", "apb_pclk"; 1047 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1048 reg-shift = <2>; 1049 reg-io-width = <4>; 1050 pinctrl-names = "default"; 1051 pinctrl-0 = <&uart4_xfer>; 1052 status = "disabled"; 1053 }; 1054 1055 i2c4: i2c@ff3d0000 { 1056 compatible = "rockchip,rk3399-i2c"; 1057 reg = <0x0 0xff3d0000 0x0 0x1000>; 1058 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1059 assigned-clock-rates = <200000000>; 1060 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1061 clock-names = "i2c", "pclk"; 1062 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1063 pinctrl-names = "default"; 1064 pinctrl-0 = <&i2c4_xfer>; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 status = "disabled"; 1068 }; 1069 1070 i2c8: i2c@ff3e0000 { 1071 compatible = "rockchip,rk3399-i2c"; 1072 reg = <0x0 0xff3e0000 0x0 0x1000>; 1073 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1074 assigned-clock-rates = <200000000>; 1075 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1076 clock-names = "i2c", "pclk"; 1077 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1078 pinctrl-names = "default"; 1079 pinctrl-0 = <&i2c8_xfer>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 1085 pwm0: pwm@ff420000 { 1086 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1087 reg = <0x0 0xff420000 0x0 0x10>; 1088 #pwm-cells = <3>; 1089 pinctrl-names = "active"; 1090 pinctrl-0 = <&pwm0_pin>; 1091 clocks = <&pmucru PCLK_RKPWM_PMU>; 1092 clock-names = "pwm"; 1093 status = "disabled"; 1094 }; 1095 1096 pwm1: pwm@ff420010 { 1097 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1098 reg = <0x0 0xff420010 0x0 0x10>; 1099 #pwm-cells = <3>; 1100 pinctrl-names = "active"; 1101 pinctrl-0 = <&pwm1_pin>; 1102 clocks = <&pmucru PCLK_RKPWM_PMU>; 1103 clock-names = "pwm"; 1104 status = "disabled"; 1105 }; 1106 1107 pwm2: pwm@ff420020 { 1108 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1109 reg = <0x0 0xff420020 0x0 0x10>; 1110 #pwm-cells = <3>; 1111 pinctrl-names = "active"; 1112 pinctrl-0 = <&pwm2_pin>; 1113 clocks = <&pmucru PCLK_RKPWM_PMU>; 1114 clock-names = "pwm"; 1115 status = "disabled"; 1116 }; 1117 1118 pwm3: pwm@ff420030 { 1119 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1120 reg = <0x0 0xff420030 0x0 0x10>; 1121 #pwm-cells = <3>; 1122 pinctrl-names = "active"; 1123 pinctrl-0 = <&pwm3a_pin>; 1124 clocks = <&pmucru PCLK_RKPWM_PMU>; 1125 clock-names = "pwm"; 1126 status = "disabled"; 1127 }; 1128 1129 cic: syscon@ff620000 { 1130 compatible = "rockchip,rk3399-cic", "syscon"; 1131 reg = <0x0 0xff620000 0x0 0x100>; 1132 }; 1133 1134 dfi: dfi@ff630000 { 1135 reg = <0x00 0xff630000 0x00 0x4000>; 1136 compatible = "rockchip,rk3399-dfi"; 1137 rockchip,pmu = <&pmugrf>; 1138 clocks = <&cru PCLK_DDR_MON>; 1139 clock-names = "pclk_ddr_mon"; 1140 status = "disabled"; 1141 }; 1142 1143 dmc: dmc { 1144 compatible = "rockchip,rk3399-dmc"; 1145 devfreq-events = <&dfi>; 1146 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; 1147 clocks = <&cru SCLK_DDRCLK>; 1148 clock-names = "dmc_clk"; 1149 reg = <0x0 0xffa80000 0x0 0x0800 1150 0x0 0xffa80800 0x0 0x1800 1151 0x0 0xffa82000 0x0 0x2000 1152 0x0 0xffa84000 0x0 0x1000 1153 0x0 0xffa88000 0x0 0x0800 1154 0x0 0xffa88800 0x0 0x1800 1155 0x0 0xffa8a000 0x0 0x2000 1156 0x0 0xffa8c000 0x0 0x1000>; 1157 }; 1158 1159 efuse0: efuse@ff690000 { 1160 compatible = "rockchip,rk3399-efuse"; 1161 reg = <0x0 0xff690000 0x0 0x80>; 1162 #address-cells = <1>; 1163 #size-cells = <1>; 1164 clocks = <&cru PCLK_EFUSE1024NS>; 1165 clock-names = "pclk_efuse"; 1166 1167 /* Data cells */ 1168 cpu_id: cpu-id@7 { 1169 reg = <0x07 0x10>; 1170 }; 1171 cpub_leakage: cpu-leakage@17 { 1172 reg = <0x17 0x1>; 1173 }; 1174 gpu_leakage: gpu-leakage@18 { 1175 reg = <0x18 0x1>; 1176 }; 1177 center_leakage: center-leakage@19 { 1178 reg = <0x19 0x1>; 1179 }; 1180 cpul_leakage: cpu-leakage@1a { 1181 reg = <0x1a 0x1>; 1182 }; 1183 logic_leakage: logic-leakage@1b { 1184 reg = <0x1b 0x1>; 1185 }; 1186 wafer_info: wafer-info@1c { 1187 reg = <0x1c 0x1>; 1188 }; 1189 }; 1190 1191 pmucru: pmu-clock-controller@ff750000 { 1192 compatible = "rockchip,rk3399-pmucru"; 1193 reg = <0x0 0xff750000 0x0 0x1000>; 1194 rockchip,grf = <&pmugrf>; 1195 #clock-cells = <1>; 1196 #reset-cells = <1>; 1197 assigned-clocks = <&pmucru PLL_PPLL>; 1198 assigned-clock-rates = <676000000>; 1199 }; 1200 1201 cru: clock-controller@ff760000 { 1202 compatible = "rockchip,rk3399-cru"; 1203 reg = <0x0 0xff760000 0x0 0x1000>; 1204 rockchip,grf = <&grf>; 1205 #clock-cells = <1>; 1206 #reset-cells = <1>; 1207 assigned-clocks = 1208 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1209 <&cru PLL_NPLL>, 1210 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1211 <&cru PCLK_PERIHP>, 1212 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1213 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1214 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1215 assigned-clock-rates = 1216 <594000000>, <800000000>, 1217 <1000000000>, 1218 <150000000>, <75000000>, 1219 <37500000>, 1220 <100000000>, <100000000>, 1221 <50000000>, <600000000>, 1222 <100000000>, <50000000>; 1223 }; 1224 1225 grf: syscon@ff770000 { 1226 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1227 reg = <0x0 0xff770000 0x0 0x10000>; 1228 #address-cells = <1>; 1229 #size-cells = <1>; 1230 1231 io_domains: io-domains { 1232 compatible = "rockchip,rk3399-io-voltage-domain"; 1233 status = "disabled"; 1234 }; 1235 1236 u2phy0: usb2-phy@e450 { 1237 compatible = "rockchip,rk3399-usb2phy"; 1238 reg = <0xe450 0x10>; 1239 clocks = <&cru SCLK_USB2PHY0_REF>; 1240 clock-names = "phyclk"; 1241 #clock-cells = <0>; 1242 clock-output-names = "clk_usbphy0_480m"; 1243 status = "disabled"; 1244 1245 u2phy0_host: host-port { 1246 #phy-cells = <0>; 1247 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1248 interrupt-names = "linestate"; 1249 status = "disabled"; 1250 }; 1251 1252 u2phy0_otg: otg-port { 1253 #phy-cells = <0>; 1254 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1255 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1256 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1257 interrupt-names = "otg-bvalid", "otg-id", 1258 "linestate"; 1259 status = "disabled"; 1260 }; 1261 }; 1262 1263 u2phy1: usb2-phy@e460 { 1264 compatible = "rockchip,rk3399-usb2phy"; 1265 reg = <0xe460 0x10>; 1266 clocks = <&cru SCLK_USB2PHY1_REF>; 1267 clock-names = "phyclk"; 1268 #clock-cells = <0>; 1269 clock-output-names = "clk_usbphy1_480m"; 1270 status = "disabled"; 1271 1272 u2phy1_host: host-port { 1273 #phy-cells = <0>; 1274 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1275 interrupt-names = "linestate"; 1276 status = "disabled"; 1277 }; 1278 1279 u2phy1_otg: otg-port { 1280 #phy-cells = <0>; 1281 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1282 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1283 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1284 interrupt-names = "otg-bvalid", "otg-id", 1285 "linestate"; 1286 status = "disabled"; 1287 }; 1288 }; 1289 1290 emmc_phy: phy@f780 { 1291 compatible = "rockchip,rk3399-emmc-phy"; 1292 reg = <0xf780 0x24>; 1293 clocks = <&sdhci>; 1294 clock-names = "emmcclk"; 1295 #phy-cells = <0>; 1296 status = "disabled"; 1297 }; 1298 1299 pcie_phy: pcie-phy { 1300 compatible = "rockchip,rk3399-pcie-phy"; 1301 clocks = <&cru SCLK_PCIEPHY_REF>; 1302 clock-names = "refclk"; 1303 #phy-cells = <0>; 1304 resets = <&cru SRST_PCIEPHY>; 1305 reset-names = "phy"; 1306 status = "disabled"; 1307 }; 1308 }; 1309 1310 watchdog@ff848000 { 1311 compatible = "snps,dw-wdt"; 1312 reg = <0x0 0xff848000 0x0 0x100>; 1313 clocks = <&cru PCLK_WDT>; 1314 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1315 }; 1316 1317 rktimer: rktimer@ff850000 { 1318 compatible = "rockchip,rk3399-timer"; 1319 reg = <0x0 0xff850000 0x0 0x1000>; 1320 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1321 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1322 clock-names = "pclk", "timer"; 1323 }; 1324 1325 spdif: spdif@ff870000 { 1326 compatible = "rockchip,rk3399-spdif"; 1327 reg = <0x0 0xff870000 0x0 0x1000>; 1328 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1329 dmas = <&dmac_bus 7>; 1330 dma-names = "tx"; 1331 clock-names = "mclk", "hclk"; 1332 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&spdif_bus>; 1335 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1336 status = "disabled"; 1337 }; 1338 1339 i2s0: i2s@ff880000 { 1340 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1341 reg = <0x0 0xff880000 0x0 0x1000>; 1342 rockchip,grf = <&grf>; 1343 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1344 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1345 dma-names = "tx", "rx"; 1346 clock-names = "i2s_clk", "i2s_hclk"; 1347 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&i2s0_8ch_bus>; 1350 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1351 status = "disabled"; 1352 }; 1353 1354 i2s1: i2s@ff890000 { 1355 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1356 reg = <0x0 0xff890000 0x0 0x1000>; 1357 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1358 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1359 dma-names = "tx", "rx"; 1360 clock-names = "i2s_clk", "i2s_hclk"; 1361 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1362 pinctrl-names = "default"; 1363 pinctrl-0 = <&i2s1_2ch_bus>; 1364 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1365 status = "disabled"; 1366 }; 1367 1368 i2s2: i2s@ff8a0000 { 1369 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1370 reg = <0x0 0xff8a0000 0x0 0x1000>; 1371 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1372 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1373 dma-names = "tx", "rx"; 1374 clock-names = "i2s_clk", "i2s_hclk"; 1375 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1376 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1377 status = "disabled"; 1378 }; 1379 1380 i2c0: i2c@ff3c0000 { 1381 compatible = "rockchip,rk3399-i2c"; 1382 reg = <0x0 0xff3c0000 0x0 0x1000>; 1383 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1384 assigned-clock-rates = <200000000>; 1385 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1386 clock-names = "i2c", "pclk"; 1387 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1388 pinctrl-names = "default"; 1389 pinctrl-0 = <&i2c0_xfer>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 status = "disabled"; 1393 }; 1394 1395 vopl: vop@ff8f0000 { 1396 compatible = "rockchip,rk3399-vop-lit"; 1397 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1398 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1399 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1400 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1401 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1402 reset-names = "axi", "ahb", "dclk"; 1403 status = "disabled"; 1404 vopl_out: port { 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 vopl_out_mipi: endpoint@0 { 1408 reg = <3>; 1409 remote-endpoint = <&mipi_in_vopl>; 1410 }; 1411 1412 vopl_out_hdmi: endpoint@1 { 1413 reg = <1>; 1414 remote-endpoint = <&hdmi_in_vopl>; 1415 }; 1416 }; 1417 }; 1418 1419 vopb: vop@ff900000 { 1420 compatible = "rockchip,rk3399-vop-big"; 1421 reg = <0x0 0xff900000 0x0 0x3efc>; 1422 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1423 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1424 #clock-cells = <0>; 1425 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1426 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1427 reset-names = "axi", "ahb", "dclk"; 1428 status = "disabled"; 1429 vopb_out: port { 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 vopb_out_mipi: endpoint@0 { 1433 reg = <3>; 1434 remote-endpoint = <&mipi_in_vopb>; 1435 }; 1436 1437 vopb_out_hdmi: endpoint@1 { 1438 reg = <1>; 1439 remote-endpoint = <&hdmi_in_vopb>; 1440 }; 1441 }; 1442 }; 1443 1444 hdmi: hdmi@ff940000 { 1445 compatible = "rockchip,rk3399-dw-hdmi"; 1446 reg = <0x0 0xff940000 0x0 0x20000>; 1447 reg-io-width = <4>; 1448 rockchip,grf = <&grf>; 1449 pinctrl-names = "default"; 1450 pinctrl-0 = <&hdmi_i2c_xfer>; 1451 power-domains = <&power RK3399_PD_HDCP>; 1452 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1453 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; 1454 clock-names = "iahb", "isfr", "vpll", "grf"; 1455 status = "disabled"; 1456 1457 ports { 1458 hdmi_in: port { 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 hdmi_in_vopb: endpoint@0 { 1462 reg = <0>; 1463 remote-endpoint = <&vopb_out_hdmi>; 1464 }; 1465 hdmi_in_vopl: endpoint@1 { 1466 reg = <1>; 1467 remote-endpoint = <&vopl_out_hdmi>; 1468 }; 1469 }; 1470 }; 1471 }; 1472 1473 mipi_dsi: mipi@ff960000 { 1474 compatible = "rockchip,rk3399_mipi_dsi"; 1475 reg = <0x0 0xff960000 0x0 0x8000>; 1476 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1477 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, 1478 <&cru SCLK_DPHY_TX0_CFG>; 1479 clock-names = "ref", "pclk", "phy_cfg"; 1480 rockchip,grf = <&grf>; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 status = "disabled"; 1484 ports { 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 reg = <1>; 1488 mipi_in: port { 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 mipi_in_vopb: endpoint@0 { 1492 reg = <0>; 1493 remote-endpoint = <&vopb_out_mipi>; 1494 }; 1495 mipi_in_vopl: endpoint@1 { 1496 reg = <1>; 1497 remote-endpoint = <&vopl_out_mipi>; 1498 }; 1499 }; 1500 }; 1501 }; 1502 1503 pinctrl: pinctrl { 1504 compatible = "rockchip,rk3399-pinctrl"; 1505 rockchip,grf = <&grf>; 1506 rockchip,pmu = <&pmugrf>; 1507 #address-cells = <2>; 1508 #size-cells = <2>; 1509 ranges; 1510 1511 gpio0: gpio0@ff720000 { 1512 compatible = "rockchip,gpio-bank"; 1513 reg = <0x0 0xff720000 0x0 0x100>; 1514 clocks = <&pmucru PCLK_GPIO0_PMU>; 1515 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1516 1517 gpio-controller; 1518 #gpio-cells = <0x2>; 1519 1520 interrupt-controller; 1521 #interrupt-cells = <0x2>; 1522 }; 1523 1524 gpio1: gpio1@ff730000 { 1525 compatible = "rockchip,gpio-bank"; 1526 reg = <0x0 0xff730000 0x0 0x100>; 1527 clocks = <&pmucru PCLK_GPIO1_PMU>; 1528 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1529 1530 gpio-controller; 1531 #gpio-cells = <0x2>; 1532 1533 interrupt-controller; 1534 #interrupt-cells = <0x2>; 1535 }; 1536 1537 gpio2: gpio2@ff780000 { 1538 compatible = "rockchip,gpio-bank"; 1539 reg = <0x0 0xff780000 0x0 0x100>; 1540 clocks = <&cru PCLK_GPIO2>; 1541 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1542 1543 gpio-controller; 1544 #gpio-cells = <0x2>; 1545 1546 interrupt-controller; 1547 #interrupt-cells = <0x2>; 1548 }; 1549 1550 gpio3: gpio3@ff788000 { 1551 compatible = "rockchip,gpio-bank"; 1552 reg = <0x0 0xff788000 0x0 0x100>; 1553 clocks = <&cru PCLK_GPIO3>; 1554 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1555 1556 gpio-controller; 1557 #gpio-cells = <0x2>; 1558 1559 interrupt-controller; 1560 #interrupt-cells = <0x2>; 1561 }; 1562 1563 gpio4: gpio4@ff790000 { 1564 compatible = "rockchip,gpio-bank"; 1565 reg = <0x0 0xff790000 0x0 0x100>; 1566 clocks = <&cru PCLK_GPIO4>; 1567 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1568 1569 gpio-controller; 1570 #gpio-cells = <0x2>; 1571 1572 interrupt-controller; 1573 #interrupt-cells = <0x2>; 1574 }; 1575 1576 pcfg_pull_up: pcfg-pull-up { 1577 bias-pull-up; 1578 }; 1579 1580 pcfg_pull_down: pcfg-pull-down { 1581 bias-pull-down; 1582 }; 1583 1584 pcfg_pull_none: pcfg-pull-none { 1585 bias-disable; 1586 }; 1587 1588 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1589 bias-disable; 1590 drive-strength = <12>; 1591 }; 1592 1593 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1594 bias-pull-up; 1595 drive-strength = <8>; 1596 }; 1597 1598 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1599 bias-pull-down; 1600 drive-strength = <4>; 1601 }; 1602 1603 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1604 bias-pull-up; 1605 drive-strength = <2>; 1606 }; 1607 1608 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1609 bias-pull-down; 1610 drive-strength = <12>; 1611 }; 1612 1613 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1614 bias-disable; 1615 drive-strength = <13>; 1616 }; 1617 1618 clock { 1619 clk_32k: clk-32k { 1620 rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>; 1621 }; 1622 }; 1623 1624 edp { 1625 edp_hpd: edp-hpd { 1626 rockchip,pins = 1627 <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1628 }; 1629 }; 1630 1631 gmac { 1632 rgmii_pins: rgmii-pins { 1633 rockchip,pins = 1634 /* mac_txclk */ 1635 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1636 /* mac_rxclk */ 1637 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1638 /* mac_mdio */ 1639 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1640 /* mac_txen */ 1641 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1642 /* mac_clk */ 1643 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1644 /* mac_rxdv */ 1645 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1646 /* mac_mdc */ 1647 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1648 /* mac_rxd1 */ 1649 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1650 /* mac_rxd0 */ 1651 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1652 /* mac_txd1 */ 1653 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1654 /* mac_txd0 */ 1655 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1656 /* mac_rxd3 */ 1657 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1658 /* mac_rxd2 */ 1659 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1660 /* mac_txd3 */ 1661 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1662 /* mac_txd2 */ 1663 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>; 1664 }; 1665 1666 rmii_pins: rmii-pins { 1667 rockchip,pins = 1668 /* mac_mdio */ 1669 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1670 /* mac_txen */ 1671 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1672 /* mac_clk */ 1673 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1674 /* mac_rxer */ 1675 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1676 /* mac_rxdv */ 1677 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1678 /* mac_mdc */ 1679 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1680 /* mac_rxd1 */ 1681 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1682 /* mac_rxd0 */ 1683 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1684 /* mac_txd1 */ 1685 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1686 /* mac_txd0 */ 1687 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>; 1688 }; 1689 }; 1690 1691 i2c0 { 1692 i2c0_xfer: i2c0-xfer { 1693 rockchip,pins = 1694 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, 1695 <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1696 }; 1697 }; 1698 1699 i2c1 { 1700 i2c1_xfer: i2c1-xfer { 1701 rockchip,pins = 1702 <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1703 <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1704 }; 1705 }; 1706 1707 i2c2 { 1708 i2c2_xfer: i2c2-xfer { 1709 rockchip,pins = 1710 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 1711 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>; 1712 }; 1713 }; 1714 1715 i2c3 { 1716 i2c3_xfer: i2c3-xfer { 1717 rockchip,pins = 1718 <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1719 <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1720 }; 1721 }; 1722 1723 i2c4 { 1724 i2c4_xfer: i2c4-xfer { 1725 rockchip,pins = 1726 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1727 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1728 }; 1729 }; 1730 1731 i2c5 { 1732 i2c5_xfer: i2c5-xfer { 1733 rockchip,pins = 1734 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>, 1735 <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 1736 }; 1737 }; 1738 1739 i2c6 { 1740 i2c6_xfer: i2c6-xfer { 1741 rockchip,pins = 1742 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>, 1743 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1744 }; 1745 }; 1746 1747 i2c7 { 1748 i2c7_xfer: i2c7-xfer { 1749 rockchip,pins = 1750 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>, 1751 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1752 }; 1753 }; 1754 1755 i2c8 { 1756 i2c8_xfer: i2c8-xfer { 1757 rockchip,pins = 1758 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, 1759 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1760 }; 1761 }; 1762 1763 i2s0 { 1764 i2s0_8ch_bus: i2s0-8ch-bus { 1765 rockchip,pins = 1766 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>, 1767 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 1768 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 1769 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, 1770 <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>, 1771 <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>, 1772 <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>, 1773 <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>, 1774 <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; 1775 }; 1776 }; 1777 1778 i2s1 { 1779 i2s1_2ch_bus: i2s1-2ch-bus { 1780 rockchip,pins = 1781 <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1782 <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1783 <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1784 <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1785 <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 1786 }; 1787 }; 1788 1789 sdio0 { 1790 sdio0_bus1: sdio0-bus1 { 1791 rockchip,pins = 1792 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1793 }; 1794 1795 sdio0_bus4: sdio0-bus4 { 1796 rockchip,pins = 1797 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 1798 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 1799 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1800 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 1801 }; 1802 1803 sdio0_cmd: sdio0-cmd { 1804 rockchip,pins = 1805 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 1806 }; 1807 1808 sdio0_clk: sdio0-clk { 1809 rockchip,pins = 1810 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 1811 }; 1812 1813 sdio0_cd: sdio0-cd { 1814 rockchip,pins = 1815 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 1816 }; 1817 1818 sdio0_pwr: sdio0-pwr { 1819 rockchip,pins = 1820 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 1821 }; 1822 1823 sdio0_bkpwr: sdio0-bkpwr { 1824 rockchip,pins = 1825 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 1826 }; 1827 1828 sdio0_wp: sdio0-wp { 1829 rockchip,pins = 1830 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 1831 }; 1832 1833 sdio0_int: sdio0-int { 1834 rockchip,pins = 1835 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 1836 }; 1837 }; 1838 1839 sdmmc { 1840 sdmmc_bus1: sdmmc-bus1 { 1841 rockchip,pins = 1842 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 1843 }; 1844 1845 sdmmc_bus4: sdmmc-bus4 { 1846 rockchip,pins = 1847 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 1848 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 1849 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1850 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 1851 }; 1852 1853 sdmmc_clk: sdmmc-clk { 1854 rockchip,pins = 1855 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1856 }; 1857 1858 sdmmc_cmd: sdmmc-cmd { 1859 rockchip,pins = 1860 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 1861 }; 1862 1863 sdmmc_cd: sdmcc-cd { 1864 rockchip,pins = 1865 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 1866 }; 1867 1868 sdmmc_wp: sdmmc-wp { 1869 rockchip,pins = 1870 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 1871 }; 1872 }; 1873 1874 sleep { 1875 ap_pwroff: ap-pwroff { 1876 rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 1877 }; 1878 1879 ddrio_pwroff: ddrio-pwroff { 1880 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1881 }; 1882 }; 1883 1884 spdif { 1885 spdif_bus: spdif-bus { 1886 rockchip,pins = 1887 <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1888 }; 1889 1890 spdif_bus_1: spdif-bus-1 { 1891 rockchip,pins = 1892 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 1893 }; 1894 }; 1895 1896 spi0 { 1897 spi0_clk: spi0-clk { 1898 rockchip,pins = 1899 <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>; 1900 }; 1901 spi0_cs0: spi0-cs0 { 1902 rockchip,pins = 1903 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 1904 }; 1905 spi0_cs1: spi0-cs1 { 1906 rockchip,pins = 1907 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 1908 }; 1909 spi0_tx: spi0-tx { 1910 rockchip,pins = 1911 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>; 1912 }; 1913 spi0_rx: spi0-rx { 1914 rockchip,pins = 1915 <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>; 1916 }; 1917 }; 1918 1919 spi1 { 1920 spi1_clk: spi1-clk { 1921 rockchip,pins = 1922 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>; 1923 }; 1924 spi1_cs0: spi1-cs0 { 1925 rockchip,pins = 1926 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>; 1927 }; 1928 spi1_rx: spi1-rx { 1929 rockchip,pins = 1930 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 1931 }; 1932 spi1_tx: spi1-tx { 1933 rockchip,pins = 1934 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 1935 }; 1936 }; 1937 1938 spi2 { 1939 spi2_clk: spi2-clk { 1940 rockchip,pins = 1941 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 1942 }; 1943 spi2_cs0: spi2-cs0 { 1944 rockchip,pins = 1945 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>; 1946 }; 1947 spi2_rx: spi2-rx { 1948 rockchip,pins = 1949 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>; 1950 }; 1951 spi2_tx: spi2-tx { 1952 rockchip,pins = 1953 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>; 1954 }; 1955 }; 1956 1957 spi3 { 1958 spi3_clk: spi3-clk { 1959 rockchip,pins = 1960 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>; 1961 }; 1962 spi3_cs0: spi3-cs0 { 1963 rockchip,pins = 1964 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>; 1965 }; 1966 spi3_rx: spi3-rx { 1967 rockchip,pins = 1968 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>; 1969 }; 1970 spi3_tx: spi3-tx { 1971 rockchip,pins = 1972 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>; 1973 }; 1974 }; 1975 1976 spi4 { 1977 spi4_clk: spi4-clk { 1978 rockchip,pins = 1979 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>; 1980 }; 1981 spi4_cs0: spi4-cs0 { 1982 rockchip,pins = 1983 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>; 1984 }; 1985 spi4_rx: spi4-rx { 1986 rockchip,pins = 1987 <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>; 1988 }; 1989 spi4_tx: spi4-tx { 1990 rockchip,pins = 1991 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>; 1992 }; 1993 }; 1994 1995 spi5 { 1996 spi5_clk: spi5-clk { 1997 rockchip,pins = 1998 <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>; 1999 }; 2000 spi5_cs0: spi5-cs0 { 2001 rockchip,pins = 2002 <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>; 2003 }; 2004 spi5_rx: spi5-rx { 2005 rockchip,pins = 2006 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>; 2007 }; 2008 spi5_tx: spi5-tx { 2009 rockchip,pins = 2010 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>; 2011 }; 2012 }; 2013 2014 tsadc { 2015 otp_gpio: otp-gpio { 2016 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2017 }; 2018 2019 otp_out: otp-out { 2020 rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2021 }; 2022 }; 2023 2024 uart0 { 2025 uart0_xfer: uart0-xfer { 2026 rockchip,pins = 2027 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>, 2028 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2029 }; 2030 2031 uart0_cts: uart0-cts { 2032 rockchip,pins = 2033 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2034 }; 2035 2036 uart0_rts: uart0-rts { 2037 rockchip,pins = 2038 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2039 }; 2040 }; 2041 2042 uart1 { 2043 uart1_xfer: uart1-xfer { 2044 rockchip,pins = 2045 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 2046 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 2047 }; 2048 }; 2049 2050 uart2a { 2051 uart2a_xfer: uart2a-xfer { 2052 rockchip,pins = 2053 <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>, 2054 <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2055 }; 2056 }; 2057 2058 uart2b { 2059 uart2b_xfer: uart2b-xfer { 2060 rockchip,pins = 2061 <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 2062 <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 2063 }; 2064 }; 2065 2066 uart2c { 2067 uart2c_xfer: uart2c-xfer { 2068 rockchip,pins = 2069 <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>, 2070 <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 2071 }; 2072 }; 2073 2074 uart3 { 2075 uart3_xfer: uart3-xfer { 2076 rockchip,pins = 2077 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 2078 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 2079 }; 2080 2081 uart3_cts: uart3-cts { 2082 rockchip,pins = 2083 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2084 }; 2085 2086 uart3_rts: uart3-rts { 2087 rockchip,pins = 2088 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 2089 }; 2090 }; 2091 2092 uart4 { 2093 uart4_xfer: uart4-xfer { 2094 rockchip,pins = 2095 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>, 2096 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 2097 }; 2098 }; 2099 2100 uarthdcp { 2101 uarthdcp_xfer: uarthdcp-xfer { 2102 rockchip,pins = 2103 <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>, 2104 <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 2105 }; 2106 }; 2107 2108 pwm0 { 2109 pwm0_pin: pwm0-pin { 2110 rockchip,pins = 2111 <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2112 }; 2113 2114 vop0_pwm_pin: vop0-pwm-pin { 2115 rockchip,pins = 2116 <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2117 }; 2118 }; 2119 2120 pwm1 { 2121 pwm1_pin: pwm1-pin { 2122 rockchip,pins = 2123 <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 2124 }; 2125 2126 vop1_pwm_pin: vop1-pwm-pin { 2127 rockchip,pins = 2128 <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2129 }; 2130 }; 2131 2132 pwm2 { 2133 pwm2_pin: pwm2-pin { 2134 rockchip,pins = 2135 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2136 }; 2137 }; 2138 2139 pwm3a { 2140 pwm3a_pin: pwm3a-pin { 2141 rockchip,pins = 2142 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2143 }; 2144 }; 2145 2146 pwm3b { 2147 pwm3b_pin: pwm3b-pin { 2148 rockchip,pins = 2149 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 2150 }; 2151 }; 2152 2153 hdmi { 2154 hdmi_i2c_xfer: hdmi-i2c-xfer { 2155 rockchip,pins = 2156 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2157 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2158 }; 2159 2160 hdmi_cec: hdmi-cec { 2161 rockchip,pins = 2162 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2163 }; 2164 }; 2165 2166 pcie { 2167 pcie_clkreqn: pci-clkreqn { 2168 rockchip,pins = 2169 <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>; 2170 }; 2171 2172 pcie_clkreqnb: pci-clkreqnb { 2173 rockchip,pins = 2174 <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 2175 }; 2176 2177 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2178 rockchip,pins = 2179 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2180 }; 2181 2182 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2183 rockchip,pins = 2184 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2185 }; 2186 }; 2187 2188 }; 2189}; 2190