1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3328-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3328"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 mmc0 = &emmc; 29 mmc1 = &sdmmc; 30 mmc2 = &sdmmc_ext; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42// clocks = <&cru ARMCLK>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 }; 45 cpu1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 reg = <0x0 0x1>; 49 enable-method = "psci"; 50 }; 51 cpu2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 reg = <0x0 0x2>; 55 enable-method = "psci"; 56 }; 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x3>; 61 enable-method = "psci"; 62 }; 63 }; 64 65 cpu0_opp_table: opp_table0 { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp@408000000 { 70 opp-hz = /bits/ 64 <408000000>; 71 opp-microvolt = <950000>; 72 clock-latency-ns = <40000>; 73 opp-suspend; 74 }; 75 opp@600000000 { 76 opp-hz = /bits/ 64 <600000000>; 77 opp-microvolt = <950000>; 78 clock-latency-ns = <40000>; 79 }; 80 opp@816000000 { 81 opp-hz = /bits/ 64 <816000000>; 82 opp-microvolt = <1000000>; 83 clock-latency-ns = <40000>; 84 }; 85 opp@1008000000 { 86 opp-hz = /bits/ 64 <1008000000>; 87 opp-microvolt = <1100000>; 88 clock-latency-ns = <40000>; 89 }; 90 opp@1200000000 { 91 opp-hz = /bits/ 64 <1200000000>; 92 opp-microvolt = <1225000>; 93 clock-latency-ns = <40000>; 94 }; 95 opp@1296000000 { 96 opp-hz = /bits/ 64 <1296000000>; 97 opp-microvolt = <1300000>; 98 clock-latency-ns = <40000>; 99 }; 100 }; 101 102 arm-pmu { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 109 }; 110 111 psci { 112 compatible = "arm,psci-1.0"; 113 method = "smc"; 114 }; 115 116 timer { 117 compatible = "arm,armv8-timer"; 118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 122 }; 123 124 xin24m: xin24m { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <24000000>; 128 clock-output-names = "xin24m"; 129 }; 130 131 i2s0: i2s@ff000000 { 132 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 133 reg = <0x0 0xff000000 0x0 0x1000>; 134 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 136 clock-names = "i2s_clk", "i2s_hclk"; 137 dmas = <&dmac 11>, <&dmac 12>; 138 #dma-cells = <2>; 139 dma-names = "tx", "rx"; 140 status = "disabled"; 141 }; 142 143 i2s1: i2s@ff010000 { 144 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 145 reg = <0x0 0xff010000 0x0 0x1000>; 146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 148 clock-names = "i2s_clk", "i2s_hclk"; 149 dmas = <&dmac 14>, <&dmac 15>; 150 #dma-cells = <2>; 151 dma-names = "tx", "rx"; 152 status = "disabled"; 153 }; 154 155 i2s2: i2s@ff020000 { 156 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 157 reg = <0x0 0xff020000 0x0 0x1000>; 158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 160 clock-names = "i2s_clk", "i2s_hclk"; 161 dmas = <&dmac 0>, <&dmac 1>; 162 #dma-cells = <2>; 163 dma-names = "tx", "rx"; 164 pinctrl-names = "default", "sleep"; 165 pinctrl-0 = <&i2s2m0_mclk 166 &i2s2m0_sclk 167 &i2s2m0_lrcktx 168 &i2s2m0_lrckrx 169 &i2s2m0_sdo 170 &i2s2m0_sdi>; 171 pinctrl-1 = <&i2s2m0_sleep>; 172 status = "disabled"; 173 }; 174 175 spdif: spdif@ff030000 { 176 compatible = "rockchip,rk3328-spdif"; 177 reg = <0x0 0xff030000 0x0 0x1000>; 178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 180 clock-names = "mclk", "hclk"; 181 dmas = <&dmac 10>; 182 #dma-cells = <1>; 183 dma-names = "tx"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&spdifm2_tx>; 186 status = "disabled"; 187 }; 188 189 grf: syscon@ff100000 { 190 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 191 reg = <0x0 0xff100000 0x0 0x1000>; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 195 io_domains: io-domains { 196 compatible = "rockchip,rk3328-io-voltage-domain"; 197 status = "disabled"; 198 }; 199 }; 200 201 uart0: serial@ff110000 { 202 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 203 reg = <0x0 0xff110000 0x0 0x100>; 204 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 206 clock-names = "baudclk", "apb_pclk"; 207 reg-shift = <2>; 208 reg-io-width = <4>; 209 dmas = <&dmac 2>, <&dmac 3>; 210 #dma-cells = <2>; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 213 status = "disabled"; 214 }; 215 216 uart1: serial@ff120000 { 217 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 218 reg = <0x0 0xff120000 0x0 0x100>; 219 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 221 clock-names = "sclk_uart", "pclk_uart"; 222 reg-shift = <2>; 223 reg-io-width = <4>; 224 dmas = <&dmac 4>, <&dmac 5>; 225 #dma-cells = <2>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 228 status = "disabled"; 229 }; 230 231 uart2: serial@ff130000 { 232 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 233 reg = <0x0 0xff130000 0x0 0x100>; 234 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 236 clock-names = "baudclk", "apb_pclk"; 237 clock-frequency = <24000000>; 238 reg-shift = <2>; 239 reg-io-width = <4>; 240 dmas = <&dmac 6>, <&dmac 7>; 241 #dma-cells = <2>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&uart2m1_xfer>; 244 status = "disabled"; 245 }; 246 247 pmu: power-management@ff140000 { 248 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; 249 reg = <0x0 0xff140000 0x0 0x1000>; 250 }; 251 252 i2c0: i2c@ff150000 { 253 compatible = "rockchip,rk3328-i2c"; 254 reg = <0x0 0xff150000 0x0 0x1000>; 255 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 259 clock-names = "i2c", "pclk"; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&i2c0_xfer>; 262 status = "disabled"; 263 }; 264 265 i2c1: i2c@ff160000 { 266 compatible = "rockchip,rk3328-i2c"; 267 reg = <0x0 0xff160000 0x0 0x1000>; 268 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 272 clock-names = "i2c", "pclk"; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&i2c1_xfer>; 275 status = "disabled"; 276 }; 277 278 i2c2: i2c@ff170000 { 279 compatible = "rockchip,rk3328-i2c"; 280 reg = <0x0 0xff170000 0x0 0x1000>; 281 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 285 clock-names = "i2c", "pclk"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&i2c2_xfer>; 288 status = "disabled"; 289 }; 290 291 i2c3: i2c@ff180000 { 292 compatible = "rockchip,rk3328-i2c"; 293 reg = <0x0 0xff180000 0x0 0x1000>; 294 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 298 clock-names = "i2c", "pclk"; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&i2c3_xfer>; 301 status = "disabled"; 302 }; 303 304 spi0: spi@ff190000 { 305 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 306 reg = <0x0 0xff190000 0x0 0x1000>; 307 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 311 clock-names = "spiclk", "apb_pclk"; 312 dmas = <&dmac 8>, <&dmac 9>; 313 #dma-cells = <2>; 314 dma-names = "tx", "rx"; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 317 status = "disabled"; 318 }; 319 320 wdt: watchdog@ff1a0000 { 321 compatible = "snps,dw-wdt"; 322 reg = <0x0 0xff1a0000 0x0 0x100>; 323 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 324 status = "disabled"; 325 }; 326 327 amba { 328 compatible = "simple-bus"; 329 #address-cells = <2>; 330 #size-cells = <2>; 331 ranges; 332 333 dmac: dmac@ff1f0000 { 334 compatible = "arm,pl330", "arm,primecell"; 335 reg = <0x0 0xff1f0000 0x0 0x4000>; 336 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cru ACLK_DMAC>; 339 clock-names = "apb_pclk"; 340 #dma-cells = <1>; 341 }; 342 }; 343 344 saradc: saradc@ff280000 { 345 compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; 346 reg = <0x0 0xff280000 0x0 0x100>; 347 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 348 #io-channel-cells = <1>; 349 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 350 clock-names = "saradc", "apb_pclk"; 351 resets = <&cru SRST_SARADC_P>; 352 reset-names = "saradc-apb"; 353 status = "disabled"; 354 }; 355 356 dmc: dmc { 357 compatible = "rockchip,rk3328-dmc"; 358 reg = <0x0 0xff400000 0x0 0x1000 359 0x0 0xff780000 0x0 0x3000 360 0x0 0xff100000 0x0 0x1000 361 0x0 0xff440000 0x0 0x1000 362 0x0 0xff720000 0x0 0x1000 363 0x0 0xff798000 0x0 0x1000>; 364 }; 365 366 cru: clock-controller@ff440000 { 367 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 368 reg = <0x0 0xff440000 0x0 0x1000>; 369 rockchip,grf = <&grf>; 370 #clock-cells = <1>; 371 #reset-cells = <1>; 372 assigned-clocks = 373 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 374 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 375 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 376 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 377 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 378 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 379 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 380 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 381 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 382 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 383 <&cru SCLK_WIFI>, <&cru ARMCLK>, 384 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 385 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 386 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 387 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 388 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, 389 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, 390 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 391 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 392 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 393 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 394 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, 395 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 396 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; 397 assigned-clock-parents = 398 <&cru HDMIPHY>, <&cru PLL_APLL>, 399 <&cru PLL_GPLL>, <&xin24m>, 400 <&xin24m>, <&xin24m>; 401 assigned-clock-rates = 402 <0>, <61440000>, 403 <0>, <24000000>, 404 <24000000>, <24000000>, 405 <15000000>, <15000000>, 406 <100000000>, <100000000>, 407 <100000000>, <100000000>, 408 <50000000>, <100000000>, 409 <100000000>, <100000000>, 410 <50000000>, <50000000>, 411 <50000000>, <50000000>, 412 <24000000>, <600000000>, 413 <491520000>, <1200000000>, 414 <150000000>, <75000000>, 415 <75000000>, <150000000>, 416 <75000000>, <75000000>, 417 <300000000>, <100000000>, 418 <300000000>, <200000000>, 419 <400000000>, <500000000>, 420 <200000000>, <300000000>, 421 <300000000>, <250000000>, 422 <200000000>, <100000000>, 423 <24000000>, <100000000>, 424 <150000000>, <50000000>, 425 <32768>, <32768>; 426 }; 427 428 usb2phy_grf: syscon-usb@ff450000 { 429 compatible = "rockchip,rk3328-usb2phy-grf", 430 "simple-mfd", "syscon"; 431 reg = <0x0 0xff450000 0x0 0x10000>; 432 #address-cells = <1>; 433 #size-cells = <1>; 434 435 u2phy: usb2-phy@100 { 436 compatible = "rockchip,rk3328-usb2phy"; 437 reg = <0x100 0x10>; 438 #phy-cells = <1>; 439 status = "disabled"; 440 441 u2phy_otg: otg-port { 442 #phy-cells = <0>; 443 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 446 interrupt-names = "otg-bvalid", "otg-id", 447 "linestate"; 448 status = "disabled"; 449 }; 450 451 u2phy_host: host-port { 452 #phy-cells = <0>; 453 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 454 interrupt-names = "linestate"; 455 status = "disabled"; 456 }; 457 }; 458 }; 459 460 sdmmc: rksdmmc@ff500000 { 461 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 462 reg = <0x0 0xff500000 0x0 0x4000>; 463 max-frequency = <150000000>; 464 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 465 clock-names = "biu", "ciu"; 466 fifo-depth = <0x100>; 467 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 468 status = "disabled"; 469 }; 470 471 sdio: dwmmc@ff510000 { 472 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 473 reg = <0x0 0xff510000 0x0 0x4000>; 474 max-frequency = <150000000>; 475 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 476 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 477 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 478 fifo-depth = <0x100>; 479 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 480 status = "disabled"; 481 }; 482 483 emmc: rksdmmc@ff520000 { 484 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 485 reg = <0x0 0xff520000 0x0 0x4000>; 486 max-frequency = <150000000>; 487 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 488 clock-names = "biu", "ciu"; 489 fifo-depth = <0x100>; 490 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 491 status = "disabled"; 492 }; 493 494 gmac2io: ethernet@ff540000 { 495 compatible = "rockchip,rk3328-gmac"; 496 reg = <0x0 0xff540000 0x0 0x10000>; 497 rockchip,grf = <&grf>; 498 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 499 interrupt-names = "macirq"; 500 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 501 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 502 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 503 <&cru PCLK_MAC2IO>; 504 clock-names = "stmmaceth", "mac_clk_rx", 505 "mac_clk_tx", "clk_mac_ref", 506 "clk_mac_refout", "aclk_mac", 507 "pclk_mac"; 508 resets = <&cru SRST_GMAC2IO_A>; 509 reset-names = "stmmaceth"; 510 status = "disabled"; 511 }; 512 513 usb_host0_ehci: usb@ff5c0000 { 514 compatible = "generic-ehci"; 515 reg = <0x0 0xff5c0000 0x0 0x10000>; 516 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 517 phys = <&u2phy 1>; 518 phy-names = "usb"; 519 status = "disabled"; 520 }; 521 522 usb_host0_ohci: usb@ff5d0000 { 523 compatible = "generic-ohci"; 524 reg = <0x0 0xff5d0000 0x0 0x10000>; 525 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 526 phys = <&u2phy 1>; 527 phy-names = "usb"; 528 status = "disabled"; 529 }; 530 531 usb20_otg: usb@ff580000 { 532 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 533 "snps,dwc2"; 534 reg = <0x0 0xff580000 0x0 0x40000>; 535 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 536 hnp-srp-disable; 537 dr_mode = "otg"; 538 phys = <&u2phy 0>; 539 phy-names = "usb"; 540 status = "disabled"; 541 }; 542 543 sdmmc_ext: rksdmmc@ff5f0000 { 544 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 545 reg = <0x0 0xff5f0000 0x0 0x4000>; 546 max-frequency = <150000000>; 547 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 548 clock-names = "biu", "ciu"; 549 fifo-depth = <0x100>; 550 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 551 status = "disabled"; 552 }; 553 554 usb_host0_xhci: usb@ff600000 { 555 compatible = "rockchip,rk3328-xhci"; 556 reg = <0x0 0xff600000 0x0 0x100000>; 557 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 558 snps,dis-enblslpm-quirk; 559 snps,phyif-utmi-bits = <16>; 560 snps,dis-u2-freeclk-exists-quirk; 561 snps,dis-u2-susphy-quirk; 562 status = "disabled"; 563 }; 564 565 gic: interrupt-controller@ffb70000 { 566 compatible = "arm,gic-400"; 567 #interrupt-cells = <3>; 568 #address-cells = <0>; 569 interrupt-controller; 570 reg = <0x0 0xff811000 0 0x1000>, 571 <0x0 0xff812000 0 0x2000>, 572 <0x0 0xff814000 0 0x2000>, 573 <0x0 0xff816000 0 0x2000>; 574 interrupts = <GIC_PPI 9 575 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 576 }; 577 578 pinctrl: pinctrl { 579 compatible = "rockchip,rk3328-pinctrl"; 580 rockchip,grf = <&grf>; 581 #address-cells = <2>; 582 #size-cells = <2>; 583 ranges; 584 585 gpio0: gpio0@ff210000 { 586 compatible = "rockchip,gpio-bank"; 587 reg = <0x0 0xff210000 0x0 0x100>; 588 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&cru PCLK_GPIO0>; 590 591 gpio-controller; 592 #gpio-cells = <2>; 593 594 interrupt-controller; 595 #interrupt-cells = <2>; 596 }; 597 598 gpio1: gpio1@ff220000 { 599 compatible = "rockchip,gpio-bank"; 600 reg = <0x0 0xff220000 0x0 0x100>; 601 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&cru PCLK_GPIO1>; 603 604 gpio-controller; 605 #gpio-cells = <2>; 606 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 }; 610 611 gpio2: gpio2@ff230000 { 612 compatible = "rockchip,gpio-bank"; 613 reg = <0x0 0xff230000 0x0 0x100>; 614 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&cru PCLK_GPIO2>; 616 617 gpio-controller; 618 #gpio-cells = <2>; 619 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 }; 623 624 gpio3: gpio3@ff240000 { 625 compatible = "rockchip,gpio-bank"; 626 reg = <0x0 0xff240000 0x0 0x100>; 627 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&cru PCLK_GPIO3>; 629 630 gpio-controller; 631 #gpio-cells = <2>; 632 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 }; 636 637 pcfg_pull_up: pcfg-pull-up { 638 bias-pull-up; 639 }; 640 641 pcfg_pull_down: pcfg-pull-down { 642 bias-pull-down; 643 }; 644 645 pcfg_pull_none: pcfg-pull-none { 646 bias-disable; 647 }; 648 649 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 650 bias-disable; 651 drive-strength = <2>; 652 }; 653 654 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 655 bias-pull-up; 656 drive-strength = <2>; 657 }; 658 659 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 660 bias-pull-up; 661 drive-strength = <4>; 662 }; 663 664 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 665 bias-disable; 666 drive-strength = <4>; 667 }; 668 669 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 670 bias-pull-down; 671 drive-strength = <4>; 672 }; 673 674 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 675 bias-disable; 676 drive-strength = <8>; 677 }; 678 679 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 680 bias-pull-up; 681 drive-strength = <8>; 682 }; 683 684 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 685 bias-disable; 686 drive-strength = <12>; 687 }; 688 689 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 690 bias-pull-up; 691 drive-strength = <12>; 692 }; 693 694 pcfg_output_high: pcfg-output-high { 695 output-high; 696 }; 697 698 pcfg_output_low: pcfg-output-low { 699 output-low; 700 }; 701 702 pcfg_input_high: pcfg-input-high { 703 bias-pull-up; 704 input-enable; 705 }; 706 707 pcfg_input: pcfg-input { 708 input-enable; 709 }; 710 711 i2c0 { 712 i2c0_xfer: i2c0-xfer { 713 rockchip,pins = 714 <2 24 RK_FUNC_1 &pcfg_pull_none>, 715 <2 25 RK_FUNC_1 &pcfg_pull_none>; 716 }; 717 }; 718 719 i2c1 { 720 i2c1_xfer: i2c1-xfer { 721 rockchip,pins = 722 <2 4 RK_FUNC_2 &pcfg_pull_none>, 723 <2 5 RK_FUNC_2 &pcfg_pull_none>; 724 }; 725 }; 726 727 i2c2 { 728 i2c2_xfer: i2c2-xfer { 729 rockchip,pins = 730 <2 13 RK_FUNC_1 &pcfg_pull_none>, 731 <2 14 RK_FUNC_1 &pcfg_pull_none>; 732 }; 733 }; 734 735 i2c3 { 736 i2c3_xfer: i2c3-xfer { 737 rockchip,pins = 738 <0 5 RK_FUNC_2 &pcfg_pull_none>, 739 <0 6 RK_FUNC_2 &pcfg_pull_none>; 740 }; 741 i2c3_gpio: i2c3-gpio { 742 rockchip,pins = 743 <0 5 RK_FUNC_GPIO &pcfg_pull_none>, 744 <0 6 RK_FUNC_GPIO &pcfg_pull_none>; 745 }; 746 }; 747 748 hdmi_i2c { 749 hdmii2c_xfer: hdmii2c-xfer { 750 rockchip,pins = 751 <0 5 RK_FUNC_1 &pcfg_pull_none>, 752 <0 6 RK_FUNC_1 &pcfg_pull_none>; 753 }; 754 }; 755 756 uart0 { 757 uart0_xfer: uart0-xfer { 758 rockchip,pins = 759 <1 9 RK_FUNC_1 &pcfg_pull_up>, 760 <1 8 RK_FUNC_1 &pcfg_pull_up>; 761 }; 762 763 uart0_cts: uart0-cts { 764 rockchip,pins = 765 <1 11 RK_FUNC_1 &pcfg_pull_none>; 766 }; 767 768 uart0_rts: uart0-rts { 769 rockchip,pins = 770 <1 10 RK_FUNC_1 &pcfg_pull_none>; 771 }; 772 773 uart0_rts_gpio: uart0-rts-gpio { 774 rockchip,pins = 775 <1 10 RK_FUNC_GPIO &pcfg_pull_none>; 776 }; 777 }; 778 779 uart1 { 780 uart1_xfer: uart1-xfer { 781 rockchip,pins = 782 <3 4 RK_FUNC_4 &pcfg_pull_up>, 783 <3 6 RK_FUNC_4 &pcfg_pull_up>; 784 }; 785 786 uart1_cts: uart1-cts { 787 rockchip,pins = 788 <3 7 RK_FUNC_4 &pcfg_pull_none>; 789 }; 790 791 uart1_rts: uart1-rts { 792 rockchip,pins = 793 <3 5 RK_FUNC_4 &pcfg_pull_none>; 794 }; 795 796 uart1_rts_gpio: uart1-rts-gpio { 797 rockchip,pins = 798 <3 5 RK_FUNC_GPIO &pcfg_pull_none>; 799 }; 800 }; 801 802 uart2-0 { 803 uart2m0_xfer: uart2m0-xfer { 804 rockchip,pins = 805 <1 0 RK_FUNC_2 &pcfg_pull_up>, 806 <1 1 RK_FUNC_2 &pcfg_pull_up>; 807 }; 808 }; 809 810 uart2-1 { 811 uart2m1_xfer: uart2m1-xfer { 812 rockchip,pins = 813 <2 0 RK_FUNC_1 &pcfg_pull_up>, 814 <2 1 RK_FUNC_1 &pcfg_pull_up>; 815 }; 816 }; 817 818 spi0-0 { 819 spi0m0_clk: spi0m0-clk { 820 rockchip,pins = 821 <2 8 RK_FUNC_1 &pcfg_pull_up>; 822 }; 823 824 spi0m0_cs0: spi0m0-cs0 { 825 rockchip,pins = 826 <2 11 RK_FUNC_1 &pcfg_pull_up>; 827 }; 828 829 spi0m0_tx: spi0m0-tx { 830 rockchip,pins = 831 <2 9 RK_FUNC_1 &pcfg_pull_up>; 832 }; 833 834 spi0m0_rx: spi0m0-rx { 835 rockchip,pins = 836 <2 10 RK_FUNC_1 &pcfg_pull_up>; 837 }; 838 839 spi0m0_cs1: spi0m0-cs1 { 840 rockchip,pins = 841 <2 12 RK_FUNC_1 &pcfg_pull_up>; 842 }; 843 }; 844 845 spi0-1 { 846 spi0m1_clk: spi0m1-clk { 847 rockchip,pins = 848 <3 23 RK_FUNC_2 &pcfg_pull_up>; 849 }; 850 851 spi0m1_cs0: spi0m1-cs0 { 852 rockchip,pins = 853 <3 26 RK_FUNC_2 &pcfg_pull_up>; 854 }; 855 856 spi0m1_tx: spi0m1-tx { 857 rockchip,pins = 858 <3 25 RK_FUNC_2 &pcfg_pull_up>; 859 }; 860 861 spi0m1_rx: spi0m1-rx { 862 rockchip,pins = 863 <3 24 RK_FUNC_2 &pcfg_pull_up>; 864 }; 865 866 spi0m1_cs1: spi0m1-cs1 { 867 rockchip,pins = 868 <3 27 RK_FUNC_2 &pcfg_pull_up>; 869 }; 870 }; 871 872 spi0-2 { 873 spi0m2_clk: spi0m2-clk { 874 rockchip,pins = 875 <3 0 RK_FUNC_4 &pcfg_pull_up>; 876 }; 877 878 spi0m2_cs0: spi0m2-cs0 { 879 rockchip,pins = 880 <3 8 RK_FUNC_3 &pcfg_pull_up>; 881 }; 882 883 spi0m2_tx: spi0m2-tx { 884 rockchip,pins = 885 <3 1 RK_FUNC_4 &pcfg_pull_up>; 886 }; 887 888 spi0m2_rx: spi0m2-rx { 889 rockchip,pins = 890 <3 2 RK_FUNC_4 &pcfg_pull_up>; 891 }; 892 }; 893 894 i2s1 { 895 i2s1_mclk: i2s1-mclk { 896 rockchip,pins = 897 <2 15 RK_FUNC_1 &pcfg_pull_none>; 898 }; 899 900 i2s1_sclk: i2s1-sclk { 901 rockchip,pins = 902 <2 18 RK_FUNC_1 &pcfg_pull_none>; 903 }; 904 905 i2s1_lrckrx: i2s1-lrckrx { 906 rockchip,pins = 907 <2 16 RK_FUNC_1 &pcfg_pull_none>; 908 }; 909 910 i2s1_lrcktx: i2s1-lrcktx { 911 rockchip,pins = 912 <2 17 RK_FUNC_1 &pcfg_pull_none>; 913 }; 914 915 i2s1_sdi: i2s1-sdi { 916 rockchip,pins = 917 <2 19 RK_FUNC_1 &pcfg_pull_none>; 918 }; 919 920 i2s1_sdo: i2s1-sdo { 921 rockchip,pins = 922 <2 23 RK_FUNC_1 &pcfg_pull_none>; 923 }; 924 925 i2s1_sdio1: i2s1-sdio1 { 926 rockchip,pins = 927 <2 20 RK_FUNC_1 &pcfg_pull_none>; 928 }; 929 930 i2s1_sdio2: i2s1-sdio2 { 931 rockchip,pins = 932 <2 21 RK_FUNC_1 &pcfg_pull_none>; 933 }; 934 935 i2s1_sdio3: i2s1-sdio3 { 936 rockchip,pins = 937 <2 22 RK_FUNC_1 &pcfg_pull_none>; 938 }; 939 940 i2s1_sleep: i2s1-sleep { 941 rockchip,pins = 942 <2 15 RK_FUNC_GPIO &pcfg_input_high>, 943 <2 16 RK_FUNC_GPIO &pcfg_input_high>, 944 <2 17 RK_FUNC_GPIO &pcfg_input_high>, 945 <2 18 RK_FUNC_GPIO &pcfg_input_high>, 946 <2 19 RK_FUNC_GPIO &pcfg_input_high>, 947 <2 20 RK_FUNC_GPIO &pcfg_input_high>, 948 <2 21 RK_FUNC_GPIO &pcfg_input_high>, 949 <2 22 RK_FUNC_GPIO &pcfg_input_high>, 950 <2 23 RK_FUNC_GPIO &pcfg_input_high>; 951 }; 952 }; 953 954 i2s2-0 { 955 i2s2m0_mclk: i2s2m0-mclk { 956 rockchip,pins = 957 <1 21 RK_FUNC_1 &pcfg_pull_none>; 958 }; 959 960 i2s2m0_sclk: i2s2m0-sclk { 961 rockchip,pins = 962 <1 22 RK_FUNC_1 &pcfg_pull_none>; 963 }; 964 965 i2s2m0_lrckrx: i2s2m0-lrckrx { 966 rockchip,pins = 967 <1 26 RK_FUNC_1 &pcfg_pull_none>; 968 }; 969 970 i2s2m0_lrcktx: i2s2m0-lrcktx { 971 rockchip,pins = 972 <1 23 RK_FUNC_1 &pcfg_pull_none>; 973 }; 974 975 i2s2m0_sdi: i2s2m0-sdi { 976 rockchip,pins = 977 <1 24 RK_FUNC_1 &pcfg_pull_none>; 978 }; 979 980 i2s2m0_sdo: i2s2m0-sdo { 981 rockchip,pins = 982 <1 25 RK_FUNC_1 &pcfg_pull_none>; 983 }; 984 985 i2s2m0_sleep: i2s2m0-sleep { 986 rockchip,pins = 987 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 988 <1 22 RK_FUNC_GPIO &pcfg_input_high>, 989 <1 26 RK_FUNC_GPIO &pcfg_input_high>, 990 <1 23 RK_FUNC_GPIO &pcfg_input_high>, 991 <1 24 RK_FUNC_GPIO &pcfg_input_high>, 992 <1 25 RK_FUNC_GPIO &pcfg_input_high>; 993 }; 994 }; 995 996 i2s2-1 { 997 i2s2m1_mclk: i2s2m1-mclk { 998 rockchip,pins = 999 <1 21 RK_FUNC_1 &pcfg_pull_none>; 1000 }; 1001 1002 i2s2m1_sclk: i2s2m1-sclk { 1003 rockchip,pins = 1004 <3 0 RK_FUNC_6 &pcfg_pull_none>; 1005 }; 1006 1007 i2s2m1_lrckrx: i2sm1-lrckrx { 1008 rockchip,pins = 1009 <3 8 RK_FUNC_6 &pcfg_pull_none>; 1010 }; 1011 1012 i2s2m1_lrcktx: i2s2m1-lrcktx { 1013 rockchip,pins = 1014 <3 8 RK_FUNC_4 &pcfg_pull_none>; 1015 }; 1016 1017 i2s2m1_sdi: i2s2m1-sdi { 1018 rockchip,pins = 1019 <3 2 RK_FUNC_6 &pcfg_pull_none>; 1020 }; 1021 1022 i2s2m1_sdo: i2s2m1-sdo { 1023 rockchip,pins = 1024 <3 1 RK_FUNC_6 &pcfg_pull_none>; 1025 }; 1026 1027 i2s2m1_sleep: i2s2m1-sleep { 1028 rockchip,pins = 1029 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 1030 <3 0 RK_FUNC_GPIO &pcfg_input_high>, 1031 <3 8 RK_FUNC_GPIO &pcfg_input_high>, 1032 <3 2 RK_FUNC_GPIO &pcfg_input_high>, 1033 <3 1 RK_FUNC_GPIO &pcfg_input_high>; 1034 }; 1035 }; 1036 1037 spdif-0 { 1038 spdifm0_tx: spdifm0-tx { 1039 rockchip,pins = 1040 <0 27 RK_FUNC_1 &pcfg_pull_none>; 1041 }; 1042 }; 1043 1044 spdif-1 { 1045 spdifm1_tx: spdifm1-tx { 1046 rockchip,pins = 1047 <2 17 RK_FUNC_2 &pcfg_pull_none>; 1048 }; 1049 }; 1050 1051 spdif-2 { 1052 spdifm2_tx: spdifm2-tx { 1053 rockchip,pins = 1054 <0 2 RK_FUNC_2 &pcfg_pull_none>; 1055 }; 1056 }; 1057 1058 sdmmc0-0 { 1059 sdmmc0m0_pwren: sdmmc0m0-pwren { 1060 rockchip,pins = 1061 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1062 }; 1063 1064 sdmmc0m0_gpio: sdmmc0m0-gpio { 1065 rockchip,pins = 1066 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1067 }; 1068 }; 1069 1070 sdmmc0-1 { 1071 sdmmc0m1_pwren: sdmmc0m1-pwren { 1072 rockchip,pins = 1073 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; 1074 }; 1075 1076 sdmmc0m1_gpio: sdmmc0m1-gpio { 1077 rockchip,pins = 1078 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1079 }; 1080 }; 1081 1082 sdmmc0 { 1083 sdmmc0_clk: sdmmc0-clk { 1084 rockchip,pins = 1085 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; 1086 }; 1087 1088 sdmmc0_cmd: sdmmc0-cmd { 1089 rockchip,pins = 1090 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; 1091 }; 1092 1093 sdmmc0_dectn: sdmmc0-dectn { 1094 rockchip,pins = 1095 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; 1096 }; 1097 1098 sdmmc0_wrprt: sdmmc0-wrprt { 1099 rockchip,pins = 1100 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1101 }; 1102 1103 sdmmc0_bus1: sdmmc0-bus1 { 1104 rockchip,pins = 1105 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; 1106 }; 1107 1108 sdmmc0_bus4: sdmmc0-bus4 { 1109 rockchip,pins = 1110 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, 1111 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, 1112 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, 1113 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; 1114 }; 1115 1116 sdmmc0_gpio: sdmmc0-gpio { 1117 rockchip,pins = 1118 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1119 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1120 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1121 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1122 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1123 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1124 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1125 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1126 }; 1127 }; 1128 1129 sdmmc0ext { 1130 sdmmc0ext_clk: sdmmc0ext-clk { 1131 rockchip,pins = 1132 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; 1133 }; 1134 1135 sdmmc0ext_cmd: sdmmc0ext-cmd { 1136 rockchip,pins = 1137 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; 1138 }; 1139 1140 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1141 rockchip,pins = 1142 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; 1143 }; 1144 1145 sdmmc0ext_dectn: sdmmc0ext-dectn { 1146 rockchip,pins = 1147 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; 1148 }; 1149 1150 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1151 rockchip,pins = 1152 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; 1153 }; 1154 1155 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1156 rockchip,pins = 1157 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, 1158 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, 1159 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, 1160 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; 1161 }; 1162 1163 sdmmc0ext_gpio: sdmmc0ext-gpio { 1164 rockchip,pins = 1165 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1166 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1167 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1168 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1169 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1170 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1171 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1172 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1173 }; 1174 }; 1175 1176 sdmmc1 { 1177 sdmmc1_clk: sdmmc1-clk { 1178 rockchip,pins = 1179 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1180 }; 1181 1182 sdmmc1_cmd: sdmmc1-cmd { 1183 rockchip,pins = 1184 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; 1185 }; 1186 1187 sdmmc1_pwren: sdmmc1-pwren { 1188 rockchip,pins = 1189 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; 1190 }; 1191 1192 sdmmc1_wrprt: sdmmc1-wrprt { 1193 rockchip,pins = 1194 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; 1195 }; 1196 1197 sdmmc1_dectn: sdmmc1-dectn { 1198 rockchip,pins = 1199 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; 1200 }; 1201 1202 sdmmc1_bus1: sdmmc1-bus1 { 1203 rockchip,pins = 1204 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; 1205 }; 1206 1207 sdmmc1_bus4: sdmmc1-bus4 { 1208 rockchip,pins = 1209 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, 1210 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, 1211 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, 1212 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; 1213 }; 1214 1215 sdmmc1_gpio: sdmmc1-gpio { 1216 rockchip,pins = 1217 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1218 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1219 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1220 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1221 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1222 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1223 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1224 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1225 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1226 }; 1227 }; 1228 1229 emmc { 1230 emmc_clk: emmc-clk { 1231 rockchip,pins = 1232 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; 1233 }; 1234 1235 emmc_cmd: emmc-cmd { 1236 rockchip,pins = 1237 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; 1238 }; 1239 1240 emmc_pwren: emmc-pwren { 1241 rockchip,pins = 1242 <3 22 RK_FUNC_2 &pcfg_pull_none>; 1243 }; 1244 1245 emmc_rstnout: emmc-rstnout { 1246 rockchip,pins = 1247 <3 20 RK_FUNC_2 &pcfg_pull_none>; 1248 }; 1249 1250 emmc_bus1: emmc-bus1 { 1251 rockchip,pins = 1252 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; 1253 }; 1254 1255 emmc_bus4: emmc-bus4 { 1256 rockchip,pins = 1257 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1258 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1259 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1260 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; 1261 }; 1262 1263 emmc_bus8: emmc-bus8 { 1264 rockchip,pins = 1265 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1266 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1267 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1268 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, 1269 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, 1270 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, 1271 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, 1272 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; 1273 }; 1274 }; 1275 1276 pwm0 { 1277 pwm0_pin: pwm0-pin { 1278 rockchip,pins = 1279 <2 4 RK_FUNC_1 &pcfg_pull_none>; 1280 }; 1281 }; 1282 1283 pwm1 { 1284 pwm1_pin: pwm1-pin { 1285 rockchip,pins = 1286 <2 5 RK_FUNC_1 &pcfg_pull_none>; 1287 }; 1288 }; 1289 1290 pwm2 { 1291 pwm2_pin: pwm2-pin { 1292 rockchip,pins = 1293 <2 6 RK_FUNC_1 &pcfg_pull_none>; 1294 }; 1295 }; 1296 1297 pwmir { 1298 pwmir_pin: pwmir-pin { 1299 rockchip,pins = 1300 <2 2 RK_FUNC_1 &pcfg_pull_none>; 1301 }; 1302 }; 1303 1304 gmac-0 { 1305 rgmiim0_pins: rgmiim0-pins { 1306 rockchip,pins = 1307 /* mac_txclk */ 1308 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 1309 /* mac_rxclk */ 1310 <0 10 RK_FUNC_1 &pcfg_pull_none>, 1311 /* mac_mdio */ 1312 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1313 /* mac_txen */ 1314 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1315 /* mac_clk */ 1316 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1317 /* mac_rxdv */ 1318 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1319 /* mac_mdc */ 1320 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1321 /* mac_rxd1 */ 1322 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1323 /* mac_rxd0 */ 1324 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1325 /* mac_txd1 */ 1326 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1327 /* mac_txd0 */ 1328 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, 1329 /* mac_rxd3 */ 1330 <0 20 RK_FUNC_1 &pcfg_pull_none>, 1331 /* mac_rxd2 */ 1332 <0 21 RK_FUNC_1 &pcfg_pull_none>, 1333 /* mac_txd3 */ 1334 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, 1335 /* mac_txd2 */ 1336 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; 1337 }; 1338 1339 rmiim0_pins: rmiim0-pins { 1340 rockchip,pins = 1341 /* mac_mdio */ 1342 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1343 /* mac_txen */ 1344 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1345 /* mac_clk */ 1346 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1347 /* mac_rxer */ 1348 <0 13 RK_FUNC_1 &pcfg_pull_none>, 1349 /* mac_rxdv */ 1350 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1351 /* mac_mdc */ 1352 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1353 /* mac_rxd1 */ 1354 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1355 /* mac_rxd0 */ 1356 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1357 /* mac_txd1 */ 1358 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1359 /* mac_txd0 */ 1360 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; 1361 }; 1362 }; 1363 1364 gmac-1 { 1365 rgmiim1_pins: rgmiim1-pins { 1366 rockchip,pins = 1367 /* mac_txclk */ 1368 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, 1369 /* mac_rxclk */ 1370 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, 1371 /* mac_mdio */ 1372 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1373 /* mac_txen */ 1374 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1375 /* mac_clk */ 1376 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1377 /* mac_rxdv */ 1378 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1379 /* mac_mdc */ 1380 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1381 /* mac_rxd1 */ 1382 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1383 /* mac_rxd0 */ 1384 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1385 /* mac_txd1 */ 1386 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1387 /* mac_txd0 */ 1388 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1389 /* mac_rxd3 */ 1390 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, 1391 /* mac_rxd2 */ 1392 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, 1393 /* mac_txd3 */ 1394 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, 1395 /* mac_txd2 */ 1396 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, 1397 1398 /* mac_txclk */ 1399 <0 8 RK_FUNC_1 &pcfg_pull_none>, 1400 /* mac_txen */ 1401 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1402 /* mac_clk */ 1403 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1404 /* mac_txd1 */ 1405 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1406 /* mac_txd0 */ 1407 <0 17 RK_FUNC_1 &pcfg_pull_none>, 1408 /* mac_txd3 */ 1409 <0 23 RK_FUNC_1 &pcfg_pull_none>, 1410 /* mac_txd2 */ 1411 <0 22 RK_FUNC_1 &pcfg_pull_none>; 1412 }; 1413 1414 rmiim1_pins: rmiim1-pins { 1415 rockchip,pins = 1416 /* mac_mdio */ 1417 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1418 /* mac_txen */ 1419 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1420 /* mac_clk */ 1421 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1422 /* mac_rxer */ 1423 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, 1424 /* mac_rxdv */ 1425 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1426 /* mac_mdc */ 1427 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1428 /* mac_rxd1 */ 1429 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1430 /* mac_rxd0 */ 1431 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1432 /* mac_txd1 */ 1433 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1434 /* mac_txd0 */ 1435 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1436 1437 /* mac_mdio */ 1438 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1439 /* mac_txen */ 1440 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1441 /* mac_clk */ 1442 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1443 /* mac_mdc */ 1444 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1445 /* mac_txd1 */ 1446 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1447 /* mac_txd0 */ 1448 <0 17 RK_FUNC_1 &pcfg_pull_none>; 1449 }; 1450 }; 1451 1452 gmac2phy { 1453 fephyled_speed100: fephyled-speed100 { 1454 rockchip,pins = 1455 <0 31 RK_FUNC_1 &pcfg_pull_none>; 1456 }; 1457 1458 fephyled_speed10: fephyled-speed10 { 1459 rockchip,pins = 1460 <0 30 RK_FUNC_1 &pcfg_pull_none>; 1461 }; 1462 1463 fephyled_duplex: fephyled-duplex { 1464 rockchip,pins = 1465 <0 30 RK_FUNC_2 &pcfg_pull_none>; 1466 }; 1467 1468 fephyled_rxm0: fephyled-rxm0 { 1469 rockchip,pins = 1470 <0 29 RK_FUNC_1 &pcfg_pull_none>; 1471 }; 1472 1473 fephyled_txm0: fephyled-txm0 { 1474 rockchip,pins = 1475 <0 29 RK_FUNC_2 &pcfg_pull_none>; 1476 }; 1477 1478 fephyled_linkm0: fephyled-linkm0 { 1479 rockchip,pins = 1480 <0 28 RK_FUNC_1 &pcfg_pull_none>; 1481 }; 1482 1483 fephyled_rxm1: fephyled-rxm1 { 1484 rockchip,pins = 1485 <2 25 RK_FUNC_2 &pcfg_pull_none>; 1486 }; 1487 1488 fephyled_txm1: fephyled-txm1 { 1489 rockchip,pins = 1490 <2 25 RK_FUNC_3 &pcfg_pull_none>; 1491 }; 1492 1493 fephyled_linkm1: fephyled-linkm1 { 1494 rockchip,pins = 1495 <2 24 RK_FUNC_2 &pcfg_pull_none>; 1496 }; 1497 }; 1498 1499 tsadc_pin { 1500 tsadc_int: tsadc-int { 1501 rockchip,pins = 1502 <2 13 RK_FUNC_2 &pcfg_pull_none>; 1503 }; 1504 tsadc_gpio: tsadc-gpio { 1505 rockchip,pins = 1506 <2 13 RK_FUNC_GPIO &pcfg_pull_none>; 1507 }; 1508 }; 1509 1510 hdmi_pin { 1511 hdmi_cec: hdmi-cec { 1512 rockchip,pins = 1513 <0 3 RK_FUNC_1 &pcfg_pull_none>; 1514 }; 1515 1516 hdmi_hpd: hdmi-hpd { 1517 rockchip,pins = 1518 <0 4 RK_FUNC_1 &pcfg_pull_down>; 1519 }; 1520 }; 1521 1522 cif-0 { 1523 dvp_d2d9_m0:dvp-d2d9-m0 { 1524 rockchip,pins = 1525 /* cif_d0 */ 1526 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1527 /* cif_d1 */ 1528 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1529 /* cif_d2 */ 1530 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1531 /* cif_d3 */ 1532 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1533 /* cif_d4 */ 1534 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1535 /* cif_d5m0 */ 1536 <3 9 RK_FUNC_2 &pcfg_pull_none>, 1537 /* cif_d6m0 */ 1538 <3 10 RK_FUNC_2 &pcfg_pull_none>, 1539 /* cif_d7m0 */ 1540 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1541 /* cif_href */ 1542 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1543 /* cif_vsync */ 1544 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1545 /* cif_clkoutm0 */ 1546 <3 3 RK_FUNC_2 &pcfg_pull_none>, 1547 /* cif_clkin */ 1548 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1549 }; 1550 }; 1551 1552 cif-1 { 1553 dvp_d2d9_m1:dvp-d2d9-m1 { 1554 rockchip,pins = 1555 /* cif_d0 */ 1556 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1557 /* cif_d1 */ 1558 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1559 /* cif_d2 */ 1560 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1561 /* cif_d3 */ 1562 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1563 /* cif_d4 */ 1564 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1565 /* cif_d5m1 */ 1566 <2 16 RK_FUNC_4 &pcfg_pull_none>, 1567 /* cif_d6m1 */ 1568 <2 17 RK_FUNC_4 &pcfg_pull_none>, 1569 /* cif_d7m1 */ 1570 <2 18 RK_FUNC_4 &pcfg_pull_none>, 1571 /* cif_href */ 1572 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1573 /* cif_vsync */ 1574 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1575 /* cif_clkoutm1 */ 1576 <2 15 RK_FUNC_4 &pcfg_pull_none>, 1577 /* cif_clkin */ 1578 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1579 }; 1580 }; 1581 }; 1582}; 1583