1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3328-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3328"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 mmc0 = &emmc; 29 mmc1 = &sdmmc; 30 mmc2 = &sdmmc_ext; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42// clocks = <&cru ARMCLK>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 }; 45 cpu1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 reg = <0x0 0x1>; 49 enable-method = "psci"; 50 }; 51 cpu2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 reg = <0x0 0x2>; 55 enable-method = "psci"; 56 }; 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x3>; 61 enable-method = "psci"; 62 }; 63 }; 64 65 cpu0_opp_table: opp_table0 { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp@408000000 { 70 opp-hz = /bits/ 64 <408000000>; 71 opp-microvolt = <950000>; 72 clock-latency-ns = <40000>; 73 opp-suspend; 74 }; 75 opp@600000000 { 76 opp-hz = /bits/ 64 <600000000>; 77 opp-microvolt = <950000>; 78 clock-latency-ns = <40000>; 79 }; 80 opp@816000000 { 81 opp-hz = /bits/ 64 <816000000>; 82 opp-microvolt = <1000000>; 83 clock-latency-ns = <40000>; 84 }; 85 opp@1008000000 { 86 opp-hz = /bits/ 64 <1008000000>; 87 opp-microvolt = <1100000>; 88 clock-latency-ns = <40000>; 89 }; 90 opp@1200000000 { 91 opp-hz = /bits/ 64 <1200000000>; 92 opp-microvolt = <1225000>; 93 clock-latency-ns = <40000>; 94 }; 95 opp@1296000000 { 96 opp-hz = /bits/ 64 <1296000000>; 97 opp-microvolt = <1300000>; 98 clock-latency-ns = <40000>; 99 }; 100 }; 101 102 arm-pmu { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 109 }; 110 111 psci { 112 compatible = "arm,psci-1.0"; 113 method = "smc"; 114 }; 115 116 timer { 117 compatible = "arm,armv8-timer"; 118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 122 }; 123 124 xin24m: xin24m { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <24000000>; 128 clock-output-names = "xin24m"; 129 }; 130 131 i2s0: i2s@ff000000 { 132 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 133 reg = <0x0 0xff000000 0x0 0x1000>; 134 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 136 clock-names = "i2s_clk", "i2s_hclk"; 137 dmas = <&dmac 11>, <&dmac 12>; 138 #dma-cells = <2>; 139 dma-names = "tx", "rx"; 140 status = "disabled"; 141 }; 142 143 i2s1: i2s@ff010000 { 144 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 145 reg = <0x0 0xff010000 0x0 0x1000>; 146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 148 clock-names = "i2s_clk", "i2s_hclk"; 149 dmas = <&dmac 14>, <&dmac 15>; 150 #dma-cells = <2>; 151 dma-names = "tx", "rx"; 152 status = "disabled"; 153 }; 154 155 i2s2: i2s@ff020000 { 156 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 157 reg = <0x0 0xff020000 0x0 0x1000>; 158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 160 clock-names = "i2s_clk", "i2s_hclk"; 161 dmas = <&dmac 0>, <&dmac 1>; 162 #dma-cells = <2>; 163 dma-names = "tx", "rx"; 164 pinctrl-names = "default", "sleep"; 165 pinctrl-0 = <&i2s2m0_mclk 166 &i2s2m0_sclk 167 &i2s2m0_lrcktx 168 &i2s2m0_lrckrx 169 &i2s2m0_sdo 170 &i2s2m0_sdi>; 171 pinctrl-1 = <&i2s2m0_sleep>; 172 status = "disabled"; 173 }; 174 175 spdif: spdif@ff030000 { 176 compatible = "rockchip,rk3328-spdif"; 177 reg = <0x0 0xff030000 0x0 0x1000>; 178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 180 clock-names = "mclk", "hclk"; 181 dmas = <&dmac 10>; 182 #dma-cells = <1>; 183 dma-names = "tx"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&spdifm2_tx>; 186 status = "disabled"; 187 }; 188 189 grf: syscon@ff100000 { 190 u-boot,dm-pre-reloc; 191 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 192 reg = <0x0 0xff100000 0x0 0x1000>; 193 #address-cells = <1>; 194 #size-cells = <1>; 195 196 io_domains: io-domains { 197 compatible = "rockchip,rk3328-io-voltage-domain"; 198 status = "disabled"; 199 }; 200 }; 201 202 uart0: serial@ff110000 { 203 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 204 reg = <0x0 0xff110000 0x0 0x100>; 205 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 207 clock-names = "baudclk", "apb_pclk"; 208 reg-shift = <2>; 209 reg-io-width = <4>; 210 dmas = <&dmac 2>, <&dmac 3>; 211 #dma-cells = <2>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 214 status = "disabled"; 215 }; 216 217 uart1: serial@ff120000 { 218 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 219 reg = <0x0 0xff120000 0x0 0x100>; 220 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 222 clock-names = "sclk_uart", "pclk_uart"; 223 reg-shift = <2>; 224 reg-io-width = <4>; 225 dmas = <&dmac 4>, <&dmac 5>; 226 #dma-cells = <2>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 229 status = "disabled"; 230 }; 231 232 uart2: serial@ff130000 { 233 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 234 reg = <0x0 0xff130000 0x0 0x100>; 235 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 237 clock-names = "baudclk", "apb_pclk"; 238 clock-frequency = <24000000>; 239 reg-shift = <2>; 240 reg-io-width = <4>; 241 dmas = <&dmac 6>, <&dmac 7>; 242 #dma-cells = <2>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&uart2m1_xfer>; 245 status = "disabled"; 246 }; 247 248 pmu: power-management@ff140000 { 249 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; 250 reg = <0x0 0xff140000 0x0 0x1000>; 251 }; 252 253 i2c0: i2c@ff150000 { 254 compatible = "rockchip,rk3328-i2c"; 255 reg = <0x0 0xff150000 0x0 0x1000>; 256 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 260 clock-names = "i2c", "pclk"; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&i2c0_xfer>; 263 status = "disabled"; 264 }; 265 266 i2c1: i2c@ff160000 { 267 compatible = "rockchip,rk3328-i2c"; 268 reg = <0x0 0xff160000 0x0 0x1000>; 269 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 273 clock-names = "i2c", "pclk"; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&i2c1_xfer>; 276 status = "disabled"; 277 }; 278 279 i2c2: i2c@ff170000 { 280 compatible = "rockchip,rk3328-i2c"; 281 reg = <0x0 0xff170000 0x0 0x1000>; 282 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 286 clock-names = "i2c", "pclk"; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&i2c2_xfer>; 289 status = "disabled"; 290 }; 291 292 i2c3: i2c@ff180000 { 293 compatible = "rockchip,rk3328-i2c"; 294 reg = <0x0 0xff180000 0x0 0x1000>; 295 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 299 clock-names = "i2c", "pclk"; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&i2c3_xfer>; 302 status = "disabled"; 303 }; 304 305 spi0: spi@ff190000 { 306 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 307 reg = <0x0 0xff190000 0x0 0x1000>; 308 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 312 clock-names = "spiclk", "apb_pclk"; 313 dmas = <&dmac 8>, <&dmac 9>; 314 #dma-cells = <2>; 315 dma-names = "tx", "rx"; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 318 status = "disabled"; 319 }; 320 321 wdt: watchdog@ff1a0000 { 322 compatible = "snps,dw-wdt"; 323 reg = <0x0 0xff1a0000 0x0 0x100>; 324 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 325 status = "disabled"; 326 }; 327 328 amba { 329 compatible = "simple-bus"; 330 #address-cells = <2>; 331 #size-cells = <2>; 332 ranges; 333 334 dmac: dmac@ff1f0000 { 335 compatible = "arm,pl330", "arm,primecell"; 336 reg = <0x0 0xff1f0000 0x0 0x4000>; 337 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&cru ACLK_DMAC>; 340 clock-names = "apb_pclk"; 341 #dma-cells = <1>; 342 }; 343 }; 344 345 saradc: saradc@ff280000 { 346 compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; 347 reg = <0x0 0xff280000 0x0 0x100>; 348 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 349 #io-channel-cells = <1>; 350 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 351 clock-names = "saradc", "apb_pclk"; 352 resets = <&cru SRST_SARADC_P>; 353 reset-names = "saradc-apb"; 354 status = "disabled"; 355 }; 356 357 dmc: dmc { 358 u-boot,dm-pre-reloc; 359 compatible = "rockchip,rk3328-dmc"; 360 reg = <0x0 0xff400000 0x0 0x1000 361 0x0 0xff780000 0x0 0x3000 362 0x0 0xff100000 0x0 0x1000 363 0x0 0xff440000 0x0 0x1000 364 0x0 0xff720000 0x0 0x1000 365 0x0 0xff798000 0x0 0x1000>; 366 }; 367 368 cru: clock-controller@ff440000 { 369 u-boot,dm-pre-reloc; 370 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 371 reg = <0x0 0xff440000 0x0 0x1000>; 372 rockchip,grf = <&grf>; 373 #clock-cells = <1>; 374 #reset-cells = <1>; 375 assigned-clocks = 376 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 377 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 378 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 379 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 380 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 381 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 382 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 383 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 384 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 385 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 386 <&cru SCLK_WIFI>, <&cru ARMCLK>, 387 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 388 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 389 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 390 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 391 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, 392 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, 393 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 394 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 395 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 396 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 397 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, 398 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 399 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; 400 assigned-clock-parents = 401 <&cru HDMIPHY>, <&cru PLL_APLL>, 402 <&cru PLL_GPLL>, <&xin24m>, 403 <&xin24m>, <&xin24m>; 404 assigned-clock-rates = 405 <0>, <61440000>, 406 <0>, <24000000>, 407 <24000000>, <24000000>, 408 <15000000>, <15000000>, 409 <100000000>, <100000000>, 410 <100000000>, <100000000>, 411 <50000000>, <100000000>, 412 <100000000>, <100000000>, 413 <50000000>, <50000000>, 414 <50000000>, <50000000>, 415 <24000000>, <600000000>, 416 <491520000>, <1200000000>, 417 <150000000>, <75000000>, 418 <75000000>, <150000000>, 419 <75000000>, <75000000>, 420 <300000000>, <100000000>, 421 <300000000>, <200000000>, 422 <400000000>, <500000000>, 423 <200000000>, <300000000>, 424 <300000000>, <250000000>, 425 <200000000>, <100000000>, 426 <24000000>, <100000000>, 427 <150000000>, <50000000>, 428 <32768>, <32768>; 429 }; 430 431 usb2phy_grf: syscon-usb@ff450000 { 432 compatible = "rockchip,rk3328-usb2phy-grf", 433 "simple-mfd", "syscon"; 434 reg = <0x0 0xff450000 0x0 0x10000>; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 438 u2phy: usb2-phy@100 { 439 compatible = "rockchip,rk3328-usb2phy"; 440 reg = <0x100 0x10>; 441 clocks = <&xin24m>; 442 clock-names = "phyclk"; 443 clock-output-names = "usb480m_phy"; 444 #clock-cells = <0>; 445 assigned-clocks = <&cru USB480M>; 446 assigned-clock-parents = <&u2phy>; 447 #phy-cells = <1>; 448 status = "disabled"; 449 450 u2phy_otg: otg-port { 451 #phy-cells = <0>; 452 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 455 interrupt-names = "otg-bvalid", "otg-id", 456 "linestate"; 457 status = "disabled"; 458 }; 459 460 u2phy_host: host-port { 461 #phy-cells = <0>; 462 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 463 interrupt-names = "linestate"; 464 status = "disabled"; 465 }; 466 }; 467 }; 468 469 sdmmc: rksdmmc@ff500000 { 470 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 471 reg = <0x0 0xff500000 0x0 0x4000>; 472 max-frequency = <150000000>; 473 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 474 clock-names = "biu", "ciu"; 475 fifo-depth = <0x100>; 476 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 477 status = "disabled"; 478 }; 479 480 sdio: dwmmc@ff510000 { 481 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 482 reg = <0x0 0xff510000 0x0 0x4000>; 483 max-frequency = <150000000>; 484 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 485 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 486 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 487 fifo-depth = <0x100>; 488 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 489 status = "disabled"; 490 }; 491 492 emmc: rksdmmc@ff520000 { 493 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 494 reg = <0x0 0xff520000 0x0 0x4000>; 495 max-frequency = <150000000>; 496 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 497 clock-names = "biu", "ciu"; 498 fifo-depth = <0x100>; 499 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 500 status = "disabled"; 501 }; 502 503 gmac2io: ethernet@ff540000 { 504 compatible = "rockchip,rk3328-gmac"; 505 reg = <0x0 0xff540000 0x0 0x10000>; 506 rockchip,grf = <&grf>; 507 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 508 interrupt-names = "macirq"; 509 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 510 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 511 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 512 <&cru PCLK_MAC2IO>; 513 clock-names = "stmmaceth", "mac_clk_rx", 514 "mac_clk_tx", "clk_mac_ref", 515 "clk_mac_refout", "aclk_mac", 516 "pclk_mac"; 517 resets = <&cru SRST_GMAC2IO_A>; 518 reset-names = "stmmaceth"; 519 status = "disabled"; 520 }; 521 522 usb_host0_ehci: usb@ff5c0000 { 523 compatible = "generic-ehci"; 524 reg = <0x0 0xff5c0000 0x0 0x10000>; 525 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 526 phys = <&u2phy 1>; 527 phy-names = "usb"; 528 status = "disabled"; 529 }; 530 531 usb_host0_ohci: usb@ff5d0000 { 532 compatible = "generic-ohci"; 533 reg = <0x0 0xff5d0000 0x0 0x10000>; 534 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 535 phys = <&u2phy 1>; 536 phy-names = "usb"; 537 status = "disabled"; 538 }; 539 540 usb20_otg: usb@ff580000 { 541 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 542 "snps,dwc2"; 543 reg = <0x0 0xff580000 0x0 0x40000>; 544 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 545 hnp-srp-disable; 546 dr_mode = "otg"; 547 phys = <&u2phy 0>; 548 phy-names = "usb"; 549 status = "disabled"; 550 }; 551 552 sdmmc_ext: rksdmmc@ff5f0000 { 553 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 554 reg = <0x0 0xff5f0000 0x0 0x4000>; 555 max-frequency = <150000000>; 556 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 557 clock-names = "biu", "ciu"; 558 fifo-depth = <0x100>; 559 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 560 status = "disabled"; 561 }; 562 563 usb_host0_xhci: usb@ff600000 { 564 compatible = "rockchip,rk3328-xhci"; 565 reg = <0x0 0xff600000 0x0 0x100000>; 566 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 567 snps,dis-enblslpm-quirk; 568 snps,phyif-utmi-bits = <16>; 569 snps,dis-u2-freeclk-exists-quirk; 570 snps,dis-u2-susphy-quirk; 571 status = "disabled"; 572 }; 573 574 gic: interrupt-controller@ffb70000 { 575 compatible = "arm,gic-400"; 576 #interrupt-cells = <3>; 577 #address-cells = <0>; 578 interrupt-controller; 579 reg = <0x0 0xff811000 0 0x1000>, 580 <0x0 0xff812000 0 0x2000>, 581 <0x0 0xff814000 0 0x2000>, 582 <0x0 0xff816000 0 0x2000>; 583 interrupts = <GIC_PPI 9 584 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 585 }; 586 587 pinctrl: pinctrl { 588 compatible = "rockchip,rk3328-pinctrl"; 589 rockchip,grf = <&grf>; 590 #address-cells = <2>; 591 #size-cells = <2>; 592 ranges; 593 594 gpio0: gpio0@ff210000 { 595 compatible = "rockchip,gpio-bank"; 596 reg = <0x0 0xff210000 0x0 0x100>; 597 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&cru PCLK_GPIO0>; 599 600 gpio-controller; 601 #gpio-cells = <2>; 602 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 }; 606 607 gpio1: gpio1@ff220000 { 608 compatible = "rockchip,gpio-bank"; 609 reg = <0x0 0xff220000 0x0 0x100>; 610 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cru PCLK_GPIO1>; 612 613 gpio-controller; 614 #gpio-cells = <2>; 615 616 interrupt-controller; 617 #interrupt-cells = <2>; 618 }; 619 620 gpio2: gpio2@ff230000 { 621 compatible = "rockchip,gpio-bank"; 622 reg = <0x0 0xff230000 0x0 0x100>; 623 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&cru PCLK_GPIO2>; 625 626 gpio-controller; 627 #gpio-cells = <2>; 628 629 interrupt-controller; 630 #interrupt-cells = <2>; 631 }; 632 633 gpio3: gpio3@ff240000 { 634 compatible = "rockchip,gpio-bank"; 635 reg = <0x0 0xff240000 0x0 0x100>; 636 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&cru PCLK_GPIO3>; 638 639 gpio-controller; 640 #gpio-cells = <2>; 641 642 interrupt-controller; 643 #interrupt-cells = <2>; 644 }; 645 646 pcfg_pull_up: pcfg-pull-up { 647 bias-pull-up; 648 }; 649 650 pcfg_pull_down: pcfg-pull-down { 651 bias-pull-down; 652 }; 653 654 pcfg_pull_none: pcfg-pull-none { 655 bias-disable; 656 }; 657 658 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 659 bias-disable; 660 drive-strength = <2>; 661 }; 662 663 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 664 bias-pull-up; 665 drive-strength = <2>; 666 }; 667 668 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 669 bias-pull-up; 670 drive-strength = <4>; 671 }; 672 673 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 674 bias-disable; 675 drive-strength = <4>; 676 }; 677 678 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 679 bias-pull-down; 680 drive-strength = <4>; 681 }; 682 683 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 684 bias-disable; 685 drive-strength = <8>; 686 }; 687 688 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 689 bias-pull-up; 690 drive-strength = <8>; 691 }; 692 693 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 694 bias-disable; 695 drive-strength = <12>; 696 }; 697 698 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 699 bias-pull-up; 700 drive-strength = <12>; 701 }; 702 703 pcfg_output_high: pcfg-output-high { 704 output-high; 705 }; 706 707 pcfg_output_low: pcfg-output-low { 708 output-low; 709 }; 710 711 pcfg_input_high: pcfg-input-high { 712 bias-pull-up; 713 input-enable; 714 }; 715 716 pcfg_input: pcfg-input { 717 input-enable; 718 }; 719 720 i2c0 { 721 i2c0_xfer: i2c0-xfer { 722 rockchip,pins = 723 <2 24 RK_FUNC_1 &pcfg_pull_none>, 724 <2 25 RK_FUNC_1 &pcfg_pull_none>; 725 }; 726 }; 727 728 i2c1 { 729 i2c1_xfer: i2c1-xfer { 730 rockchip,pins = 731 <2 4 RK_FUNC_2 &pcfg_pull_none>, 732 <2 5 RK_FUNC_2 &pcfg_pull_none>; 733 }; 734 }; 735 736 i2c2 { 737 i2c2_xfer: i2c2-xfer { 738 rockchip,pins = 739 <2 13 RK_FUNC_1 &pcfg_pull_none>, 740 <2 14 RK_FUNC_1 &pcfg_pull_none>; 741 }; 742 }; 743 744 i2c3 { 745 i2c3_xfer: i2c3-xfer { 746 rockchip,pins = 747 <0 5 RK_FUNC_2 &pcfg_pull_none>, 748 <0 6 RK_FUNC_2 &pcfg_pull_none>; 749 }; 750 i2c3_gpio: i2c3-gpio { 751 rockchip,pins = 752 <0 5 RK_FUNC_GPIO &pcfg_pull_none>, 753 <0 6 RK_FUNC_GPIO &pcfg_pull_none>; 754 }; 755 }; 756 757 hdmi_i2c { 758 hdmii2c_xfer: hdmii2c-xfer { 759 rockchip,pins = 760 <0 5 RK_FUNC_1 &pcfg_pull_none>, 761 <0 6 RK_FUNC_1 &pcfg_pull_none>; 762 }; 763 }; 764 765 uart0 { 766 uart0_xfer: uart0-xfer { 767 rockchip,pins = 768 <1 9 RK_FUNC_1 &pcfg_pull_up>, 769 <1 8 RK_FUNC_1 &pcfg_pull_up>; 770 }; 771 772 uart0_cts: uart0-cts { 773 rockchip,pins = 774 <1 11 RK_FUNC_1 &pcfg_pull_none>; 775 }; 776 777 uart0_rts: uart0-rts { 778 rockchip,pins = 779 <1 10 RK_FUNC_1 &pcfg_pull_none>; 780 }; 781 782 uart0_rts_gpio: uart0-rts-gpio { 783 rockchip,pins = 784 <1 10 RK_FUNC_GPIO &pcfg_pull_none>; 785 }; 786 }; 787 788 uart1 { 789 uart1_xfer: uart1-xfer { 790 rockchip,pins = 791 <3 4 RK_FUNC_4 &pcfg_pull_up>, 792 <3 6 RK_FUNC_4 &pcfg_pull_up>; 793 }; 794 795 uart1_cts: uart1-cts { 796 rockchip,pins = 797 <3 7 RK_FUNC_4 &pcfg_pull_none>; 798 }; 799 800 uart1_rts: uart1-rts { 801 rockchip,pins = 802 <3 5 RK_FUNC_4 &pcfg_pull_none>; 803 }; 804 805 uart1_rts_gpio: uart1-rts-gpio { 806 rockchip,pins = 807 <3 5 RK_FUNC_GPIO &pcfg_pull_none>; 808 }; 809 }; 810 811 uart2-0 { 812 uart2m0_xfer: uart2m0-xfer { 813 rockchip,pins = 814 <1 0 RK_FUNC_2 &pcfg_pull_up>, 815 <1 1 RK_FUNC_2 &pcfg_pull_up>; 816 }; 817 }; 818 819 uart2-1 { 820 uart2m1_xfer: uart2m1-xfer { 821 rockchip,pins = 822 <2 0 RK_FUNC_1 &pcfg_pull_up>, 823 <2 1 RK_FUNC_1 &pcfg_pull_up>; 824 }; 825 }; 826 827 spi0-0 { 828 spi0m0_clk: spi0m0-clk { 829 rockchip,pins = 830 <2 8 RK_FUNC_1 &pcfg_pull_up>; 831 }; 832 833 spi0m0_cs0: spi0m0-cs0 { 834 rockchip,pins = 835 <2 11 RK_FUNC_1 &pcfg_pull_up>; 836 }; 837 838 spi0m0_tx: spi0m0-tx { 839 rockchip,pins = 840 <2 9 RK_FUNC_1 &pcfg_pull_up>; 841 }; 842 843 spi0m0_rx: spi0m0-rx { 844 rockchip,pins = 845 <2 10 RK_FUNC_1 &pcfg_pull_up>; 846 }; 847 848 spi0m0_cs1: spi0m0-cs1 { 849 rockchip,pins = 850 <2 12 RK_FUNC_1 &pcfg_pull_up>; 851 }; 852 }; 853 854 spi0-1 { 855 spi0m1_clk: spi0m1-clk { 856 rockchip,pins = 857 <3 23 RK_FUNC_2 &pcfg_pull_up>; 858 }; 859 860 spi0m1_cs0: spi0m1-cs0 { 861 rockchip,pins = 862 <3 26 RK_FUNC_2 &pcfg_pull_up>; 863 }; 864 865 spi0m1_tx: spi0m1-tx { 866 rockchip,pins = 867 <3 25 RK_FUNC_2 &pcfg_pull_up>; 868 }; 869 870 spi0m1_rx: spi0m1-rx { 871 rockchip,pins = 872 <3 24 RK_FUNC_2 &pcfg_pull_up>; 873 }; 874 875 spi0m1_cs1: spi0m1-cs1 { 876 rockchip,pins = 877 <3 27 RK_FUNC_2 &pcfg_pull_up>; 878 }; 879 }; 880 881 spi0-2 { 882 spi0m2_clk: spi0m2-clk { 883 rockchip,pins = 884 <3 0 RK_FUNC_4 &pcfg_pull_up>; 885 }; 886 887 spi0m2_cs0: spi0m2-cs0 { 888 rockchip,pins = 889 <3 8 RK_FUNC_3 &pcfg_pull_up>; 890 }; 891 892 spi0m2_tx: spi0m2-tx { 893 rockchip,pins = 894 <3 1 RK_FUNC_4 &pcfg_pull_up>; 895 }; 896 897 spi0m2_rx: spi0m2-rx { 898 rockchip,pins = 899 <3 2 RK_FUNC_4 &pcfg_pull_up>; 900 }; 901 }; 902 903 i2s1 { 904 i2s1_mclk: i2s1-mclk { 905 rockchip,pins = 906 <2 15 RK_FUNC_1 &pcfg_pull_none>; 907 }; 908 909 i2s1_sclk: i2s1-sclk { 910 rockchip,pins = 911 <2 18 RK_FUNC_1 &pcfg_pull_none>; 912 }; 913 914 i2s1_lrckrx: i2s1-lrckrx { 915 rockchip,pins = 916 <2 16 RK_FUNC_1 &pcfg_pull_none>; 917 }; 918 919 i2s1_lrcktx: i2s1-lrcktx { 920 rockchip,pins = 921 <2 17 RK_FUNC_1 &pcfg_pull_none>; 922 }; 923 924 i2s1_sdi: i2s1-sdi { 925 rockchip,pins = 926 <2 19 RK_FUNC_1 &pcfg_pull_none>; 927 }; 928 929 i2s1_sdo: i2s1-sdo { 930 rockchip,pins = 931 <2 23 RK_FUNC_1 &pcfg_pull_none>; 932 }; 933 934 i2s1_sdio1: i2s1-sdio1 { 935 rockchip,pins = 936 <2 20 RK_FUNC_1 &pcfg_pull_none>; 937 }; 938 939 i2s1_sdio2: i2s1-sdio2 { 940 rockchip,pins = 941 <2 21 RK_FUNC_1 &pcfg_pull_none>; 942 }; 943 944 i2s1_sdio3: i2s1-sdio3 { 945 rockchip,pins = 946 <2 22 RK_FUNC_1 &pcfg_pull_none>; 947 }; 948 949 i2s1_sleep: i2s1-sleep { 950 rockchip,pins = 951 <2 15 RK_FUNC_GPIO &pcfg_input_high>, 952 <2 16 RK_FUNC_GPIO &pcfg_input_high>, 953 <2 17 RK_FUNC_GPIO &pcfg_input_high>, 954 <2 18 RK_FUNC_GPIO &pcfg_input_high>, 955 <2 19 RK_FUNC_GPIO &pcfg_input_high>, 956 <2 20 RK_FUNC_GPIO &pcfg_input_high>, 957 <2 21 RK_FUNC_GPIO &pcfg_input_high>, 958 <2 22 RK_FUNC_GPIO &pcfg_input_high>, 959 <2 23 RK_FUNC_GPIO &pcfg_input_high>; 960 }; 961 }; 962 963 i2s2-0 { 964 i2s2m0_mclk: i2s2m0-mclk { 965 rockchip,pins = 966 <1 21 RK_FUNC_1 &pcfg_pull_none>; 967 }; 968 969 i2s2m0_sclk: i2s2m0-sclk { 970 rockchip,pins = 971 <1 22 RK_FUNC_1 &pcfg_pull_none>; 972 }; 973 974 i2s2m0_lrckrx: i2s2m0-lrckrx { 975 rockchip,pins = 976 <1 26 RK_FUNC_1 &pcfg_pull_none>; 977 }; 978 979 i2s2m0_lrcktx: i2s2m0-lrcktx { 980 rockchip,pins = 981 <1 23 RK_FUNC_1 &pcfg_pull_none>; 982 }; 983 984 i2s2m0_sdi: i2s2m0-sdi { 985 rockchip,pins = 986 <1 24 RK_FUNC_1 &pcfg_pull_none>; 987 }; 988 989 i2s2m0_sdo: i2s2m0-sdo { 990 rockchip,pins = 991 <1 25 RK_FUNC_1 &pcfg_pull_none>; 992 }; 993 994 i2s2m0_sleep: i2s2m0-sleep { 995 rockchip,pins = 996 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 997 <1 22 RK_FUNC_GPIO &pcfg_input_high>, 998 <1 26 RK_FUNC_GPIO &pcfg_input_high>, 999 <1 23 RK_FUNC_GPIO &pcfg_input_high>, 1000 <1 24 RK_FUNC_GPIO &pcfg_input_high>, 1001 <1 25 RK_FUNC_GPIO &pcfg_input_high>; 1002 }; 1003 }; 1004 1005 i2s2-1 { 1006 i2s2m1_mclk: i2s2m1-mclk { 1007 rockchip,pins = 1008 <1 21 RK_FUNC_1 &pcfg_pull_none>; 1009 }; 1010 1011 i2s2m1_sclk: i2s2m1-sclk { 1012 rockchip,pins = 1013 <3 0 RK_FUNC_6 &pcfg_pull_none>; 1014 }; 1015 1016 i2s2m1_lrckrx: i2sm1-lrckrx { 1017 rockchip,pins = 1018 <3 8 RK_FUNC_6 &pcfg_pull_none>; 1019 }; 1020 1021 i2s2m1_lrcktx: i2s2m1-lrcktx { 1022 rockchip,pins = 1023 <3 8 RK_FUNC_4 &pcfg_pull_none>; 1024 }; 1025 1026 i2s2m1_sdi: i2s2m1-sdi { 1027 rockchip,pins = 1028 <3 2 RK_FUNC_6 &pcfg_pull_none>; 1029 }; 1030 1031 i2s2m1_sdo: i2s2m1-sdo { 1032 rockchip,pins = 1033 <3 1 RK_FUNC_6 &pcfg_pull_none>; 1034 }; 1035 1036 i2s2m1_sleep: i2s2m1-sleep { 1037 rockchip,pins = 1038 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 1039 <3 0 RK_FUNC_GPIO &pcfg_input_high>, 1040 <3 8 RK_FUNC_GPIO &pcfg_input_high>, 1041 <3 2 RK_FUNC_GPIO &pcfg_input_high>, 1042 <3 1 RK_FUNC_GPIO &pcfg_input_high>; 1043 }; 1044 }; 1045 1046 spdif-0 { 1047 spdifm0_tx: spdifm0-tx { 1048 rockchip,pins = 1049 <0 27 RK_FUNC_1 &pcfg_pull_none>; 1050 }; 1051 }; 1052 1053 spdif-1 { 1054 spdifm1_tx: spdifm1-tx { 1055 rockchip,pins = 1056 <2 17 RK_FUNC_2 &pcfg_pull_none>; 1057 }; 1058 }; 1059 1060 spdif-2 { 1061 spdifm2_tx: spdifm2-tx { 1062 rockchip,pins = 1063 <0 2 RK_FUNC_2 &pcfg_pull_none>; 1064 }; 1065 }; 1066 1067 sdmmc0-0 { 1068 sdmmc0m0_pwren: sdmmc0m0-pwren { 1069 rockchip,pins = 1070 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1071 }; 1072 1073 sdmmc0m0_gpio: sdmmc0m0-gpio { 1074 rockchip,pins = 1075 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1076 }; 1077 }; 1078 1079 sdmmc0-1 { 1080 sdmmc0m1_pwren: sdmmc0m1-pwren { 1081 rockchip,pins = 1082 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; 1083 }; 1084 1085 sdmmc0m1_gpio: sdmmc0m1-gpio { 1086 rockchip,pins = 1087 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1088 }; 1089 }; 1090 1091 sdmmc0 { 1092 sdmmc0_clk: sdmmc0-clk { 1093 rockchip,pins = 1094 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; 1095 }; 1096 1097 sdmmc0_cmd: sdmmc0-cmd { 1098 rockchip,pins = 1099 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; 1100 }; 1101 1102 sdmmc0_dectn: sdmmc0-dectn { 1103 rockchip,pins = 1104 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; 1105 }; 1106 1107 sdmmc0_wrprt: sdmmc0-wrprt { 1108 rockchip,pins = 1109 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1110 }; 1111 1112 sdmmc0_bus1: sdmmc0-bus1 { 1113 rockchip,pins = 1114 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; 1115 }; 1116 1117 sdmmc0_bus4: sdmmc0-bus4 { 1118 rockchip,pins = 1119 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, 1120 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, 1121 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, 1122 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; 1123 }; 1124 1125 sdmmc0_gpio: sdmmc0-gpio { 1126 rockchip,pins = 1127 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1128 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1129 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1130 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1131 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1132 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1133 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1134 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1135 }; 1136 }; 1137 1138 sdmmc0ext { 1139 sdmmc0ext_clk: sdmmc0ext-clk { 1140 rockchip,pins = 1141 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; 1142 }; 1143 1144 sdmmc0ext_cmd: sdmmc0ext-cmd { 1145 rockchip,pins = 1146 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; 1147 }; 1148 1149 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1150 rockchip,pins = 1151 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; 1152 }; 1153 1154 sdmmc0ext_dectn: sdmmc0ext-dectn { 1155 rockchip,pins = 1156 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; 1157 }; 1158 1159 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1160 rockchip,pins = 1161 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; 1162 }; 1163 1164 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1165 rockchip,pins = 1166 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, 1167 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, 1168 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, 1169 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; 1170 }; 1171 1172 sdmmc0ext_gpio: sdmmc0ext-gpio { 1173 rockchip,pins = 1174 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1175 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1176 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1177 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1178 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1179 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1180 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1181 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1182 }; 1183 }; 1184 1185 sdmmc1 { 1186 sdmmc1_clk: sdmmc1-clk { 1187 rockchip,pins = 1188 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1189 }; 1190 1191 sdmmc1_cmd: sdmmc1-cmd { 1192 rockchip,pins = 1193 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; 1194 }; 1195 1196 sdmmc1_pwren: sdmmc1-pwren { 1197 rockchip,pins = 1198 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; 1199 }; 1200 1201 sdmmc1_wrprt: sdmmc1-wrprt { 1202 rockchip,pins = 1203 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; 1204 }; 1205 1206 sdmmc1_dectn: sdmmc1-dectn { 1207 rockchip,pins = 1208 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; 1209 }; 1210 1211 sdmmc1_bus1: sdmmc1-bus1 { 1212 rockchip,pins = 1213 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; 1214 }; 1215 1216 sdmmc1_bus4: sdmmc1-bus4 { 1217 rockchip,pins = 1218 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, 1219 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, 1220 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, 1221 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; 1222 }; 1223 1224 sdmmc1_gpio: sdmmc1-gpio { 1225 rockchip,pins = 1226 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1227 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1228 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1229 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1230 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1231 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1232 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1233 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1234 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1235 }; 1236 }; 1237 1238 emmc { 1239 emmc_clk: emmc-clk { 1240 rockchip,pins = 1241 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; 1242 }; 1243 1244 emmc_cmd: emmc-cmd { 1245 rockchip,pins = 1246 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; 1247 }; 1248 1249 emmc_pwren: emmc-pwren { 1250 rockchip,pins = 1251 <3 22 RK_FUNC_2 &pcfg_pull_none>; 1252 }; 1253 1254 emmc_rstnout: emmc-rstnout { 1255 rockchip,pins = 1256 <3 20 RK_FUNC_2 &pcfg_pull_none>; 1257 }; 1258 1259 emmc_bus1: emmc-bus1 { 1260 rockchip,pins = 1261 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; 1262 }; 1263 1264 emmc_bus4: emmc-bus4 { 1265 rockchip,pins = 1266 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1267 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1268 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1269 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; 1270 }; 1271 1272 emmc_bus8: emmc-bus8 { 1273 rockchip,pins = 1274 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1275 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1276 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1277 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, 1278 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, 1279 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, 1280 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, 1281 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; 1282 }; 1283 }; 1284 1285 pwm0 { 1286 pwm0_pin: pwm0-pin { 1287 rockchip,pins = 1288 <2 4 RK_FUNC_1 &pcfg_pull_none>; 1289 }; 1290 }; 1291 1292 pwm1 { 1293 pwm1_pin: pwm1-pin { 1294 rockchip,pins = 1295 <2 5 RK_FUNC_1 &pcfg_pull_none>; 1296 }; 1297 }; 1298 1299 pwm2 { 1300 pwm2_pin: pwm2-pin { 1301 rockchip,pins = 1302 <2 6 RK_FUNC_1 &pcfg_pull_none>; 1303 }; 1304 }; 1305 1306 pwmir { 1307 pwmir_pin: pwmir-pin { 1308 rockchip,pins = 1309 <2 2 RK_FUNC_1 &pcfg_pull_none>; 1310 }; 1311 }; 1312 1313 gmac-0 { 1314 rgmiim0_pins: rgmiim0-pins { 1315 rockchip,pins = 1316 /* mac_txclk */ 1317 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 1318 /* mac_rxclk */ 1319 <0 10 RK_FUNC_1 &pcfg_pull_none>, 1320 /* mac_mdio */ 1321 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1322 /* mac_txen */ 1323 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1324 /* mac_clk */ 1325 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1326 /* mac_rxdv */ 1327 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1328 /* mac_mdc */ 1329 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1330 /* mac_rxd1 */ 1331 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1332 /* mac_rxd0 */ 1333 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1334 /* mac_txd1 */ 1335 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1336 /* mac_txd0 */ 1337 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, 1338 /* mac_rxd3 */ 1339 <0 20 RK_FUNC_1 &pcfg_pull_none>, 1340 /* mac_rxd2 */ 1341 <0 21 RK_FUNC_1 &pcfg_pull_none>, 1342 /* mac_txd3 */ 1343 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, 1344 /* mac_txd2 */ 1345 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; 1346 }; 1347 1348 rmiim0_pins: rmiim0-pins { 1349 rockchip,pins = 1350 /* mac_mdio */ 1351 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1352 /* mac_txen */ 1353 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1354 /* mac_clk */ 1355 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1356 /* mac_rxer */ 1357 <0 13 RK_FUNC_1 &pcfg_pull_none>, 1358 /* mac_rxdv */ 1359 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1360 /* mac_mdc */ 1361 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1362 /* mac_rxd1 */ 1363 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1364 /* mac_rxd0 */ 1365 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1366 /* mac_txd1 */ 1367 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1368 /* mac_txd0 */ 1369 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; 1370 }; 1371 }; 1372 1373 gmac-1 { 1374 rgmiim1_pins: rgmiim1-pins { 1375 rockchip,pins = 1376 /* mac_txclk */ 1377 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, 1378 /* mac_rxclk */ 1379 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, 1380 /* mac_mdio */ 1381 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1382 /* mac_txen */ 1383 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1384 /* mac_clk */ 1385 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1386 /* mac_rxdv */ 1387 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1388 /* mac_mdc */ 1389 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1390 /* mac_rxd1 */ 1391 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1392 /* mac_rxd0 */ 1393 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1394 /* mac_txd1 */ 1395 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1396 /* mac_txd0 */ 1397 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1398 /* mac_rxd3 */ 1399 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, 1400 /* mac_rxd2 */ 1401 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, 1402 /* mac_txd3 */ 1403 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, 1404 /* mac_txd2 */ 1405 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, 1406 1407 /* mac_txclk */ 1408 <0 8 RK_FUNC_1 &pcfg_pull_none>, 1409 /* mac_txen */ 1410 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1411 /* mac_clk */ 1412 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1413 /* mac_txd1 */ 1414 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1415 /* mac_txd0 */ 1416 <0 17 RK_FUNC_1 &pcfg_pull_none>, 1417 /* mac_txd3 */ 1418 <0 23 RK_FUNC_1 &pcfg_pull_none>, 1419 /* mac_txd2 */ 1420 <0 22 RK_FUNC_1 &pcfg_pull_none>; 1421 }; 1422 1423 rmiim1_pins: rmiim1-pins { 1424 rockchip,pins = 1425 /* mac_mdio */ 1426 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1427 /* mac_txen */ 1428 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1429 /* mac_clk */ 1430 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1431 /* mac_rxer */ 1432 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, 1433 /* mac_rxdv */ 1434 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1435 /* mac_mdc */ 1436 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1437 /* mac_rxd1 */ 1438 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1439 /* mac_rxd0 */ 1440 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1441 /* mac_txd1 */ 1442 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1443 /* mac_txd0 */ 1444 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1445 1446 /* mac_mdio */ 1447 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1448 /* mac_txen */ 1449 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1450 /* mac_clk */ 1451 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1452 /* mac_mdc */ 1453 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1454 /* mac_txd1 */ 1455 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1456 /* mac_txd0 */ 1457 <0 17 RK_FUNC_1 &pcfg_pull_none>; 1458 }; 1459 }; 1460 1461 gmac2phy { 1462 fephyled_speed100: fephyled-speed100 { 1463 rockchip,pins = 1464 <0 31 RK_FUNC_1 &pcfg_pull_none>; 1465 }; 1466 1467 fephyled_speed10: fephyled-speed10 { 1468 rockchip,pins = 1469 <0 30 RK_FUNC_1 &pcfg_pull_none>; 1470 }; 1471 1472 fephyled_duplex: fephyled-duplex { 1473 rockchip,pins = 1474 <0 30 RK_FUNC_2 &pcfg_pull_none>; 1475 }; 1476 1477 fephyled_rxm0: fephyled-rxm0 { 1478 rockchip,pins = 1479 <0 29 RK_FUNC_1 &pcfg_pull_none>; 1480 }; 1481 1482 fephyled_txm0: fephyled-txm0 { 1483 rockchip,pins = 1484 <0 29 RK_FUNC_2 &pcfg_pull_none>; 1485 }; 1486 1487 fephyled_linkm0: fephyled-linkm0 { 1488 rockchip,pins = 1489 <0 28 RK_FUNC_1 &pcfg_pull_none>; 1490 }; 1491 1492 fephyled_rxm1: fephyled-rxm1 { 1493 rockchip,pins = 1494 <2 25 RK_FUNC_2 &pcfg_pull_none>; 1495 }; 1496 1497 fephyled_txm1: fephyled-txm1 { 1498 rockchip,pins = 1499 <2 25 RK_FUNC_3 &pcfg_pull_none>; 1500 }; 1501 1502 fephyled_linkm1: fephyled-linkm1 { 1503 rockchip,pins = 1504 <2 24 RK_FUNC_2 &pcfg_pull_none>; 1505 }; 1506 }; 1507 1508 tsadc_pin { 1509 tsadc_int: tsadc-int { 1510 rockchip,pins = 1511 <2 13 RK_FUNC_2 &pcfg_pull_none>; 1512 }; 1513 tsadc_gpio: tsadc-gpio { 1514 rockchip,pins = 1515 <2 13 RK_FUNC_GPIO &pcfg_pull_none>; 1516 }; 1517 }; 1518 1519 hdmi_pin { 1520 hdmi_cec: hdmi-cec { 1521 rockchip,pins = 1522 <0 3 RK_FUNC_1 &pcfg_pull_none>; 1523 }; 1524 1525 hdmi_hpd: hdmi-hpd { 1526 rockchip,pins = 1527 <0 4 RK_FUNC_1 &pcfg_pull_down>; 1528 }; 1529 }; 1530 1531 cif-0 { 1532 dvp_d2d9_m0:dvp-d2d9-m0 { 1533 rockchip,pins = 1534 /* cif_d0 */ 1535 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1536 /* cif_d1 */ 1537 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1538 /* cif_d2 */ 1539 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1540 /* cif_d3 */ 1541 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1542 /* cif_d4 */ 1543 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1544 /* cif_d5m0 */ 1545 <3 9 RK_FUNC_2 &pcfg_pull_none>, 1546 /* cif_d6m0 */ 1547 <3 10 RK_FUNC_2 &pcfg_pull_none>, 1548 /* cif_d7m0 */ 1549 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1550 /* cif_href */ 1551 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1552 /* cif_vsync */ 1553 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1554 /* cif_clkoutm0 */ 1555 <3 3 RK_FUNC_2 &pcfg_pull_none>, 1556 /* cif_clkin */ 1557 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1558 }; 1559 }; 1560 1561 cif-1 { 1562 dvp_d2d9_m1:dvp-d2d9-m1 { 1563 rockchip,pins = 1564 /* cif_d0 */ 1565 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1566 /* cif_d1 */ 1567 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1568 /* cif_d2 */ 1569 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1570 /* cif_d3 */ 1571 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1572 /* cif_d4 */ 1573 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1574 /* cif_d5m1 */ 1575 <2 16 RK_FUNC_4 &pcfg_pull_none>, 1576 /* cif_d6m1 */ 1577 <2 17 RK_FUNC_4 &pcfg_pull_none>, 1578 /* cif_d7m1 */ 1579 <2 18 RK_FUNC_4 &pcfg_pull_none>, 1580 /* cif_href */ 1581 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1582 /* cif_vsync */ 1583 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1584 /* cif_clkoutm1 */ 1585 <2 15 RK_FUNC_4 &pcfg_pull_none>, 1586 /* cif_clkin */ 1587 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1588 }; 1589 }; 1590 }; 1591}; 1592