1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3328-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3328"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 mmc0 = &emmc; 29 mmc1 = &sdmmc; 30 mmc2 = &sdmmc_ext; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42// clocks = <&cru ARMCLK>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 }; 45 cpu1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 reg = <0x0 0x1>; 49 enable-method = "psci"; 50 }; 51 cpu2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 reg = <0x0 0x2>; 55 enable-method = "psci"; 56 }; 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x3>; 61 enable-method = "psci"; 62 }; 63 }; 64 65 cpu0_opp_table: opp_table0 { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp@408000000 { 70 opp-hz = /bits/ 64 <408000000>; 71 opp-microvolt = <950000>; 72 clock-latency-ns = <40000>; 73 opp-suspend; 74 }; 75 opp@600000000 { 76 opp-hz = /bits/ 64 <600000000>; 77 opp-microvolt = <950000>; 78 clock-latency-ns = <40000>; 79 }; 80 opp@816000000 { 81 opp-hz = /bits/ 64 <816000000>; 82 opp-microvolt = <1000000>; 83 clock-latency-ns = <40000>; 84 }; 85 opp@1008000000 { 86 opp-hz = /bits/ 64 <1008000000>; 87 opp-microvolt = <1100000>; 88 clock-latency-ns = <40000>; 89 }; 90 opp@1200000000 { 91 opp-hz = /bits/ 64 <1200000000>; 92 opp-microvolt = <1225000>; 93 clock-latency-ns = <40000>; 94 }; 95 opp@1296000000 { 96 opp-hz = /bits/ 64 <1296000000>; 97 opp-microvolt = <1300000>; 98 clock-latency-ns = <40000>; 99 }; 100 }; 101 102 arm-pmu { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 109 }; 110 111 psci { 112 compatible = "arm,psci-1.0"; 113 method = "smc"; 114 }; 115 116 timer { 117 compatible = "arm,armv8-timer"; 118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 122 }; 123 124 xin24m: xin24m { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <24000000>; 128 clock-output-names = "xin24m"; 129 }; 130 131 i2s0: i2s@ff000000 { 132 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 133 reg = <0x0 0xff000000 0x0 0x1000>; 134 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 136 clock-names = "i2s_clk", "i2s_hclk"; 137 dmas = <&dmac 11>, <&dmac 12>; 138 #dma-cells = <2>; 139 dma-names = "tx", "rx"; 140 status = "disabled"; 141 }; 142 143 i2s1: i2s@ff010000 { 144 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 145 reg = <0x0 0xff010000 0x0 0x1000>; 146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 148 clock-names = "i2s_clk", "i2s_hclk"; 149 dmas = <&dmac 14>, <&dmac 15>; 150 #dma-cells = <2>; 151 dma-names = "tx", "rx"; 152 status = "disabled"; 153 }; 154 155 i2s2: i2s@ff020000 { 156 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 157 reg = <0x0 0xff020000 0x0 0x1000>; 158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 160 clock-names = "i2s_clk", "i2s_hclk"; 161 dmas = <&dmac 0>, <&dmac 1>; 162 #dma-cells = <2>; 163 dma-names = "tx", "rx"; 164 pinctrl-names = "default", "sleep"; 165 pinctrl-0 = <&i2s2m0_mclk 166 &i2s2m0_sclk 167 &i2s2m0_lrcktx 168 &i2s2m0_lrckrx 169 &i2s2m0_sdo 170 &i2s2m0_sdi>; 171 pinctrl-1 = <&i2s2m0_sleep>; 172 status = "disabled"; 173 }; 174 175 spdif: spdif@ff030000 { 176 compatible = "rockchip,rk3328-spdif"; 177 reg = <0x0 0xff030000 0x0 0x1000>; 178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 180 clock-names = "mclk", "hclk"; 181 dmas = <&dmac 10>; 182 #dma-cells = <1>; 183 dma-names = "tx"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&spdifm2_tx>; 186 status = "disabled"; 187 }; 188 189 grf: syscon@ff100000 { 190 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 191 reg = <0x0 0xff100000 0x0 0x1000>; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 195 io_domains: io-domains { 196 compatible = "rockchip,rk3328-io-voltage-domain"; 197 status = "disabled"; 198 }; 199 }; 200 201 uart0: serial@ff110000 { 202 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 203 reg = <0x0 0xff110000 0x0 0x100>; 204 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 206 clock-names = "baudclk", "apb_pclk"; 207 reg-shift = <2>; 208 reg-io-width = <4>; 209 dmas = <&dmac 2>, <&dmac 3>; 210 #dma-cells = <2>; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 213 status = "disabled"; 214 }; 215 216 uart1: serial@ff120000 { 217 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 218 reg = <0x0 0xff120000 0x0 0x100>; 219 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 221 clock-names = "sclk_uart", "pclk_uart"; 222 reg-shift = <2>; 223 reg-io-width = <4>; 224 dmas = <&dmac 4>, <&dmac 5>; 225 #dma-cells = <2>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 228 status = "disabled"; 229 }; 230 231 uart2: serial@ff130000 { 232 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 233 reg = <0x0 0xff130000 0x0 0x100>; 234 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 236 clock-names = "baudclk", "apb_pclk"; 237 clock-frequency = <24000000>; 238 reg-shift = <2>; 239 reg-io-width = <4>; 240 dmas = <&dmac 6>, <&dmac 7>; 241 #dma-cells = <2>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&uart2m1_xfer>; 244 status = "disabled"; 245 }; 246 247 pmu: power-management@ff140000 { 248 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; 249 reg = <0x0 0xff140000 0x0 0x1000>; 250 }; 251 252 i2c0: i2c@ff150000 { 253 compatible = "rockchip,rk3328-i2c"; 254 reg = <0x0 0xff150000 0x0 0x1000>; 255 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 259 clock-names = "i2c", "pclk"; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&i2c0_xfer>; 262 status = "disabled"; 263 }; 264 265 i2c1: i2c@ff160000 { 266 compatible = "rockchip,rk3328-i2c"; 267 reg = <0x0 0xff160000 0x0 0x1000>; 268 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 272 clock-names = "i2c", "pclk"; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&i2c1_xfer>; 275 status = "disabled"; 276 }; 277 278 i2c2: i2c@ff170000 { 279 compatible = "rockchip,rk3328-i2c"; 280 reg = <0x0 0xff170000 0x0 0x1000>; 281 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 285 clock-names = "i2c", "pclk"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&i2c2_xfer>; 288 status = "disabled"; 289 }; 290 291 i2c3: i2c@ff180000 { 292 compatible = "rockchip,rk3328-i2c"; 293 reg = <0x0 0xff180000 0x0 0x1000>; 294 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 298 clock-names = "i2c", "pclk"; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&i2c3_xfer>; 301 status = "disabled"; 302 }; 303 304 spi0: spi@ff190000 { 305 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 306 reg = <0x0 0xff190000 0x0 0x1000>; 307 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 311 clock-names = "spiclk", "apb_pclk"; 312 dmas = <&dmac 8>, <&dmac 9>; 313 #dma-cells = <2>; 314 dma-names = "tx", "rx"; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 317 status = "disabled"; 318 }; 319 320 wdt: watchdog@ff1a0000 { 321 compatible = "snps,dw-wdt"; 322 reg = <0x0 0xff1a0000 0x0 0x100>; 323 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 324 status = "disabled"; 325 }; 326 327 amba { 328 compatible = "simple-bus"; 329 #address-cells = <2>; 330 #size-cells = <2>; 331 ranges; 332 333 dmac: dmac@ff1f0000 { 334 compatible = "arm,pl330", "arm,primecell"; 335 reg = <0x0 0xff1f0000 0x0 0x4000>; 336 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cru ACLK_DMAC>; 339 clock-names = "apb_pclk"; 340 #dma-cells = <1>; 341 }; 342 }; 343 344 saradc: saradc@ff280000 { 345 compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; 346 reg = <0x0 0xff280000 0x0 0x100>; 347 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 348 #io-channel-cells = <1>; 349 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 350 clock-names = "saradc", "apb_pclk"; 351 resets = <&cru SRST_SARADC_P>; 352 reset-names = "saradc-apb"; 353 status = "disabled"; 354 }; 355 356 dmc: dmc { 357 compatible = "rockchip,rk3328-dmc"; 358 reg = <0x0 0xff400000 0x0 0x1000 359 0x0 0xff780000 0x0 0x3000 360 0x0 0xff100000 0x0 0x1000 361 0x0 0xff440000 0x0 0x1000 362 0x0 0xff720000 0x0 0x1000 363 0x0 0xff798000 0x0 0x1000>; 364 }; 365 366 cru: clock-controller@ff440000 { 367 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 368 reg = <0x0 0xff440000 0x0 0x1000>; 369 rockchip,grf = <&grf>; 370 #clock-cells = <1>; 371 #reset-cells = <1>; 372 assigned-clocks = 373 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 374 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 375 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 376 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 377 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 378 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 379 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 380 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 381 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 382 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 383 <&cru SCLK_WIFI>, <&cru ARMCLK>, 384 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 385 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 386 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 387 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 388 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, 389 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, 390 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 391 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 392 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 393 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 394 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, 395 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 396 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; 397 assigned-clock-parents = 398 <&cru HDMIPHY>, <&cru PLL_APLL>, 399 <&cru PLL_GPLL>, <&xin24m>, 400 <&xin24m>, <&xin24m>; 401 assigned-clock-rates = 402 <0>, <61440000>, 403 <0>, <24000000>, 404 <24000000>, <24000000>, 405 <15000000>, <15000000>, 406 <100000000>, <100000000>, 407 <100000000>, <100000000>, 408 <50000000>, <100000000>, 409 <100000000>, <100000000>, 410 <50000000>, <50000000>, 411 <50000000>, <50000000>, 412 <24000000>, <600000000>, 413 <491520000>, <1200000000>, 414 <150000000>, <75000000>, 415 <75000000>, <150000000>, 416 <75000000>, <75000000>, 417 <300000000>, <100000000>, 418 <300000000>, <200000000>, 419 <400000000>, <500000000>, 420 <200000000>, <300000000>, 421 <300000000>, <250000000>, 422 <200000000>, <100000000>, 423 <24000000>, <100000000>, 424 <150000000>, <50000000>, 425 <32768>, <32768>; 426 }; 427 428 usb2phy_grf: syscon-usb@ff450000 { 429 compatible = "rockchip,rk3328-usb2phy-grf", 430 "simple-mfd", "syscon"; 431 reg = <0x0 0xff450000 0x0 0x10000>; 432 #address-cells = <1>; 433 #size-cells = <1>; 434 435 u2phy: usb2-phy@100 { 436 compatible = "rockchip,rk3328-usb2phy"; 437 reg = <0x100 0x10>; 438 #phy-cells = <1>; 439 status = "disabled"; 440 441 u2phy_otg: otg-port { 442 #phy-cells = <0>; 443 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 446 interrupt-names = "otg-bvalid", "otg-id", 447 "linestate"; 448 status = "disabled"; 449 }; 450 451 u2phy_host: host-port { 452 #phy-cells = <0>; 453 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 454 interrupt-names = "linestate"; 455 status = "disabled"; 456 }; 457 }; 458 }; 459 460 sdmmc: rksdmmc@ff500000 { 461 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 462 reg = <0x0 0xff500000 0x0 0x4000>; 463 max-frequency = <150000000>; 464 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 465 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 466 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 467 fifo-depth = <0x100>; 468 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 469 status = "disabled"; 470 }; 471 472 sdio: dwmmc@ff510000 { 473 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 474 reg = <0x0 0xff510000 0x0 0x4000>; 475 max-frequency = <150000000>; 476 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 477 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 478 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 479 fifo-depth = <0x100>; 480 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 481 status = "disabled"; 482 }; 483 484 emmc: rksdmmc@ff520000 { 485 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 486 reg = <0x0 0xff520000 0x0 0x4000>; 487 max-frequency = <150000000>; 488 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 489 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 490 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 491 fifo-depth = <0x100>; 492 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 493 status = "disabled"; 494 }; 495 496 gmac2io: ethernet@ff540000 { 497 compatible = "rockchip,rk3328-gmac"; 498 reg = <0x0 0xff540000 0x0 0x10000>; 499 rockchip,grf = <&grf>; 500 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 501 interrupt-names = "macirq"; 502 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 503 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 504 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 505 <&cru PCLK_MAC2IO>; 506 clock-names = "stmmaceth", "mac_clk_rx", 507 "mac_clk_tx", "clk_mac_ref", 508 "clk_mac_refout", "aclk_mac", 509 "pclk_mac"; 510 resets = <&cru SRST_GMAC2IO_A>; 511 reset-names = "stmmaceth"; 512 status = "disabled"; 513 }; 514 515 usb_host0_ehci: usb@ff5c0000 { 516 compatible = "generic-ehci"; 517 reg = <0x0 0xff5c0000 0x0 0x10000>; 518 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 519 phys = <&u2phy 1>; 520 phy-names = "usb"; 521 status = "disabled"; 522 }; 523 524 usb_host0_ohci: usb@ff5d0000 { 525 compatible = "generic-ohci"; 526 reg = <0x0 0xff5d0000 0x0 0x10000>; 527 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 528 phys = <&u2phy 1>; 529 phy-names = "usb"; 530 status = "disabled"; 531 }; 532 533 usb20_otg: usb@ff580000 { 534 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 535 "snps,dwc2"; 536 reg = <0x0 0xff580000 0x0 0x40000>; 537 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 538 hnp-srp-disable; 539 dr_mode = "otg"; 540 phys = <&u2phy 0>; 541 phy-names = "usb"; 542 status = "disabled"; 543 }; 544 545 sdmmc_ext: rksdmmc@ff5f0000 { 546 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 547 reg = <0x0 0xff5f0000 0x0 0x4000>; 548 max-frequency = <150000000>; 549 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 550 clock-names = "biu", "ciu"; 551 fifo-depth = <0x100>; 552 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 553 status = "disabled"; 554 }; 555 556 usb_host0_xhci: usb@ff600000 { 557 compatible = "rockchip,rk3328-xhci"; 558 reg = <0x0 0xff600000 0x0 0x100000>; 559 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 560 snps,dis-enblslpm-quirk; 561 snps,phyif-utmi-bits = <16>; 562 snps,dis-u2-freeclk-exists-quirk; 563 snps,dis-u2-susphy-quirk; 564 status = "disabled"; 565 }; 566 567 gic: interrupt-controller@ffb70000 { 568 compatible = "arm,gic-400"; 569 #interrupt-cells = <3>; 570 #address-cells = <0>; 571 interrupt-controller; 572 reg = <0x0 0xff811000 0 0x1000>, 573 <0x0 0xff812000 0 0x2000>, 574 <0x0 0xff814000 0 0x2000>, 575 <0x0 0xff816000 0 0x2000>; 576 interrupts = <GIC_PPI 9 577 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 578 }; 579 580 pinctrl: pinctrl { 581 compatible = "rockchip,rk3328-pinctrl"; 582 rockchip,grf = <&grf>; 583 #address-cells = <2>; 584 #size-cells = <2>; 585 ranges; 586 587 gpio0: gpio0@ff210000 { 588 compatible = "rockchip,gpio-bank"; 589 reg = <0x0 0xff210000 0x0 0x100>; 590 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&cru PCLK_GPIO0>; 592 593 gpio-controller; 594 #gpio-cells = <2>; 595 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 }; 599 600 gpio1: gpio1@ff220000 { 601 compatible = "rockchip,gpio-bank"; 602 reg = <0x0 0xff220000 0x0 0x100>; 603 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&cru PCLK_GPIO1>; 605 606 gpio-controller; 607 #gpio-cells = <2>; 608 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 }; 612 613 gpio2: gpio2@ff230000 { 614 compatible = "rockchip,gpio-bank"; 615 reg = <0x0 0xff230000 0x0 0x100>; 616 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&cru PCLK_GPIO2>; 618 619 gpio-controller; 620 #gpio-cells = <2>; 621 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 }; 625 626 gpio3: gpio3@ff240000 { 627 compatible = "rockchip,gpio-bank"; 628 reg = <0x0 0xff240000 0x0 0x100>; 629 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&cru PCLK_GPIO3>; 631 632 gpio-controller; 633 #gpio-cells = <2>; 634 635 interrupt-controller; 636 #interrupt-cells = <2>; 637 }; 638 639 pcfg_pull_up: pcfg-pull-up { 640 bias-pull-up; 641 }; 642 643 pcfg_pull_down: pcfg-pull-down { 644 bias-pull-down; 645 }; 646 647 pcfg_pull_none: pcfg-pull-none { 648 bias-disable; 649 }; 650 651 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 652 bias-disable; 653 drive-strength = <2>; 654 }; 655 656 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 657 bias-pull-up; 658 drive-strength = <2>; 659 }; 660 661 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 662 bias-pull-up; 663 drive-strength = <4>; 664 }; 665 666 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 667 bias-disable; 668 drive-strength = <4>; 669 }; 670 671 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 672 bias-pull-down; 673 drive-strength = <4>; 674 }; 675 676 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 677 bias-disable; 678 drive-strength = <8>; 679 }; 680 681 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 682 bias-pull-up; 683 drive-strength = <8>; 684 }; 685 686 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 687 bias-disable; 688 drive-strength = <12>; 689 }; 690 691 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 692 bias-pull-up; 693 drive-strength = <12>; 694 }; 695 696 pcfg_output_high: pcfg-output-high { 697 output-high; 698 }; 699 700 pcfg_output_low: pcfg-output-low { 701 output-low; 702 }; 703 704 pcfg_input_high: pcfg-input-high { 705 bias-pull-up; 706 input-enable; 707 }; 708 709 pcfg_input: pcfg-input { 710 input-enable; 711 }; 712 713 i2c0 { 714 i2c0_xfer: i2c0-xfer { 715 rockchip,pins = 716 <2 24 RK_FUNC_1 &pcfg_pull_none>, 717 <2 25 RK_FUNC_1 &pcfg_pull_none>; 718 }; 719 }; 720 721 i2c1 { 722 i2c1_xfer: i2c1-xfer { 723 rockchip,pins = 724 <2 4 RK_FUNC_2 &pcfg_pull_none>, 725 <2 5 RK_FUNC_2 &pcfg_pull_none>; 726 }; 727 }; 728 729 i2c2 { 730 i2c2_xfer: i2c2-xfer { 731 rockchip,pins = 732 <2 13 RK_FUNC_1 &pcfg_pull_none>, 733 <2 14 RK_FUNC_1 &pcfg_pull_none>; 734 }; 735 }; 736 737 i2c3 { 738 i2c3_xfer: i2c3-xfer { 739 rockchip,pins = 740 <0 5 RK_FUNC_2 &pcfg_pull_none>, 741 <0 6 RK_FUNC_2 &pcfg_pull_none>; 742 }; 743 i2c3_gpio: i2c3-gpio { 744 rockchip,pins = 745 <0 5 RK_FUNC_GPIO &pcfg_pull_none>, 746 <0 6 RK_FUNC_GPIO &pcfg_pull_none>; 747 }; 748 }; 749 750 hdmi_i2c { 751 hdmii2c_xfer: hdmii2c-xfer { 752 rockchip,pins = 753 <0 5 RK_FUNC_1 &pcfg_pull_none>, 754 <0 6 RK_FUNC_1 &pcfg_pull_none>; 755 }; 756 }; 757 758 uart0 { 759 uart0_xfer: uart0-xfer { 760 rockchip,pins = 761 <1 9 RK_FUNC_1 &pcfg_pull_up>, 762 <1 8 RK_FUNC_1 &pcfg_pull_up>; 763 }; 764 765 uart0_cts: uart0-cts { 766 rockchip,pins = 767 <1 11 RK_FUNC_1 &pcfg_pull_none>; 768 }; 769 770 uart0_rts: uart0-rts { 771 rockchip,pins = 772 <1 10 RK_FUNC_1 &pcfg_pull_none>; 773 }; 774 775 uart0_rts_gpio: uart0-rts-gpio { 776 rockchip,pins = 777 <1 10 RK_FUNC_GPIO &pcfg_pull_none>; 778 }; 779 }; 780 781 uart1 { 782 uart1_xfer: uart1-xfer { 783 rockchip,pins = 784 <3 4 RK_FUNC_4 &pcfg_pull_up>, 785 <3 6 RK_FUNC_4 &pcfg_pull_up>; 786 }; 787 788 uart1_cts: uart1-cts { 789 rockchip,pins = 790 <3 7 RK_FUNC_4 &pcfg_pull_none>; 791 }; 792 793 uart1_rts: uart1-rts { 794 rockchip,pins = 795 <3 5 RK_FUNC_4 &pcfg_pull_none>; 796 }; 797 798 uart1_rts_gpio: uart1-rts-gpio { 799 rockchip,pins = 800 <3 5 RK_FUNC_GPIO &pcfg_pull_none>; 801 }; 802 }; 803 804 uart2-0 { 805 uart2m0_xfer: uart2m0-xfer { 806 rockchip,pins = 807 <1 0 RK_FUNC_2 &pcfg_pull_up>, 808 <1 1 RK_FUNC_2 &pcfg_pull_up>; 809 }; 810 }; 811 812 uart2-1 { 813 uart2m1_xfer: uart2m1-xfer { 814 rockchip,pins = 815 <2 0 RK_FUNC_1 &pcfg_pull_up>, 816 <2 1 RK_FUNC_1 &pcfg_pull_up>; 817 }; 818 }; 819 820 spi0-0 { 821 spi0m0_clk: spi0m0-clk { 822 rockchip,pins = 823 <2 8 RK_FUNC_1 &pcfg_pull_up>; 824 }; 825 826 spi0m0_cs0: spi0m0-cs0 { 827 rockchip,pins = 828 <2 11 RK_FUNC_1 &pcfg_pull_up>; 829 }; 830 831 spi0m0_tx: spi0m0-tx { 832 rockchip,pins = 833 <2 9 RK_FUNC_1 &pcfg_pull_up>; 834 }; 835 836 spi0m0_rx: spi0m0-rx { 837 rockchip,pins = 838 <2 10 RK_FUNC_1 &pcfg_pull_up>; 839 }; 840 841 spi0m0_cs1: spi0m0-cs1 { 842 rockchip,pins = 843 <2 12 RK_FUNC_1 &pcfg_pull_up>; 844 }; 845 }; 846 847 spi0-1 { 848 spi0m1_clk: spi0m1-clk { 849 rockchip,pins = 850 <3 23 RK_FUNC_2 &pcfg_pull_up>; 851 }; 852 853 spi0m1_cs0: spi0m1-cs0 { 854 rockchip,pins = 855 <3 26 RK_FUNC_2 &pcfg_pull_up>; 856 }; 857 858 spi0m1_tx: spi0m1-tx { 859 rockchip,pins = 860 <3 25 RK_FUNC_2 &pcfg_pull_up>; 861 }; 862 863 spi0m1_rx: spi0m1-rx { 864 rockchip,pins = 865 <3 24 RK_FUNC_2 &pcfg_pull_up>; 866 }; 867 868 spi0m1_cs1: spi0m1-cs1 { 869 rockchip,pins = 870 <3 27 RK_FUNC_2 &pcfg_pull_up>; 871 }; 872 }; 873 874 spi0-2 { 875 spi0m2_clk: spi0m2-clk { 876 rockchip,pins = 877 <3 0 RK_FUNC_4 &pcfg_pull_up>; 878 }; 879 880 spi0m2_cs0: spi0m2-cs0 { 881 rockchip,pins = 882 <3 8 RK_FUNC_3 &pcfg_pull_up>; 883 }; 884 885 spi0m2_tx: spi0m2-tx { 886 rockchip,pins = 887 <3 1 RK_FUNC_4 &pcfg_pull_up>; 888 }; 889 890 spi0m2_rx: spi0m2-rx { 891 rockchip,pins = 892 <3 2 RK_FUNC_4 &pcfg_pull_up>; 893 }; 894 }; 895 896 i2s1 { 897 i2s1_mclk: i2s1-mclk { 898 rockchip,pins = 899 <2 15 RK_FUNC_1 &pcfg_pull_none>; 900 }; 901 902 i2s1_sclk: i2s1-sclk { 903 rockchip,pins = 904 <2 18 RK_FUNC_1 &pcfg_pull_none>; 905 }; 906 907 i2s1_lrckrx: i2s1-lrckrx { 908 rockchip,pins = 909 <2 16 RK_FUNC_1 &pcfg_pull_none>; 910 }; 911 912 i2s1_lrcktx: i2s1-lrcktx { 913 rockchip,pins = 914 <2 17 RK_FUNC_1 &pcfg_pull_none>; 915 }; 916 917 i2s1_sdi: i2s1-sdi { 918 rockchip,pins = 919 <2 19 RK_FUNC_1 &pcfg_pull_none>; 920 }; 921 922 i2s1_sdo: i2s1-sdo { 923 rockchip,pins = 924 <2 23 RK_FUNC_1 &pcfg_pull_none>; 925 }; 926 927 i2s1_sdio1: i2s1-sdio1 { 928 rockchip,pins = 929 <2 20 RK_FUNC_1 &pcfg_pull_none>; 930 }; 931 932 i2s1_sdio2: i2s1-sdio2 { 933 rockchip,pins = 934 <2 21 RK_FUNC_1 &pcfg_pull_none>; 935 }; 936 937 i2s1_sdio3: i2s1-sdio3 { 938 rockchip,pins = 939 <2 22 RK_FUNC_1 &pcfg_pull_none>; 940 }; 941 942 i2s1_sleep: i2s1-sleep { 943 rockchip,pins = 944 <2 15 RK_FUNC_GPIO &pcfg_input_high>, 945 <2 16 RK_FUNC_GPIO &pcfg_input_high>, 946 <2 17 RK_FUNC_GPIO &pcfg_input_high>, 947 <2 18 RK_FUNC_GPIO &pcfg_input_high>, 948 <2 19 RK_FUNC_GPIO &pcfg_input_high>, 949 <2 20 RK_FUNC_GPIO &pcfg_input_high>, 950 <2 21 RK_FUNC_GPIO &pcfg_input_high>, 951 <2 22 RK_FUNC_GPIO &pcfg_input_high>, 952 <2 23 RK_FUNC_GPIO &pcfg_input_high>; 953 }; 954 }; 955 956 i2s2-0 { 957 i2s2m0_mclk: i2s2m0-mclk { 958 rockchip,pins = 959 <1 21 RK_FUNC_1 &pcfg_pull_none>; 960 }; 961 962 i2s2m0_sclk: i2s2m0-sclk { 963 rockchip,pins = 964 <1 22 RK_FUNC_1 &pcfg_pull_none>; 965 }; 966 967 i2s2m0_lrckrx: i2s2m0-lrckrx { 968 rockchip,pins = 969 <1 26 RK_FUNC_1 &pcfg_pull_none>; 970 }; 971 972 i2s2m0_lrcktx: i2s2m0-lrcktx { 973 rockchip,pins = 974 <1 23 RK_FUNC_1 &pcfg_pull_none>; 975 }; 976 977 i2s2m0_sdi: i2s2m0-sdi { 978 rockchip,pins = 979 <1 24 RK_FUNC_1 &pcfg_pull_none>; 980 }; 981 982 i2s2m0_sdo: i2s2m0-sdo { 983 rockchip,pins = 984 <1 25 RK_FUNC_1 &pcfg_pull_none>; 985 }; 986 987 i2s2m0_sleep: i2s2m0-sleep { 988 rockchip,pins = 989 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 990 <1 22 RK_FUNC_GPIO &pcfg_input_high>, 991 <1 26 RK_FUNC_GPIO &pcfg_input_high>, 992 <1 23 RK_FUNC_GPIO &pcfg_input_high>, 993 <1 24 RK_FUNC_GPIO &pcfg_input_high>, 994 <1 25 RK_FUNC_GPIO &pcfg_input_high>; 995 }; 996 }; 997 998 i2s2-1 { 999 i2s2m1_mclk: i2s2m1-mclk { 1000 rockchip,pins = 1001 <1 21 RK_FUNC_1 &pcfg_pull_none>; 1002 }; 1003 1004 i2s2m1_sclk: i2s2m1-sclk { 1005 rockchip,pins = 1006 <3 0 RK_FUNC_6 &pcfg_pull_none>; 1007 }; 1008 1009 i2s2m1_lrckrx: i2sm1-lrckrx { 1010 rockchip,pins = 1011 <3 8 RK_FUNC_6 &pcfg_pull_none>; 1012 }; 1013 1014 i2s2m1_lrcktx: i2s2m1-lrcktx { 1015 rockchip,pins = 1016 <3 8 RK_FUNC_4 &pcfg_pull_none>; 1017 }; 1018 1019 i2s2m1_sdi: i2s2m1-sdi { 1020 rockchip,pins = 1021 <3 2 RK_FUNC_6 &pcfg_pull_none>; 1022 }; 1023 1024 i2s2m1_sdo: i2s2m1-sdo { 1025 rockchip,pins = 1026 <3 1 RK_FUNC_6 &pcfg_pull_none>; 1027 }; 1028 1029 i2s2m1_sleep: i2s2m1-sleep { 1030 rockchip,pins = 1031 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 1032 <3 0 RK_FUNC_GPIO &pcfg_input_high>, 1033 <3 8 RK_FUNC_GPIO &pcfg_input_high>, 1034 <3 2 RK_FUNC_GPIO &pcfg_input_high>, 1035 <3 1 RK_FUNC_GPIO &pcfg_input_high>; 1036 }; 1037 }; 1038 1039 spdif-0 { 1040 spdifm0_tx: spdifm0-tx { 1041 rockchip,pins = 1042 <0 27 RK_FUNC_1 &pcfg_pull_none>; 1043 }; 1044 }; 1045 1046 spdif-1 { 1047 spdifm1_tx: spdifm1-tx { 1048 rockchip,pins = 1049 <2 17 RK_FUNC_2 &pcfg_pull_none>; 1050 }; 1051 }; 1052 1053 spdif-2 { 1054 spdifm2_tx: spdifm2-tx { 1055 rockchip,pins = 1056 <0 2 RK_FUNC_2 &pcfg_pull_none>; 1057 }; 1058 }; 1059 1060 sdmmc0-0 { 1061 sdmmc0m0_pwren: sdmmc0m0-pwren { 1062 rockchip,pins = 1063 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1064 }; 1065 1066 sdmmc0m0_gpio: sdmmc0m0-gpio { 1067 rockchip,pins = 1068 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1069 }; 1070 }; 1071 1072 sdmmc0-1 { 1073 sdmmc0m1_pwren: sdmmc0m1-pwren { 1074 rockchip,pins = 1075 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; 1076 }; 1077 1078 sdmmc0m1_gpio: sdmmc0m1-gpio { 1079 rockchip,pins = 1080 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1081 }; 1082 }; 1083 1084 sdmmc0 { 1085 sdmmc0_clk: sdmmc0-clk { 1086 rockchip,pins = 1087 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; 1088 }; 1089 1090 sdmmc0_cmd: sdmmc0-cmd { 1091 rockchip,pins = 1092 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; 1093 }; 1094 1095 sdmmc0_dectn: sdmmc0-dectn { 1096 rockchip,pins = 1097 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; 1098 }; 1099 1100 sdmmc0_wrprt: sdmmc0-wrprt { 1101 rockchip,pins = 1102 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1103 }; 1104 1105 sdmmc0_bus1: sdmmc0-bus1 { 1106 rockchip,pins = 1107 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; 1108 }; 1109 1110 sdmmc0_bus4: sdmmc0-bus4 { 1111 rockchip,pins = 1112 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, 1113 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, 1114 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, 1115 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; 1116 }; 1117 1118 sdmmc0_gpio: sdmmc0-gpio { 1119 rockchip,pins = 1120 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1121 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1122 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1123 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1124 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1125 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1126 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1127 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1128 }; 1129 }; 1130 1131 sdmmc0ext { 1132 sdmmc0ext_clk: sdmmc0ext-clk { 1133 rockchip,pins = 1134 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; 1135 }; 1136 1137 sdmmc0ext_cmd: sdmmc0ext-cmd { 1138 rockchip,pins = 1139 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; 1140 }; 1141 1142 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1143 rockchip,pins = 1144 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; 1145 }; 1146 1147 sdmmc0ext_dectn: sdmmc0ext-dectn { 1148 rockchip,pins = 1149 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; 1150 }; 1151 1152 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1153 rockchip,pins = 1154 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; 1155 }; 1156 1157 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1158 rockchip,pins = 1159 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, 1160 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, 1161 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, 1162 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; 1163 }; 1164 1165 sdmmc0ext_gpio: sdmmc0ext-gpio { 1166 rockchip,pins = 1167 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1168 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1169 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1170 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1171 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1172 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1173 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1174 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1175 }; 1176 }; 1177 1178 sdmmc1 { 1179 sdmmc1_clk: sdmmc1-clk { 1180 rockchip,pins = 1181 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1182 }; 1183 1184 sdmmc1_cmd: sdmmc1-cmd { 1185 rockchip,pins = 1186 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; 1187 }; 1188 1189 sdmmc1_pwren: sdmmc1-pwren { 1190 rockchip,pins = 1191 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; 1192 }; 1193 1194 sdmmc1_wrprt: sdmmc1-wrprt { 1195 rockchip,pins = 1196 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; 1197 }; 1198 1199 sdmmc1_dectn: sdmmc1-dectn { 1200 rockchip,pins = 1201 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; 1202 }; 1203 1204 sdmmc1_bus1: sdmmc1-bus1 { 1205 rockchip,pins = 1206 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; 1207 }; 1208 1209 sdmmc1_bus4: sdmmc1-bus4 { 1210 rockchip,pins = 1211 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, 1212 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, 1213 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, 1214 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; 1215 }; 1216 1217 sdmmc1_gpio: sdmmc1-gpio { 1218 rockchip,pins = 1219 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1220 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1221 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1222 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1223 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1224 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1225 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1226 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1227 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1228 }; 1229 }; 1230 1231 emmc { 1232 emmc_clk: emmc-clk { 1233 rockchip,pins = 1234 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; 1235 }; 1236 1237 emmc_cmd: emmc-cmd { 1238 rockchip,pins = 1239 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; 1240 }; 1241 1242 emmc_pwren: emmc-pwren { 1243 rockchip,pins = 1244 <3 22 RK_FUNC_2 &pcfg_pull_none>; 1245 }; 1246 1247 emmc_rstnout: emmc-rstnout { 1248 rockchip,pins = 1249 <3 20 RK_FUNC_2 &pcfg_pull_none>; 1250 }; 1251 1252 emmc_bus1: emmc-bus1 { 1253 rockchip,pins = 1254 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; 1255 }; 1256 1257 emmc_bus4: emmc-bus4 { 1258 rockchip,pins = 1259 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1260 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1261 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1262 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; 1263 }; 1264 1265 emmc_bus8: emmc-bus8 { 1266 rockchip,pins = 1267 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1268 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1269 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1270 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, 1271 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, 1272 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, 1273 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, 1274 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; 1275 }; 1276 }; 1277 1278 pwm0 { 1279 pwm0_pin: pwm0-pin { 1280 rockchip,pins = 1281 <2 4 RK_FUNC_1 &pcfg_pull_none>; 1282 }; 1283 }; 1284 1285 pwm1 { 1286 pwm1_pin: pwm1-pin { 1287 rockchip,pins = 1288 <2 5 RK_FUNC_1 &pcfg_pull_none>; 1289 }; 1290 }; 1291 1292 pwm2 { 1293 pwm2_pin: pwm2-pin { 1294 rockchip,pins = 1295 <2 6 RK_FUNC_1 &pcfg_pull_none>; 1296 }; 1297 }; 1298 1299 pwmir { 1300 pwmir_pin: pwmir-pin { 1301 rockchip,pins = 1302 <2 2 RK_FUNC_1 &pcfg_pull_none>; 1303 }; 1304 }; 1305 1306 gmac-0 { 1307 rgmiim0_pins: rgmiim0-pins { 1308 rockchip,pins = 1309 /* mac_txclk */ 1310 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 1311 /* mac_rxclk */ 1312 <0 10 RK_FUNC_1 &pcfg_pull_none>, 1313 /* mac_mdio */ 1314 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1315 /* mac_txen */ 1316 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1317 /* mac_clk */ 1318 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1319 /* mac_rxdv */ 1320 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1321 /* mac_mdc */ 1322 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1323 /* mac_rxd1 */ 1324 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1325 /* mac_rxd0 */ 1326 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1327 /* mac_txd1 */ 1328 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1329 /* mac_txd0 */ 1330 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, 1331 /* mac_rxd3 */ 1332 <0 20 RK_FUNC_1 &pcfg_pull_none>, 1333 /* mac_rxd2 */ 1334 <0 21 RK_FUNC_1 &pcfg_pull_none>, 1335 /* mac_txd3 */ 1336 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, 1337 /* mac_txd2 */ 1338 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; 1339 }; 1340 1341 rmiim0_pins: rmiim0-pins { 1342 rockchip,pins = 1343 /* mac_mdio */ 1344 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1345 /* mac_txen */ 1346 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1347 /* mac_clk */ 1348 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1349 /* mac_rxer */ 1350 <0 13 RK_FUNC_1 &pcfg_pull_none>, 1351 /* mac_rxdv */ 1352 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1353 /* mac_mdc */ 1354 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1355 /* mac_rxd1 */ 1356 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1357 /* mac_rxd0 */ 1358 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1359 /* mac_txd1 */ 1360 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1361 /* mac_txd0 */ 1362 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; 1363 }; 1364 }; 1365 1366 gmac-1 { 1367 rgmiim1_pins: rgmiim1-pins { 1368 rockchip,pins = 1369 /* mac_txclk */ 1370 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, 1371 /* mac_rxclk */ 1372 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, 1373 /* mac_mdio */ 1374 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1375 /* mac_txen */ 1376 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1377 /* mac_clk */ 1378 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1379 /* mac_rxdv */ 1380 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1381 /* mac_mdc */ 1382 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1383 /* mac_rxd1 */ 1384 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1385 /* mac_rxd0 */ 1386 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1387 /* mac_txd1 */ 1388 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1389 /* mac_txd0 */ 1390 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1391 /* mac_rxd3 */ 1392 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, 1393 /* mac_rxd2 */ 1394 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, 1395 /* mac_txd3 */ 1396 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, 1397 /* mac_txd2 */ 1398 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, 1399 1400 /* mac_txclk */ 1401 <0 8 RK_FUNC_1 &pcfg_pull_none>, 1402 /* mac_txen */ 1403 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1404 /* mac_clk */ 1405 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1406 /* mac_txd1 */ 1407 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1408 /* mac_txd0 */ 1409 <0 17 RK_FUNC_1 &pcfg_pull_none>, 1410 /* mac_txd3 */ 1411 <0 23 RK_FUNC_1 &pcfg_pull_none>, 1412 /* mac_txd2 */ 1413 <0 22 RK_FUNC_1 &pcfg_pull_none>; 1414 }; 1415 1416 rmiim1_pins: rmiim1-pins { 1417 rockchip,pins = 1418 /* mac_mdio */ 1419 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1420 /* mac_txen */ 1421 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1422 /* mac_clk */ 1423 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1424 /* mac_rxer */ 1425 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, 1426 /* mac_rxdv */ 1427 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1428 /* mac_mdc */ 1429 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1430 /* mac_rxd1 */ 1431 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1432 /* mac_rxd0 */ 1433 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1434 /* mac_txd1 */ 1435 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1436 /* mac_txd0 */ 1437 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1438 1439 /* mac_mdio */ 1440 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1441 /* mac_txen */ 1442 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1443 /* mac_clk */ 1444 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1445 /* mac_mdc */ 1446 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1447 /* mac_txd1 */ 1448 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1449 /* mac_txd0 */ 1450 <0 17 RK_FUNC_1 &pcfg_pull_none>; 1451 }; 1452 }; 1453 1454 gmac2phy { 1455 fephyled_speed100: fephyled-speed100 { 1456 rockchip,pins = 1457 <0 31 RK_FUNC_1 &pcfg_pull_none>; 1458 }; 1459 1460 fephyled_speed10: fephyled-speed10 { 1461 rockchip,pins = 1462 <0 30 RK_FUNC_1 &pcfg_pull_none>; 1463 }; 1464 1465 fephyled_duplex: fephyled-duplex { 1466 rockchip,pins = 1467 <0 30 RK_FUNC_2 &pcfg_pull_none>; 1468 }; 1469 1470 fephyled_rxm0: fephyled-rxm0 { 1471 rockchip,pins = 1472 <0 29 RK_FUNC_1 &pcfg_pull_none>; 1473 }; 1474 1475 fephyled_txm0: fephyled-txm0 { 1476 rockchip,pins = 1477 <0 29 RK_FUNC_2 &pcfg_pull_none>; 1478 }; 1479 1480 fephyled_linkm0: fephyled-linkm0 { 1481 rockchip,pins = 1482 <0 28 RK_FUNC_1 &pcfg_pull_none>; 1483 }; 1484 1485 fephyled_rxm1: fephyled-rxm1 { 1486 rockchip,pins = 1487 <2 25 RK_FUNC_2 &pcfg_pull_none>; 1488 }; 1489 1490 fephyled_txm1: fephyled-txm1 { 1491 rockchip,pins = 1492 <2 25 RK_FUNC_3 &pcfg_pull_none>; 1493 }; 1494 1495 fephyled_linkm1: fephyled-linkm1 { 1496 rockchip,pins = 1497 <2 24 RK_FUNC_2 &pcfg_pull_none>; 1498 }; 1499 }; 1500 1501 tsadc_pin { 1502 tsadc_int: tsadc-int { 1503 rockchip,pins = 1504 <2 13 RK_FUNC_2 &pcfg_pull_none>; 1505 }; 1506 tsadc_gpio: tsadc-gpio { 1507 rockchip,pins = 1508 <2 13 RK_FUNC_GPIO &pcfg_pull_none>; 1509 }; 1510 }; 1511 1512 hdmi_pin { 1513 hdmi_cec: hdmi-cec { 1514 rockchip,pins = 1515 <0 3 RK_FUNC_1 &pcfg_pull_none>; 1516 }; 1517 1518 hdmi_hpd: hdmi-hpd { 1519 rockchip,pins = 1520 <0 4 RK_FUNC_1 &pcfg_pull_down>; 1521 }; 1522 }; 1523 1524 cif-0 { 1525 dvp_d2d9_m0:dvp-d2d9-m0 { 1526 rockchip,pins = 1527 /* cif_d0 */ 1528 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1529 /* cif_d1 */ 1530 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1531 /* cif_d2 */ 1532 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1533 /* cif_d3 */ 1534 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1535 /* cif_d4 */ 1536 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1537 /* cif_d5m0 */ 1538 <3 9 RK_FUNC_2 &pcfg_pull_none>, 1539 /* cif_d6m0 */ 1540 <3 10 RK_FUNC_2 &pcfg_pull_none>, 1541 /* cif_d7m0 */ 1542 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1543 /* cif_href */ 1544 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1545 /* cif_vsync */ 1546 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1547 /* cif_clkoutm0 */ 1548 <3 3 RK_FUNC_2 &pcfg_pull_none>, 1549 /* cif_clkin */ 1550 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1551 }; 1552 }; 1553 1554 cif-1 { 1555 dvp_d2d9_m1:dvp-d2d9-m1 { 1556 rockchip,pins = 1557 /* cif_d0 */ 1558 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1559 /* cif_d1 */ 1560 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1561 /* cif_d2 */ 1562 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1563 /* cif_d3 */ 1564 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1565 /* cif_d4 */ 1566 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1567 /* cif_d5m1 */ 1568 <2 16 RK_FUNC_4 &pcfg_pull_none>, 1569 /* cif_d6m1 */ 1570 <2 17 RK_FUNC_4 &pcfg_pull_none>, 1571 /* cif_d7m1 */ 1572 <2 18 RK_FUNC_4 &pcfg_pull_none>, 1573 /* cif_href */ 1574 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1575 /* cif_vsync */ 1576 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1577 /* cif_clkoutm1 */ 1578 <2 15 RK_FUNC_4 &pcfg_pull_none>, 1579 /* cif_clkin */ 1580 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1581 }; 1582 }; 1583 }; 1584}; 1585